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Change in coreboot[master]: tint: introduce the new tint build system with checksum verification
by Mike Banon (Code Review) 21 Feb '21

21 Feb '21

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44582 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... tint: introduce the new tint build system with checksum verification Three stages of the new tint build system: 1) generate_core.sh extracts the core part from buildgcc script, most importantly the checksum calculation/verification functions. 2) tintify_core.sh adds the tint-specific footer/header to the core, such as the properties of current version including its checksum. 3) tint.sh - generated and "tintified" core script - builds a tint. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2f540676521ac33558d9f1c131bd1ed70bcc82e2 --- M payloads/external/tint/Makefile A payloads/external/tint/generate_core.sh R payloads/external/tint/tint-0.04-nmu1_libpayload.patch A payloads/external/tint/tintify_core.sh 4 files changed, 252 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44582/1 diff --git a/payloads/external/tint/Makefile b/payloads/external/tint/Makefile index 9473c02..95cbd87 100644 --- a/payloads/external/tint/Makefile +++ b/payloads/external/tint/Makefile @@ -1,5 +1,25 @@ -project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.04+nmu1.tar.gz -archive_name=tint_0.04+nmu1.tar.gz +# +# TINT build system - helps to securely download TINT with a checksum verification and build it. +# + +# +# Properties of the current TINT version +# + +TINT_VERSION=0.04-nmu1 +TINT_EXT_VERSION=0.04+nmu1 +TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.t…" +TINT_ARCHIVE="tint_${TINT_VERSION}.tar.gz" +TINT_DIR="tint-${TINT_VERSION}" +TINT_CHECKSUM="7fcaa428c6d0de7096d1e4fbfd14848096ae5aad" + +# +# Locations of the input/output scripts +# + +buildgcc="./../../../util/crossgcc/buildgcc" +corescript="./core.sh" +tintified="./tint.sh" unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -10,28 +30,39 @@ all: tint -tint: patch - echo " MAKE TINT " - $(MAKE) -C tint +################################################################################ +# +# Three stages of TINT build system: +# +# 1) generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# 2) tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current version including its checksum. +# +# 3) tint.sh - generated and "tintified" core script - builds a TINT. +# +################################################################################ -patch: download - cd tint; \ - if [ -e debian ]; then \ - rm -rf debian typedefs.h Makefile; \ - touch Makefile; \ - patch -l -p1 < ../libpayload_tint.patch; \ - fi - -download: - test -d tint || { wget $(project_url); \ - tar -xvf $(archive_name); \ - rm $(archive_name); \ - mv tint-0.04+nmu1 tint; } +tint: + if [ ! -f ${tintified} ]; then \ + chmod +x "./generate_core.sh" ; \ + "./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \ + chmod +x "./tintify_core.sh" ; \ + "./tintify_core.sh" ${corescript} ${tintified} \ + ${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_CHECKSUM} ; \ + fi ; \ + chmod +x ${tintified} + ${tintified} clean: - test -d tint && $(MAKE) -C tint clean || exit 0 + test -d "./tint/" && $(MAKE) -C "./tint/" clean || exit 0 distclean: - rm -rf tint + rm -rf "./tint/" + rm -f ${corescript} + rm -f ${tintified} -.PHONY: download patch tint clean distclean +.PHONY: tint clean distclean + +# diff --git a/payloads/external/tint/generate_core.sh b/payloads/external/tint/generate_core.sh new file mode 100755 index 0000000..bb0de2d --- /dev/null +++ b/payloads/external/tint/generate_core.sh @@ -0,0 +1,102 @@ +#!/bin/sh +# +# generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +############################################################################## +# +# USAGE: +# ./generate_core.sh <buildgcc> <corescript> prepare_before_patch +# where +# buildgcc - path to input buildgcc script +# corescript - path to output core part script +# prepare_before_patch - optional argument to insert prepare_${package} +# call into the unpack_and_patch function, e.g. +# for removing some files with rm command +# in order to reduce the size of patch file +# +############################################################################## + +buildgcc="$1" +corescript="$2" +prepare_before_patch="$3" + +# +# Imports the source file fragment between start and end into the +# destination file, optionally excluding the last line if not needed +# + +import_from_file() { + source="$1" + destination="$2" + start="$3" + end="$4" + last_line_disabled="$5" + if [ -z "${last_line_disabled}" ] ; then + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" "$source" >> "$destination" + else + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" "$source" >> "$destination" + fi +} + +# +# Import the color defines together with UNAME/HALT_FOR_TOOLS variables +# + +import_from_file "$buildgcc" "$corescript" "red=" "HALT_FOR_TOOLS=0" || exit "$?" + +# +# Import the core functions +# + +FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" + +for F in $FUNCTIONS ; do + import_from_file "$buildgcc" "$corescript" "$F()" "}" || exit "$?" +done + +# +# Import a fragment where we find tar/patch/make and other essential tools +# + +import_from_file "$buildgcc" "$corescript" "# Find all the required tools" "# Allow" "last_line_disabled" || exit "$?" + +# +# Import a fragment with conditional exit if some required tools were not found +# + +import_from_file "$buildgcc" "$corescript" "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" + +# +# Avoid the unnecessary subdirectories holding a single file each +# + +sed -i -e "s/patches\///g" "$corescript" +sed -i -e "s/sum\///g" "$corescript" +sed -i -e "s/tarballs\///g" "$corescript" +sed -i -e "s/cd tarballs || exit 1//g" "$corescript" +sed -i -e "s/cd \.\.//g" "$corescript" + +# +# Get the known checksum without using a dedicated single-line file +# + +sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" "$corescript" + +# +# Update the paths printed at the error messages +# + +sed -i -e "s/util\/crossgcc\///g" "$corescript" + +# +# Insert prepare_${package} function call between the unpack and patch operations +# + +if [ ! -z "${prepare_before_patch}" ] ; then + sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript" +fi + +# diff --git a/payloads/external/tint/libpayload_tint.patch b/payloads/external/tint/tint-0.04-nmu1_libpayload.patch similarity index 100% rename from payloads/external/tint/libpayload_tint.patch rename to payloads/external/tint/tint-0.04-nmu1_libpayload.patch diff --git a/payloads/external/tint/tintify_core.sh b/payloads/external/tint/tintify_core.sh new file mode 100755 index 0000000..77abc14 --- /dev/null +++ b/payloads/external/tint/tintify_core.sh @@ -0,0 +1,98 @@ +#!/bin/sh +# +# tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current TINT version including its checksum. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +################################################################################ +# +# USAGE: +# ./tintify_core.sh <corescript> <tintified> \ +# <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> +# where +# corescript - path to input core script +# tintified - path to output tint script +# +################################################################################ + +corescript="$1" +tintified="$2" + +# +# TINT-specific header +# + +# +# Insert the properties of the current TINT version +# + +echo "#!/bin/sh" > "$tintified" +echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified" +echo "TINT_ARCHIVE=${4}" >> "$tintified" +echo "TINT_DIR=${5}" >> "$tintified" +echo "TINT_CHECKSUM=${6}" >> "$tintified" + +# +# Add the replace_plus_with_minus() function - needed to fix the version number +# + +echo "replace_plus_with_minus() {" >> "$tintified" +echo "for x in *\"+\"*; do" >> "$tintified" +echo "y=\$(printf %sa \"\$x\" | tr \"+\" \"-\")" >> "$tintified" +echo "mv -- \"\$x\" \"\${y%a}\"" >> "$tintified" +echo "done" >> "$tintified" +echo "}" >> "$tintified" + +# +# Add the prepare_TINT() function, it will remove the unneeded debian directory +# as well as typedefs.h and old Makefile to significantly reduce the patch size +# + +echo "prepare_TINT() {" >> "$tintified" +echo "replace_plus_with_minus" >> "$tintified" +echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ] ; then" >> "$tintified" +echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "touch ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "fi" >> "$tintified" +echo "}" >> "$tintified" + +# +# Importing the core script +# + +cat "$corescript" >> "$tintified" + +# +# download() function adjustments - became necessary after a version number fix +# + +sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" "$tintified" +sed -i -e "s/downloading from \$archive/&_link/g" "$tintified" +sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" "$tintified" + +# +# TINT-specific footer +# + +echo "if [ ! -d tint ] ; then" >> "$tintified" + +echo "printf \"Downloading and verifying TINT tarball ... \\n\"" >> "$tintified" +echo "download TINT || exit \"\$?\"" >> "$tintified" +echo "verify_hash TINT \${TINT_CHECKSUM} || exit \"\$?\"" >> "$tintified" +echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "printf \"Unpacking and patching TINT... \\n\"" >> "$tintified" +echo "unpack_and_patch TINT || exit 1" >> "$tintified" +echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "mv ./\${TINT_DIR} ./tint" >> "$tintified" +echo "fi" >> "$tintified" + +echo "printf \"Building TINT ... \\n\"" >> "$tintified" +echo "make -C ./tint" >> "$tintified" +echo "printf \"TINT built ... \${green}ok\${NC}\\n\"" >> "$tintified" + +chmod +x "$tintified" + +# -- To view, visit https://review.coreboot.org/c/coreboot/+/44582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f540676521ac33558d9f1c131bd1ed70bcc82e2 Gerrit-Change-Number: 44582 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/amd/hda: Move HDA PCI device from DSDT to SSDT
by Furquan Shaikh (Code Review) 19 Feb '21

19 Feb '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40785 ) Change subject: soc/amd/hda: Move HDA PCI device from DSDT to SSDT ...................................................................... soc/amd/hda: Move HDA PCI device from DSDT to SSDT This change adds support in common block HDA driver to add a PCI device for HDA in SSDT and removes the HDA device from DSDT for Stoneyridge and Picasso. _INI method is still retained in stoneyridge since I am unsure why it was added. In order to support the _INI method, HDA driver makes a callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks required for the HDA device. This callback is implemented by Stoneyridge to provide the _INI method which retains the same functionality for HDA device. BUG=b:153858769,b:155132752 TEST=Verified that audio still works fine on Trembyle. Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/hda/hda.c A src/soc/amd/common/block/include/amdblocks/hda.h M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/northbridge.c 5 files changed, 79 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/40785/1 diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index ea42b84..2028f09 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <arch/acpigen.h> +#include <amdblocks/hda.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -19,12 +21,23 @@ return "AZHD"; } +__weak void hda_soc_ssdt_quirks(const struct device *dev) +{ +} + +static void hda_fill_ssdt(const struct device *dev) +{ + acpi_device_write_pci_dev(dev); + hda_soc_ssdt_quirks(dev); +} + static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .acpi_name = hda_acpi_name, + .acpi_fill_ssdt = hda_fill_ssdt, }; static const struct pci_driver hdaaudio_driver __pci_driver = { diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h new file mode 100644 index 0000000..b59a7b0 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/hda.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_HDA_H__ +#define __AMDBLOCKS_HDA_H__ + +#include <device/device.h> + +/* SoC callback to add any quirks to HDA device node in SSDT. */ +void hda_soc_ssdt_quirks(const struct device *dev); + +#endif /* __AMDBLOCKS_HDA_H__ */ diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 0a3a979..67ae6f2 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -76,6 +76,3 @@ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c807601..91e43aa 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -81,40 +81,3 @@ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6c), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - If (LEqual (OSVR, 0x03)) - { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) - } - } -} /* end AZHD */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index db71509..b551426 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <assert.h> #include <amdblocks/biosram.h> +#include <amdblocks/hda.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -501,3 +503,55 @@ params->iGpuVgaMode = 0; params->GnbIoapicAddress = IO_APIC2_ADDR; } + +void hda_soc_ssdt_quirks(const struct device *dev) +{ + const char *scope = acpi_device_path(dev); + static const struct fieldlist list[] = { + FIELDLIST_OFFSET(0x42), + FIELDLIST_NAMESTR("NSDI", 1), + FIELDLIST_NAMESTR("NSDO", 1), + FIELDLIST_NAMESTR("NSEN", 1), + }; + struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100); + + assert(scope); + + acpigen_write_scope(scope); + + /* + * OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + * Field (AZPD, AnyAcc, NoLock, Preserve) { + * Offset (0x42), + * NSDI, 1, + * NSDO, 1, + * NSEN, 1, + * } + */ + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* + * Method (_INI, 0, NotSerialized) { + * If (LEqual (OSVR, 0x03)) { + * Store (Zero, NSEN) + * Store (One, NSDO) + * Store (One, NSDI) + * } + * } + */ + acpigen_write_method("_INI", 0); + + acpigen_write_if_lequal_namestr_int("OSVR", 0x03); + + acpigen_write_store_op_to_namestr(ONE_OP, "NSEN"); + acpigen_write_store_op_to_namestr(ZERO_OP, "NSDO"); + acpigen_write_store_op_to_namestr(ZERO_OP, "NSDI"); + + acpigen_pop_len(); /* If */ + + acpigen_pop_len(); /* Method _INI */ + + acpigen_pop_len(); /* Scope */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Gerrit-Change-Number: 40785 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: soc/intel/apollolake: Make SMI_STS offset macro definition consistent
by Subrata Banik (Code Review) 19 Feb '21

19 Feb '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39022 ) Change subject: soc/intel/apollolake: Make SMI_STS offset macro definition consistent ...................................................................... soc/intel/apollolake: Make SMI_STS offset macro definition consistent This patch makes all bit field macro definition for SMI_STS register (offset 0x44) be consistent i.e. ending with "_STS_BIT". Also modified relevant files where those macros are getting used. Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/smihandler.c 3 files changed, 52 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39022/1 diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 22e414c..0cf06b2 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -105,29 +105,30 @@ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) #define SMI_STS 0x44 +#define SMI_STS_BITS 32 /* Bits for SMI status */ #define ESPI_SMI_STS_BIT 28 -#define PMC_OCP_SMI_STS 27 -#define SPI_SMI_STS 26 -#define SPI_SSMI_STS 25 -#define SCC2_SMI_STS 21 -#define PCIE_SMI_STS 20 -#define SCS_SMI_STS 19 -#define HSMBUS_SMI_STS 18 -#define XHCI_SMI_STS 17 -#define SMBUS_SMI_STS 16 -#define SERIRQ_SMI_STS 15 -#define PERIODIC_SMI_STS 14 -#define TCO_SMI_STS 13 -#define MC_SMI_STS 12 -#define GPIO_UNLOCK_SMI_STS 11 -#define GPIO_SMI_STS 10 -#define FAKE_PM1_SMI_STS 8 -#define SWSMI_TMR_SMI_STS 6 -#define APM_SMI_STS 5 -#define SLP_SMI_STS 4 -#define LEGACY_USB_SMI_STS 3 -#define BIOS_SMI_STS 2 +#define PMC_OCP_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SPI_SSMI_STS_BIT 25 +#define SCC2_SMI_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SCS_SMI_STS_BIT 19 +#define HSMBUS_SMI_STS_BIT 18 +#define XHCI_SMI_STS_BIT 17 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define MC_SMI_STS_BIT 12 +#define GPIO_UNLOCK_SMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 8151afc..4a08827 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -57,27 +57,27 @@ const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { - [BIOS_SMI_STS] = "BIOS", - [LEGACY_USB_SMI_STS] = "LEGACY USB", - [SLP_SMI_STS] = "SLP_SMI", - [APM_SMI_STS] = "APM", - [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", - [FAKE_PM1_SMI_STS] = "PM1", - [GPIO_SMI_STS] = "GPIO_SMI", - [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI", - [MC_SMI_STS] = "MCSMI", - [TCO_SMI_STS] = "TCO", - [PERIODIC_SMI_STS] = "PERIODIC", - [SERIRQ_SMI_STS] = "SERIRQ", - [SMBUS_SMI_STS] = "SMBUS_SMI", - [XHCI_SMI_STS] = "XHCI", - [HSMBUS_SMI_STS] = "HOST_SMBUS", - [SCS_SMI_STS] = "SCS", - [PCIE_SMI_STS] = "PCI_EXP_SMI", - [SCC2_SMI_STS] = "SCC2", - [SPI_SSMI_STS] = "SPI_SSMI", - [SPI_SMI_STS] = "SPI", - [PMC_OCP_SMI_STS] = "OCP_CSE", + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPIO_STS_BIT] = "GPIO_SMI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", + [MC_SMI_STS_BIT] = "MCSMI", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [XHCI_SMI_STS_BIT] = "XHCI", + [SCS_SMI_STS_BIT] = "HOST_SMBUS", + [SCS_SMI_STS_BIT] = "SCS", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [SCC2_SMI_STS_BIT] = "SCC2", + [SPI_SSMI_STS_BIT] = "SPI_SSMI", + [SPI_SMI_STS_BIT] = "SPI", + [PMC_OCP_SMI_STS_BIT] = "OCP_CSE", }; *a = ARRAY_SIZE(smi_sts_bits); @@ -98,7 +98,7 @@ /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) - generic_sts |= (1 << FAKE_PM1_SMI_STS); + generic_sts |= (1 << PM1_STS_BIT); } return generic_sts; diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..424d66f 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -38,19 +38,19 @@ uint32_t smihandler_soc_get_sci_mask(void) { uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_SMI_STS) | - SMI_HANDLER_SCI_EN(SLP_SMI_STS); + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; } const smi_handler_t southbridge_smi[32] = { - [SLP_SMI_STS] = smihandler_southbridge_sleep, - [APM_SMI_STS] = smihandler_southbridge_apmc, - [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1, - [GPIO_SMI_STS] = smihandler_southbridge_gpi, - [TCO_SMI_STS] = smihandler_southbridge_tco, - [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [TCO_STS_BIT] = smihandler_southbridge_tco, + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Gerrit-Change-Number: 39022 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000
by Raul Rangel (Code Review) 18 Feb '21

18 Feb '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42886 ) Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ...................................................................... soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 This places EARLY_RESERVED_DRAM_BASE right after the Option ROM. This closes the ~31 MiB gap between the Option ROM and Early RAM. [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 [ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000003bcfff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000003bd000-0x00000000cc51bfff] usable [ 0.000000] BIOS-e820: [mem 0x00000000cc51c000-0x00000000cd7fffff] type 16 [ 0.000000] BIOS-e820: [mem 0x00000000cd800000-0x00000000cfffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000042f33ffff] usable [ 0.000000] BIOS-e820: [mem 0x000000042f340000-0x000000042fffffff] reserved BUG=b:159081993 TEST=Boot picasso trembyle and run suspend_stress_test a few times. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5944abce19f17458ea3017d04f6dfdfe8e8050bf --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42886/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9630ad3..0d87c1f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -63,7 +63,7 @@ config EARLY_RESERVED_DRAM_BASE hex - default 0x2000000 + default 0x100000 help This variable defines the base address of the DRAM which is reserved for usage by coreboot in early stages (i.e. before ramstage is up). @@ -77,14 +77,14 @@ config PSP_APOB_DRAM_ADDRESS hex - default 0x2001000 + default 0x101000 help Location in DRAM where the PSP will copy the AGESA PSP Output Block. config PSP_SHAREDMEM_BASE hex - default 0x2011000 if VBOOT + default 0x111000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies @@ -111,7 +111,7 @@ config BOOTBLOCK_ADDR hex - default 0x2030000 + default 0x120000 help Sets the address in DRAM where bootblock should be loaded. @@ -126,7 +126,7 @@ config X86_RESET_VECTOR hex depends on ARCH_X86 - default 0x203fff0 + default 0x12fff0 help Sets the reset vector within bootblock where x86 starts execution. Reset vector is supposed to live at offset -0x10 from end of @@ -134,7 +134,7 @@ config ROMSTAGE_ADDR hex - default 0x2040000 + default 0x130000 help Sets the address in DRAM where romstage should be loaded. @@ -146,7 +146,7 @@ config FSP_M_ADDR hex - default 0x20C0000 + default 0x1B0000 help Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address. @@ -160,7 +160,7 @@ config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2140000 + default 0x230000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..e94c3ba 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -39,7 +39,7 @@ * | (C_ENV_BOOTBLOCK_SIZE) | * +--------------------------------+ BOOTBLOCK_ADDR * | Unused hole | - * | (86KiB) | + * | (21KiB) | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 -- To view, visit https://review.coreboot.org/c/coreboot/+/42886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5944abce19f17458ea3017d04f6dfdfe8e8050bf Gerrit-Change-Number: 42886 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Chrome EC SOCs: Integrate Chrome EC check
by Paul Menzel (Code Review) 18 Feb '21

18 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42258 ) Change subject: Chrome EC SOCs: Integrate Chrome EC check ...................................................................... Chrome EC SOCs: Integrate Chrome EC check Behave the same as newer platforms. Skylake has the same code. This also adds brackets around &(gnvs->chromeos), so the it’s clear, what pointer is meant. Change-Id: I43ff551c717f598c7a65547ec49157853681314f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/apollolake/acpi.c 3 files changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/42258/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index fe5879c..7068ac0 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -254,8 +254,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ea67aa3..54b5521 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -229,8 +229,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 595e6a2..f9962e9 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -83,8 +83,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ff551c717f598c7a65547ec49157853681314f Gerrit-Change-Number: 42258 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/*/acpi: Put braces around *else* branch
by Paul Menzel (Code Review) 18 Feb '21

18 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42257 ) Change subject: soc/intel/*/acpi: Put braces around *else* branch ...................................................................... soc/intel/*/acpi: Put braces around *else* branch From `Documentation/coding_style.md`: > This does not apply if only one branch of a conditional statement is a > single statement; in the latter case use braces in both branches: Change-Id: Idb4427f7ae9f7b99ba74f7e84aed6b8a901ca9fc Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42257/1 diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 796e770..12ce34c 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -198,8 +198,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 88ec5fe..250ff3b 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -292,8 +292,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 0991134..e965c48 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -292,8 +292,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4427f7ae9f7b99ba74f7e84aed6b8a901ca9fc Gerrit-Change-Number: 42257 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Make `acpi_create_gnvs()` static
by Paul Menzel (Code Review) 18 Feb '21

18 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42199 ) Change subject: soc/intel/cannonlake: Make `acpi_create_gnvs()` static ...................................................................... soc/intel/cannonlake: Make `acpi_create_gnvs()` static The function `acpi_create_gnvs()` is only used in this translation unit, so make it `static`. This unifies it with the Skylake version `src/soc/intel/skylake/acpi.c`. Change-Id: I8f817aa46c75332ec5a5fa77e8772ae0f0e3a366 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42199/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 12758e1..886cba2 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -182,7 +182,7 @@ return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +static void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; config = config_of_soc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f817aa46c75332ec5a5fa77e8772ae0f0e3a366 Gerrit-Change-Number: 42199 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: nb/intel/pineview: Drop unused `GPIO32` macro
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45423 ) Change subject: nb/intel/pineview: Drop unused `GPIO32` macro ...................................................................... nb/intel/pineview: Drop unused `GPIO32` macro It's not used, and GPIO registers are on the southbridge. Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/pineview.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45423/1 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 82ae3ff..48ee263 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -26,8 +26,6 @@ #define GTTADR 0x1c #define BSM 0x5c -#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) - /* * MCHBAR */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Gerrit-Change-Number: 45423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45503 ) Change subject: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 ...................................................................... nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 The 100 MHz reference clock seems to be unstable when using high multipliers. Use the 133 MHz reference clock instead. Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45503/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 6b74405..19e0e1d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -136,7 +136,7 @@ { if (ctrl->tCK <= TCK_1200MHZ) { ctrl->tCK = TCK_1200MHZ; - ctrl->base_freq = 100; + ctrl->base_freq = 133; } else if (ctrl->tCK <= TCK_1100MHZ) { ctrl->tCK = TCK_1100MHZ; ctrl->base_freq = 100; -- To view, visit https://review.coreboot.org/c/coreboot/+/45503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Gerrit-Change-Number: 45503 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Clean up `dram_freq` function
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45502 ) Change subject: nb/intel/sandybridge: Clean up `dram_freq` function ...................................................................... nb/intel/sandybridge: Clean up `dram_freq` function The thing that this function initializes is the MPLL (Memory PLL). So, call it by its name. Also add a missing newline in a printk, and update a comment on the callsite of this function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45502/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 64a381d..6b74405 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -459,7 +459,7 @@ if (ctrl->tCK > TCK_400MHZ) { printk(BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). " - "Increasing to 400 MHz as last resort"); + "Increasing to 400 MHz as last resort.\n"); ctrl->tCK = TCK_400MHZ; } @@ -467,11 +467,11 @@ u8 val2; u32 reg1 = 0; - /* Step 1 - Set target PCU frequency */ + /* Step 1 - Determine target MPLL frequency */ find_cas_tck(ctrl); /* - * The PLL will never lock if the required frequency is already set. + * The MPLL will never lock if the requested frequency is already set. * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); @@ -479,16 +479,16 @@ if (val2) return; - /* Step 2 - Select frequency in the MCU */ + /* Step 2 - Request MPLL frequency */ reg1 = ctrl->FRQ; if (ctrl->base_freq == 100) - reg1 |= 0x100; /* Enable 100Mhz REF clock */ + reg1 |= 0x100; /* Use 100MHz reference clock */ - reg1 |= 0x80000000; /* set running bit */ + reg1 |= (1 << 31); /* Set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; int i = 0; - printk(BIOS_DEBUG, "PLL busy... "); - while (reg1 & 0x80000000) { + printk(BIOS_DEBUG, "MPLL busy... "); + while (reg1 & (1 << 31)) { udelay(10); i++; reg1 = MCHBAR32(MC_BIOS_REQ); @@ -499,11 +499,11 @@ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; if (val2 >= ctrl->FRQ) { - printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); return; } - printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); + printk(BIOS_DEBUG, "MPLL didn't lock. Retrying at lower frequency\n"); ctrl->tCK++; } } @@ -571,7 +571,7 @@ dram_dimm_mapping(ctrl); } - /* Set MC frequency */ + /* Set MPLL frequency */ dram_freq(ctrl); if (!fast_boot) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Gerrit-Change-Number: 45502 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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