coreboot-gerrit October 2020

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Change in coreboot[master]: soc/mediatek/mt8192: Get dram total size from emi config
by CK HU (Code Review) 08 Mar '21

08 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44729 to review the following change. Change subject: soc/mediatek/mt8192: Get dram total size from emi config ...................................................................... soc/mediatek/mt8192: Get dram total size from emi config Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I5fb64e964cbf62ee70a90975583a9947558bbab6 --- M src/soc/mediatek/mt8192/emi.c 1 file changed, 63 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44729/1 diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index acd605f..d485131 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -437,9 +437,71 @@ dramc_set_broadcast(bc_bak); } +static int get_rank_num_by_emi(void) +{ + unsigned int emi_cona = read32(&emi_reg->cona); + + if (emi_cona & (0x3 << 16)) + return 2; + else + return 1; +} + +static int get_channel_num_by_emi(void) +{ + unsigned int emi_cona = read32(&emi_reg->cona); + + int channel_nr = 0x1 << ((emi_cona >> 8) & 0x3); + + return channel_nr; +} + +static void get_rank_size_by_emi_reg(u64 rank_size[RANK_MAX]) +{ + u32 quad_ch_ratio = 1; + u64 ch0_rank0_size, ch0_rank1_size; + u64 ch1_rank0_size, ch1_rank1_size; + u32 cen_emi_conh = read32(&emi_reg->conh); + + rank_size[0] = 0; + rank_size[1] = 0; + + ch0_rank0_size = (cen_emi_conh >> 16) & 0xf; + ch0_rank1_size = (cen_emi_conh >> 20) & 0xf; + ch1_rank0_size = (cen_emi_conh >> 24) & 0xf; + ch1_rank1_size = (cen_emi_conh >> 28) & 0xf; + + ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28; + ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28; + ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28; + ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28; + + rank_size[0] += ch0_rank0_size; + + if (get_rank_num_by_emi() > 1) + rank_size[1] += ch0_rank1_size; + + if (get_channel_num_by_emi() > 1) { + rank_size[0] += ch1_rank0_size; + if (get_rank_num_by_emi() > 1) + rank_size[1] += ch1_rank1_size; + } + + dramc_dbg("DRAM rank0 size:0x%llX, DRAM rank1 size=0x%llX\n", + rank_size[0], rank_size[1]); +} + size_t sdram_size(void) { - size_t dram_size = 0x100000000; + int rank_num; + size_t dram_size = 0; + u64 rank_size[RANK_MAX]; + + get_rank_size_by_emi_reg(rank_size); + rank_num = get_rank_num_by_emi(); + + for (int i = 0; i < rank_num; i++) + dram_size += rank_size[i]; return dram_size; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fb64e964cbf62ee70a90975583a9947558bbab6 Gerrit-Change-Number: 44729 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/mediatek/mt8192: Set dramc DVFS setting
by CK HU (Code Review) 08 Mar '21

08 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44726 to review the following change. Change subject: soc/mediatek/mt8192: Set dramc DVFS setting ...................................................................... soc/mediatek/mt8192: Set dramc DVFS setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I3750a52046b241e533873aee1e6061c65e4bbea3 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 2 files changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44726/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index c51c261..eb37ac3 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -111,6 +111,63 @@ *(cali->pll_mode) = pll_mode; } +void dvfs_settings(const struct ddr_cali *cali) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel, + MISC_CKMUX_SEL_RG_52M_104M_SEL, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_dvfsdll, + MISC_SHU_DVFSDLL_R_DLL_IDLE, 0x2b, + MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 0x43); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, get_shu(cali)); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_RG_MRW_AFTER_DFS, 1); + SET32_BITFIELDS(&mtk_dpm->fsm_cfg_1, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 1, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 1, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 1, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_opt, + MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 1, + MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 1, + MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl7, + MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl, + MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 1, + MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl, + MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 1, + MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 3, + MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW, 3); + } + + SET32_BITFIELDS(&ch[0].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 0); + SET32_BITFIELDS(&ch[1].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 1); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfs_emi_clk, + MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_RG_DLL_SHUFFLE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_OPTION, 0, + MISC_DVFSCTL2_R_DVFS_PARK_N, 0); + } + + dramc_set_broadcast(bc_bak); +} + void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst) { u8 tmp; diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index ab6b027..1d6b6c2 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -4281,6 +4281,18 @@ SHU_R0_B1_DQ0_ARPI_PBYTE_B1, wl_dqs_final_delay[rank][1]); } } + +static void dramc_enable_phy_dcm(dcm_state dcm) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + enable_phy_dcm_non_shuffle(dcm); + enable_phy_dcm_shuffle(dcm, 0); + + dramc_set_broadcast(bc_bak); +} + static void ddr_update_ac_timing(const struct ddr_cali *cali) { u8 table_idx; @@ -4568,7 +4580,10 @@ static void dramc_init(const struct ddr_cali *cali) { dramc_setting(cali); + dramc_enable_phy_dcm(DCM_OFF); dramc_reset_delay_chain_before_calibration(); + dvfs_settings(cali); + dramc_8_phase_cal(cali); dramc_duty_calibration(cali->params); dramc_mode_reg_init(cali); -- To view, visit https://review.coreboot.org/c/coreboot/+/44726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3750a52046b241e533873aee1e6061c65e4bbea3 Gerrit-Change-Number: 44726 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/mediatek/mt8192: Limit DRAM calibration frequency count to reduce...
by CK HU (Code Review) 08 Mar '21

08 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44731 to review the following change. Change subject: soc/mediatek/mt8192: Limit DRAM calibration frequency count to reduce bootup time ...................................................................... soc/mediatek/mt8192: Limit DRAM calibration frequency count to reduce bootup time Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Id664c0623318a37ed5b10c4aa5d62507187cfdac --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h 4 files changed, 71 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44731/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 1d1cf7b..7547032 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -35,6 +35,14 @@ This options enables DRAM calibration with multiple frequencies (low, medium and high) for DVFS feature. +config MT8192_DRAM_DVFS_LIMIT_FREQ_CNT + bool + default n + select MT8192_DRAM_DVFS + help + This options limit DRAM frequency calibration count from total 7 to 3, + other frequency will directly use the low frequency shu result. + config MEMORY_TEST bool default y diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 72f9a24..f93be32 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -377,10 +377,20 @@ write32(&mtk_apmixed->pllon_con3, tmp & ~(0x1 << 2)); } +static void save_low_frequency_shu_result_to_no_k_shu(void) +{ + for (u8 k_seq_idx = CALI_SEQ0; k_seq_idx < CALI_SEQ_MAX; k_seq_idx++) { + if (!is_freq_need_k(k_seq_idx)) { + dram_dfs_shu shu = get_shu_save_by_k_shu(k_seq_idx); + dramc_info("This shu no need do calibration, use shu0 result directly\n"); + dramc_save_result_to_shuffle(DRAM_DFS_SHU0, shu); + } + } +} + void init_dram(const struct dramc_data *dparam) { u32 bc_bak; - u8 k_shuffle, k_shuffle_end; u8 pll_mode = 0; bool first_freq_k = true; @@ -407,13 +417,12 @@ dramc_sw_impedance_cal(ODT_OFF, &cali.impedance); dramc_sw_impedance_cal(ODT_ON, &cali.impedance); - if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) - k_shuffle_end = CALI_SEQ_MAX; - else - k_shuffle_end = CALI_SEQ1; + for (u8 k_seq_idx = CALI_SEQ0; k_seq_idx < CALI_SEQ_MAX; k_seq_idx++) { + if (!is_freq_need_k(k_seq_idx)) + continue; - for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) { - set_cali_datas(&cali, dparam, k_shuffle); + set_cali_datas(&cali, dparam, k_seq_idx); + dramc_info("start calibration frequency %d\n", cali.frequency); set_vcore_voltage_for_each_freq(&cali); dfs_init_for_calibration(&cali); @@ -429,9 +438,12 @@ dramc_ac_timing_optimize(&cali); dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu); - /* for frequency switch in dramc_mode_reg_init phase */ - if (first_freq_k) + if (first_freq_k) { + save_low_frequency_shu_result_to_no_k_shu(); + + /* for frequency switch in dramc_mode_reg_init phase */ dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1); + } first_freq_k = false; dramc_info("frequency %d calibration finish\n", get_frequency(&cali)); diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c index 526059a..e8878c1 100644 --- a/src/soc/mediatek/mt8192/dramc_utility.c +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -13,6 +13,10 @@ u32 vcore; }; +struct freq_cali_sel { + bool freq_sel; +}; + static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = { /* frequency freq_group div_mode shuffle_saved vref_cali vcore*/ [CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000}, @@ -24,6 +28,38 @@ [CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500}, }; +#if CONFIG(MT8192_DRAM_DVFS_LIMIT_FREQ_CNT) +static const struct freq_cali_sel cali_select[CALI_SEQ_MAX] = { + [CALI_SEQ0] = {true}, + [CALI_SEQ1] = {false}, + [CALI_SEQ2] = {false}, + [CALI_SEQ3] = {false}, + [CALI_SEQ4] = {false}, + [CALI_SEQ5] = {true}, + [CALI_SEQ6] = {true}, +}; +#elif CONFIG(MT8192_DRAM_DVFS) +static const struct freq_cali_sel cali_select[CALI_SEQ_MAX] = { + [CALI_SEQ0] = {true}, + [CALI_SEQ1] = {true}, + [CALI_SEQ2] = {true}, + [CALI_SEQ3] = {true}, + [CALI_SEQ4] = {true}, + [CALI_SEQ5] = {true}, + [CALI_SEQ6] = {true}, +}; +#else +static const struct freq_cali_sel cali_select[CALI_SEQ_MAX] = { + [CALI_SEQ0] = {true}, + [CALI_SEQ1] = {false}, + [CALI_SEQ2] = {false}, + [CALI_SEQ3] = {false}, + [CALI_SEQ4] = {false}, + [CALI_SEQ5] = {false}, + [CALI_SEQ6] = {false}, +}; +#endif + void dramc_set_broadcast(u32 onoff) { write32(&mt8192_infracfg->dramc_wbr, onoff); @@ -84,6 +120,11 @@ return cali->vref_cali; } +bool is_freq_need_k(dram_cali_seq k_seq) +{ + return cali_select[k_seq].freq_sel; +} + dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali) { return cali->pinmux_type; diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h index c2dec82..9872cda 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -284,6 +284,7 @@ void dramc_tx_oe_calibration(const struct ddr_cali* cali); dram_freq_grp get_freq_group(const struct ddr_cali *cali); dram_odt_state get_odt_state(const struct ddr_cali *cali); +bool is_freq_need_k(dram_cali_seq k_seq); u8 get_fsp(const struct ddr_cali *cali); dram_dfs_shu get_shu(const struct ddr_cali *cali); dram_freq_grp get_highest_freq_group(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/44731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id664c0623318a37ed5b10c4aa5d62507187cfdac Gerrit-Change-Number: 44731 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup...
by CK HU (Code Review) 08 Mar '21

08 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44730 to review the following change. Change subject: soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time ...................................................................... soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ib37ecc7bf3f1776d27161948e779ed1f96ee9a0c --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 197 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44730/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index eb37ac3..fbb23bb 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -3,6 +3,11 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +typedef enum { + SRAM_SHU_TYPE_LOAD, + SRAM_SHU_TYPE_RESTORE, +} sram_shu_type; + void enable_dfs_hw_mode_clk(void) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -17,6 +22,62 @@ } } +static void no_queue_flush_wa(bool wa_enable) +{ + u32 bc_bak = 0; + static u32 perfctl0_bak = 0; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + if (wa_enable) { + perfctl0_bak = (read32(&ch[0].ao.perfctl0) >> 10) & 0x3; + SET32_BITFIELDS(&ch[0].ao.perfctl0, + PERFCTL0_RWAGEEN, 0, + PERFCTL0_EMILLATEN, 0); + } else { + SET32_BITFIELDS(&ch[0].ao.perfctl0, + PERFCTL0_RWAGEEN, perfctl0_bak & 0x1, + PERFCTL0_EMILLATEN, (perfctl0_bak >>1) & 0x1); + } + + dramc_set_broadcast(bc_bak); +} + +static void wait_sram_shu_ack(sram_shu_type type) +{ + u8 ack_state = 0, complete = 1; + + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { + do { + if (type == SRAM_SHU_TYPE_LOAD) + ack_state = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK); + else + ack_state = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK); + } while(ack_state != complete); + } +} + +static void timing_tx_sr(u32 shu_level) +{ + u32 onoff = 0, bc_bak = 0; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + if ((shu_level == DRAM_DFS_SHU4) || (shu_level == DRAM_DFS_SHU5) || + (shu_level == DRAM_DFS_SHU6)) + onoff = 0; + else + onoff = 1; + + SET32_BITFIELDS(&ch[0].ao.refctrl1, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, onoff); + dramc_set_broadcast(bc_bak); +} + void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level) { u8 shu_ack = 0; @@ -109,6 +170,129 @@ pll_mode = !pll_mode; *(cali->pll_mode) = pll_mode; + dramc_dbg("%s end with pll_mode:%d\n", __func__, *(cali->pll_mode)); +} + +void dramc_dfs_direct_jump_sram_shu_rg_mode(const struct ddr_cali *cali, + dram_dfs_shu shu_level) +{ + u8 shu_ack = 0; + u8 pll_mode = *(cali->pll_mode); + u32 *shu_ack_reg = &mtk_dpm->status_4; + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("Disable CLRPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + } else { + dramc_dbg("Disable PHYPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + shu_ack |= (0x1 << chn); + + if (pll_mode == PHYPLL_MODE) + dramc_dbg("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); + else + dramc_dbg("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, shu_ack); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 1); + } + + udelay(1); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 0); + + if (pll_mode == PHYPLL_MODE) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, !pll_mode); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 1); + } + dramc_dbg("Enable CLRPLL\n"); + } else { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, !pll_mode); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 1); + } + dramc_dbg("Enable PHYPLL\n"); + } + + udelay(1); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, shu_level); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 1); + } + + wait_sram_shu_ack(SRAM_SHU_TYPE_LOAD); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 0); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 1); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1); + + no_queue_flush_wa(true); + + udelay(20); + + dramc_dbg("SHUFFLE Start\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 1); + + while ((READ32_BITFIELD(shu_ack_reg, LPIF_STATUS_4_SHU_EN_ACK) != shu_ack)) + dramc_dbg("wait shu_en ack.\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0); + dramc_dbg("SHUFFLE End\n"); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 1); + + wait_sram_shu_ack(SRAM_SHU_TYPE_RESTORE); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 0); + + no_queue_flush_wa(false); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0); + + timing_tx_sr(shu_level); + + dramc_dbg("Shuffle flow complete\n"); + *(cali->pll_mode) = !pll_mode; } void dvfs_settings(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 2bcc449..72f9a24 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -440,5 +440,18 @@ after_calib(&cali); enable_dfs_hw_mode_clk(); + if (CONFIG(MT8192_DRAM_DVFS)) { + dram_cali_seq bootup_cali_seq = CALI_SEQ5; + dram_dfs_shu bootup_shu = get_shu_save_by_k_shu(bootup_cali_seq); + + set_cali_datas(&cali, dparam, bootup_cali_seq); + set_vcore_voltage_for_each_freq(&cali); + + dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, DRAM_DFS_SHU1); + dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, bootup_shu); + dramc_info("switch to frequency %d to decrease the bootup time\n", + get_frequency_by_shu(bootup_shu)); + } + dramc_runtime_config(&cali); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib37ecc7bf3f1776d27161948e779ed1f96ee9a0c Gerrit-Change-Number: 44730 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: soc/mediatek/mt8192: Do write leveling training
by CK HU (Code Review) 08 Mar '21

08 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44717 to review the following change. Change subject: soc/mediatek/mt8192: Do write leveling training ...................................................................... soc/mediatek/mt8192: Do write leveling training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Icf4f5d07eb8ef1d0d99ad106f497fea5f60c8a97 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44717/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 84acb3e..d418228 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -4096,6 +4096,191 @@ move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); } +static void shift_dq_oen_ui(const struct ddr_cali* cali, u8 rk) +{ + s8 shift_ui = -1; + u8 chn = cali->chn; + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 20}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 20}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 20}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 16}, + {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 20}}; + + for (u8 idx = 0; idx < ARRAY_SIZE(ui_regs); idx++) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + +static void shift_dqs_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) +{ + u8 idx, step; + u8 chn = cali->chn; + + if (byte == 0) { + idx = 0; + step = 2; + } else if (byte == 1) { + idx = 1; + step = 2; + } else { + idx = 0; + step = 1; + } + + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_selph_dqs1, 0}, + {&ch[chn].ao.shu_selph_dqs1, 4}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_selph_dqs0, 0}, + {&ch[chn].ao.shu_selph_dqs0, 4}}; + for (; idx < ARRAY_SIZE(ui_regs); idx += step) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + +static void shift_dqs_oen_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) +{ + u8 idx, step; + u8 chn = cali->chn; + + if (byte == 0) { + idx = 0; + step = 2; + } else if (byte == 1) { + idx = 1; + step = 2; + } else { + idx = 0; + step = 1; + } + + reg_transfer ui_regs[] = {{&ch[chn].ao.shu_selph_dqs1, 16}, + {&ch[chn].ao.shu_selph_dqs1, 20}}; + reg_transfer mck_regs[] = {{&ch[chn].ao.shu_selph_dqs0, 16}, + {&ch[chn].ao.shu_selph_dqs0, 20}}; + for (; idx < ARRAY_SIZE(ui_regs); idx += step) + move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); +} + +static void shift_dq_ui_all_rk(const struct ddr_cali* cali) +{ + s8 shift_ui = -1; + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + shift_dq_ui(cali, rk, shift_ui); +} + +static void shift_dq_oen_ui_all_rk(const struct ddr_cali* cali) +{ + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + shift_dq_oen_ui(cali, rk); +} + +static void shift_dqs_wck_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) +{ + shift_dqs_ui(cali, shift_ui, byte); + shift_dqs_oen_ui(cali, shift_ui, byte); +} + +static void write_leveling_move_dqs_instead_of_clk(const struct ddr_cali* cali) +{ + s8 shift_ui = -1; + u8 chn = cali->chn; + + shift_dq_ui_all_rk(cali); + shift_dq_oen_ui_all_rk(cali); + shift_dqs_wck_ui(cali, shift_ui, BYTE_NUM); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0); +} + +static void set_dram_mr_write_leveling(const struct ddr_cali* cali, bool state) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + struct mr_values *mr_value = cali->mr_value; + u8 mr02 = mr_value->mr02[get_fsp(cali)]; + + if (state) + mr02 |= 0x80; + else + mr02 &= 0x7f; + + dramc_mode_reg_write_by_rank(cali, chn, rank, 2, mr02); +} + +void dramc_write_leveling(const struct ddr_cali* cali, u8 wl_dqs_final_delay[2][2]) +{ + s8 shift_ui; + u8 chn = cali->chn; + u8 rank = cali->rank; + u16 pi_bound; + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.cbt_wlev_ctrl0}, + {&ch[chn].ao.cbt_wlev_ctrl1}, + {&ch[chn].ao.cbt_wlev_ctrl3}, + {&ch[chn].ao.cbt_wlev_ctrl5}, + {&ch[chn].phy_ao.byte[0].shu_b0_vref}, + {&ch[chn].phy_ao.byte[1].shu_b0_vref}, + {&ch[chn].phy_ao.byte[0].rk[rank].shu_b0_phy_vref_sel}, + {&ch[chn].phy_ao.byte[1].rk[rank].shu_b0_phy_vref_sel}, + {&ch[chn].ao.dramc_pd_ctrl}, + }; + + if ((cali->freq_group == DDRFREQ_400) && (rank == RANK_1)) + return; + + if (cali->freq_group == DDRFREQ_400) + pi_bound = 32; + else + pi_bound = 64; + + wl_dqs_final_delay[rank][0] = cali->params->wr_level[chn][rank][0]; + wl_dqs_final_delay[rank][1] = cali->params->wr_level[chn][rank][1]; + dramc_dbg("WRITELEVELING DQS0:%d, DQS1:%d, pi_bound:%d\n", + wl_dqs_final_delay[rank][0], wl_dqs_final_delay[rank][1], pi_bound); + + dramc_auto_refresh_switch(chn, false); + + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, rank); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 1); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + if (rank == RANK_0) + write_leveling_move_dqs_instead_of_clk(cali); + + set_dram_mr_write_leveling(cali, false); + + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 0); + o1_path_on_off(cali, O1_OFF); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, 0); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 0); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + for (u8 byte = 0; byte < BYTE_NUM; byte++) { + dramc_dbg("Write leveling (Byte %d): %d", byte, wl_dqs_final_delay[rank][byte]); + if (wl_dqs_final_delay[rank][byte] >= pi_bound) { + shift_ui = (wl_dqs_final_delay[rank][byte] / pi_bound) * (pi_bound / 32); + shift_dqs_wck_ui(cali, shift_ui, byte); + wl_dqs_final_delay[rank][byte] %= pi_bound; + } + dramc_dbg(" => %d\n", wl_dqs_final_delay[rank][byte]); + } + + for (u8 rk = rank; rk < RANK_MAX; rk++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, wl_dqs_final_delay[rank][0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, wl_dqs_final_delay[rank][1]); + } +} static void ddr_update_ac_timing(const struct ddr_cali *cali) { u8 table_idx; diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 214bf55..2be3962 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -220,6 +220,8 @@ static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn) { + u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]; + cali->chn = chn; SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, @@ -233,6 +235,15 @@ } shuffle_dfs_to_fsp1(cali); + + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) { + cali->rank = rank; + dramc_dbg("Start K CH %d, RK %d\n", chn, rank); + + /* should disable the auto refresh before do write leveling */ + dramc_auto_refresh_switch(chn, false); + dramc_write_leveling(cali, dqs_final_delay); + } } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf4f5d07eb8ef1d0d99ad106f497fea5f60c8a97 Gerrit-Change-Number: 44717 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: mb/google/octopus/var/fleex: Add new SKU for LTE touch
by Amanda Hwang (Code Review) 05 Mar '21

05 Mar '21

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46643 ) Change subject: mb/google/octopus/var/fleex: Add new SKU for LTE touch ...................................................................... mb/google/octopus/var/fleex: Add new SKU for LTE touch BUG=b:168001586 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4 and 5. Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/variant.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/46643/1 diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index f1ec818..fcc8be0 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -5,11 +5,9 @@ #include <ec/google/chromeec/ec.h> #include <sar.h> -#define LTE_SKU 4 - static bool is_lte_sku(void) { - return (google_chromeec_get_board_sku() == LTE_SKU); + return (google_chromeec_get_board_sku() > 3); } void variant_smi_sleep(u8 slp_typ) -- To view, visit https://review.coreboot.org/c/coreboot/+/46643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4 Gerrit-Change-Number: 46643 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/broadwell/pch: Rename USB files
by Angel Pons (Code Review) 05 Mar '21

05 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47021 ) Change subject: soc/intel/broadwell/pch: Rename USB files ...................................................................... soc/intel/broadwell/pch: Rename USB files Done to ease diffing against Lynxpoint. Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/Makefile.inc R src/soc/intel/broadwell/pch/usb_ehci.c R src/soc/intel/broadwell/pch/usb_xhci.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/47021/1 diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 1c19613..1ebe324f 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -32,8 +32,8 @@ bootblock-y += usb_debug.c romstage-y += usb_debug.c ramstage-y += usb_debug.c -ramstage-y += ehci.c -ramstage-y += xhci.c -smm-y += xhci.c +ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c +smm-y += usb_xhci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/soc/intel/broadwell/pch/ehci.c b/src/soc/intel/broadwell/pch/usb_ehci.c similarity index 100% rename from src/soc/intel/broadwell/pch/ehci.c rename to src/soc/intel/broadwell/pch/usb_ehci.c diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/usb_xhci.c similarity index 100% rename from src/soc/intel/broadwell/pch/xhci.c rename to src/soc/intel/broadwell/pch/usb_xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86 Gerrit-Change-Number: 47021 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 04 Mar '21

04 Mar '21

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42079 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 266 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42079/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fbf56b4..55c06b1 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -208,4 +208,10 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 + +config EARLY_TCSS + bool "Enable early TCSS" + help + Enable devices to be detected over Type-C ports during boot. + endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..5e60114 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-$(CONFIG_EARLY_TCSS) += early_tcss.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 00db2a4..3da5d9a 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -10,6 +10,7 @@ #include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> +#include <soc/early_tcss.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -129,6 +130,10 @@ * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Check for early TCSS and connect devices */ + if (CONFIG(EARLY_TCSS)) + early_tcss_enable(); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c new file mode 100644 index 0000000..942d490 --- /dev/null +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/pmclib.h> +#include <soc/early_tcss.h> +#include <soc/pci_devs.h> +#include <stdlib.h> + +/* send the ipc_command */ +static int send_ipc_command(uint32_t cmd, uint8_t *tcss_req, int req_size, + struct pmc_ipc_buffer *rbuf) +{ + struct pmc_ipc_buffer *wbuf = malloc(sizeof(*tcss_req)); + + /* copy the tcss_req into a buffer for ipc command */ + memcpy(wbuf, tcss_req, req_size); + + return pmc_send_ipc_cmd(cmd, wbuf, rbuf); +} + +static int send_pmc_connect_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_CONN_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_CONN_REQ_RES | /* Usage */ + mux_data.usb3_port << 4; + tcss_req[1] = mux_data.usb2_port | + mux_data.ufp << 4 | /* 1=UFP/0=DFP */ + mux_data.polarity << 5 | /* ORI-HSL */ + mux_data.polarity << 6 | /* ORI-SBU */ + mux_data.acc << 7; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" + "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); + + tcss_cmd.len = PMC_IPC_CONN_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_CONN_REQ_SIZE, rbuf); +} + +static int send_pmc_safe_mode_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_SAFE_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_SAFE_MODE_REQ_RES | + mux_data.usb3_port << 4; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n", tcss_req[0]); + + tcss_cmd.cmd.len = PMC_IPC_SAFE_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_SAFE_REQ_SIZE, rbuf); +} + +static int send_pmc_alt_mode_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_ALT_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_ALTMODE_REQ_RES | mux_data.usb3_port << 4; + tcss_req[1] |= PMC_IPC_DP_MODE; + + tcss_req[4] = mux_data.polarity << 1 | + mux_data.cable << 2 | + mux_data.ufp << 3 | + mux_data.polarity << 4 | + mux_data.polarity << 5; + + if (mux_data.dp_mode <= MODE_DP_PIN_F) { + switch (mux_data.dp_mode) { + case MODE_DP_PIN_A: + tcss_req[5] = 0; + break; + case MODE_DP_PIN_B: + tcss_req[5] = 1; + break; + case MODE_DP_PIN_C: + tcss_req[5] = 2; + break; + case MODE_DP_PIN_D: + tcss_req[5] = 3; + break; + case MODE_DP_PIN_E: + tcss_req[5] = 4; + break; + case MODE_DP_PIN_F: + tcss_req[5] = 5; + break; + } + } + + tcss_req[5] |= mux_data.hpd_lvl << 6; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" + "tcss_req[1]-> 0x%x\n" + "tcss_req[4]-> 0x%x\n" + "tcss_req[5]-> 0x%x\n\t", + tcss_req[0], tcss_req[1], tcss_req[4], tcss_req[5]); + + tcss_cmd.len = PMC_IPC_ALT_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_ALT_REQ_SIZE, rbuf); +} + +static void update_tcss_mux(int port, struct tcss_mux mux_data) +{ + struct pmc_ipc_buffer *rbuf = malloc(sizeof(*rbuf)); + int ret = 0; + + /* Check if the mux has a USB device */ + if (mux_data.usb) { + ret = send_pmc_connect_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + } + + /* check if mux has a DP device */ + if (mux_data.dp) { + + if (!mux_data.usb) { + ret = send_pmc_connect_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + } + ret = send_pmc_safe_mode_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d safe mode request failed\n", port); + return; + } + + ret = send_pmc_alt_mode_request(mux_data, rbuf); + } + + if (ret) + printk(BIOS_ERR, "Port %d mux set failed with error %d\n", port, ret); +} + +void early_tcss_enable(void) +{ + uint8_t num_ports; + int ret, i; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) + return; + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) + continue; + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) + continue; + + ret = google_chromeec_usb_pd_control(i, &mux_data.ufp, &mux_data.acc, + &mux_data.dp_mode); + if (ret < 0) + continue; + + mux_data.usb = !!(mux_flags & USB_PD_CTRL_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_CTRL_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_MUX_TBT_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_CTRL_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_CTRL_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_CTRL_HPD_LVL); + mux_data.usb2_port = port_map & 0x0F; + mux_data.usb3_port = (port_map & 0xF0) >> 4; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "ufp = %d dbg_acc=%d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.ufp, mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h new file mode 100644 index 0000000..29b7cdd --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PMC IPC related offsets and commands */ +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_USBC_SUBCMD_ID 0x0 +#define PMC_IPC_CMD 0x0 +#define PMC_IPC_TCSS_CONN_REQ_RES 0x0 +#define PMC_IPC_TCSS_SAFE_MODE_REQ_RES 0x2 +#define PMC_IPC_TCSS_ALTMODE_REQ_RES 0x3 +#define PMC_IPC_CONN_REQ_SIZE 2 +#define PMC_IPC_ALT_REQ_SIZE 8 +#define PMC_IPC_SAFE_REQ_SIZE 1 +#define PMC_IPC_DP_MODE BIT(4) + +/* connection modes for pmc */ +enum pmc_ipc_conn_mode { + PMC_IPC_TCSS_DISCONNECT_MODE, + PMC_IPC_TCSS_USB_MODE, + PMC_IPC_TCSS_ALTERNATE_MODE, + PMC_IPC_TCSS_SAFE_MODE, + PMC_IPC_TCSS_HPD_MODE, + PMC_IPC_TCSS_TOTAL_MODES, +}; + +/* DP Mode pin definitions */ +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) + +/* struct to hold all tcss_mux related variables */ +struct tcss_mux { + bool dp; /* DP connected */ + bool usb; /* USB connected */ + bool cable; /* Activ/Passive Cable */ + bool polarity; /* polarity of connected device */ + bool hpd_lvl; /* HPD Level assert */ + bool hpd_irq; /* HPD IRQ assert */ + bool ufp; + bool acc; + uint8_t dp_mode; /* DP Operation Mode */ + uint8_t usb3_port; /* USB2 Port Number */ + uint8_t usb2_port; /* USB3 Port Number */ +}; + +void early_tcss_enable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Gerrit-Change-Number: 42079 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smbus: Add config to use ACPI
by Maxim Polyakov (Code Review) 03 Mar '21

03 Mar '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44865 ) Change subject: soc/intel/common/block/smbus: Add config to use ACPI ...................................................................... soc/intel/common/block/smbus: Add config to use ACPI Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/smbus/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44865/1 diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index fe940cc..818200e 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -3,6 +3,13 @@ help Intel Processor common SMBus support +config SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_SMBUS + help + Intel Processor SMBus ACPI driver support + config SOC_INTEL_COMMON_BLOCK_TCO bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/44865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Gerrit-Change-Number: 44865 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate lock bit write
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47036 ) Change subject: sb/intel/lynxpoint/lpc.c: Relocate lock bit write ...................................................................... sb/intel/lynxpoint/lpc.c: Relocate lock bit write This lock bit can be set later, and should also be set for Lynxpoint-H. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47036/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b47b8a..10e498a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -364,9 +364,6 @@ if (RCBA32(FD) & PCH_DISABLE_ADSPD) RCBA32_OR(0x2b1c, (1 << 29)); - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - /* Set RCBA 0x33D4 after other setup */ RCBA32_OR(0x33d4, 0x2fff2fb1); @@ -772,6 +769,9 @@ { spi_finalize_ops(); + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) apm_control(APM_CNT_FINALIZE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Gerrit-Change-Number: 47036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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