coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: sb/intel/lynxpoint/acpi: Add missing USB ports
by Angel Pons (Code Review) 25 Feb '21

25 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46959 ) Change subject: sb/intel/lynxpoint/acpi: Add missing USB ports ...................................................................... sb/intel/lynxpoint/acpi: Add missing USB ports Broadwell has these, so add them to Lynxpoint as well. Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/xhci.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46959/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbeb562..2b3d433 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -338,9 +338,12 @@ Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT6) { Name (_ADR, 6) } // USB Port 5 Device (PRT7) { Name (_ADR, 7) } // USB Port 6 + Device (PRT8) { Name (_ADR, 8) } // USB Port 7 Device (SSP1) { Name (_ADR, 10) } // USB Port 10 Device (SSP2) { Name (_ADR, 11) } // USB Port 11 Device (SSP3) { Name (_ADR, 12) } // USB Port 12 Device (SSP4) { Name (_ADR, 13) } // USB Port 13 + Device (SSP5) { Name (_ADR, 14) } // USB Port 14 + Device (SSP6) { Name (_ADR, 15) } // USB Port 15 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Gerrit-Change-Number: 46959 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/amd/agesa/hudson/lpc: Remove space between function and signature
by Paul Menzel (Code Review) 25 Feb '21

25 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46638 ) Change subject: sb/amd/agesa/hudson/lpc: Remove space between function and signature ...................................................................... sb/amd/agesa/hudson/lpc: Remove space between function and signature Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/amd/agesa/hudson/lpc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46638/1 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 3fde291..f811302 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -68,10 +68,10 @@ cmos_init(0); /* Initialize i8259 pic */ - setup_i8259 (); + setup_i8259(); /* Initialize i8254 timers */ - setup_i8254 (); + setup_i8254(); } static void hudson_lpc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b Gerrit-Change-Number: 46638 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/amd/agesa/hudson: Use comment style from style guide
by Paul Menzel (Code Review) 25 Feb '21

25 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46637 ) Change subject: sb/amd/agesa/hudson: Use comment style from style guide ...................................................................... sb/amd/agesa/hudson: Use comment style from style guide Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/amd/agesa/hudson/lpc.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46637/1 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 89c9a6b..3fde291 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -59,7 +59,8 @@ cmos_check_update_date(); - /* Initialize the real time clock. + /* + * Initialize the real time clock. * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. * 1 tells cmos_init to always initialize the CMOS. -- To view, visit https://review.coreboot.org/c/coreboot/+/46637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2 Gerrit-Change-Number: 46637 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [WIP]mb/prodrive/hermes: Improve board config EEPROM handling
by Patrick Rudolph (Code Review) 25 Feb '21

25 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45686 ) Change subject: [WIP]mb/prodrive/hermes: Improve board config EEPROM handling ...................................................................... [WIP]mb/prodrive/hermes: Improve board config EEPROM handling * Check and print errors returned reading from I2C * Rework offset calculation by using more macros * Get rid of stage specific preprocessor code * Define the EEPROM layout as struct * Make use of the defined EEPROM layout to calculate the offset * Read the UPD to disable Vtd from EEPROM * Verify the checksum of the 'board settings' * Enable DeepS5 depending on the configuration value in 'board settings' Untested. Change-Id: I7f83d1ddb455a3d0aaec9757666d161f2091cec2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/ramstage.c M src/mainboard/prodrive/hermes/romstage.c M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h 5 files changed, 119 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/45686/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index bd5db5c..763f8bd 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -3,19 +3,20 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/smbus_host.h> +#include <crc_byte.h> #include "variants/baseboard/include/eeprom.h" /* * Check Signature in EEPROM (M24C32-FMN6TP) * If signature is there we assume that that the content is valid */ -int check_signature(u8 addr) +int check_fsp_signature(u8 addr, size_t offset, uint64_t fsp_signature) { u8 blob[8] = {0}; - if (!read_write_config(addr, blob, EEPROM_OFFSET_FSP_SIGNATURE, 0, ARRAY_SIZE(blob))) { + if (!read_write_config(addr, blob, offset, 0, ARRAY_SIZE(blob))) { // Check Signature - if (*(uint64_t *)blob == FSP_UPD_SIGNATURE) { + if (*(uint64_t *)blob == fsp_signature) { printk(BIOS_DEBUG, "CFG EEPROM: Signature valid.\n"); return 1; } @@ -25,6 +26,30 @@ return 0; } +/* + * Check Checksum of board settings in EEPROM (M24C32-FMN6TP) + * If signature is valid we assume that the settings are also sane. + */ +int check_board_settings_signature(u8 addr) +{ + const size_t off = offsetof(struct eeprom_layout, BoardSettings); + struct eeprom_board_settings BoardSettings; + uint32_t crc; + + if (read_write_config(addr, &BoardSettings, off, 0, sizeof(BoardSettings))) { + printk(BIOS_ERR, "CFG EEPROM: Failed to read board settings\n"); + return 0; + } + + crc = CRC(((uint8_t *)&BoardSettings) + sizeof(uint32_t), + sizeof(BoardSettings) - sizeof(uint32_t), crc32_byte); + if (crc != BoardSettings.signature) { + printk(BIOS_ERR, "CFG EEPROM: Board settings have invalid checksum\n"); + return 0; + } + return 1; +} + // Read data from offset and write it to offset in UPD bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, size_t size) diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b24dd56..ca42afb 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include "variants/baseboard/include/eeprom.h" #include "gpio.h" /* FIXME: Example code below */ @@ -84,6 +85,24 @@ mb_usb2_fp2_pwr_enable(1); } +static void mainboard_init(void *chip_info) +{ + uint8_t value = 0; + + if (!check_board_settings_signature(I2C_ADDR_EEPROM)) { + return; + } + + read_write_config(I2C_ADDR_EEPROM, &value, offsetof(struct eeprom_layout, BoardSettings) + + offsetof(struct eeprom_board_settings, deep_s5), 0, + sizeof(value)); + + config_t *config = config_of_soc(); + config->deep_s5_enable_ac = value; + config->deep_s5_enable_dc = value; +} + struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 18fc915..9130823 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -1,16 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include "variants/baseboard/include/eeprom.h" -static fsp_params parmas_list[] = { - // FIXME: Fill with additional options +static const fsp_params parmas_list[] = { + GET_VALUE_FSP_S_TEST_CONFIG(VtdDisableDeprecated), }; void mainboard_silicon_init_params(FSP_S_CONFIG *params) { size_t num = 0; + bool ret; const struct pad_config *gpio_table = get_gpio_table(&num); /* Configure pads prior to SiliconInit() in case there's any @@ -20,15 +22,19 @@ params->SataLedEnable = 1; // Overwrite params - if (!check_signature(I2C_ADDR_EEPROM)) + if (!check_fsp_signature(I2C_ADDR_EEPROM, + offsetof(struct eeprom_layout, FSPS_UPD), + FSPS_UPD_SIGNATURE)) return; - for (u8 i = 0; i <= ARRAY_SIZE(parmas_list); i++) { - if (ARRAY_SIZE(parmas_list) == 0) - break; - read_write_config(I2C_ADDR_EEPROM, params, EEPROM_OFFSET_FSP_CONFIG + - parmas_list[i].offset, - EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, - parmas_list[i].size); + for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) { + ret = read_write_config(I2C_ADDR_EEPROM, params, + parmas_list[i].eeprom_offset, + parmas_list[i].fsp_upd_offset, + parmas_list[i].size); + if (ret) { + printk(BIOS_ERR, "MB: Failed to read from EEPROM at addr. 0x%zx\n", + parmas_list[i].eeprom_offset); + } } } diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c index a25c43a..9202ad8 100644 --- a/src/mainboard/prodrive/hermes/romstage.c +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -1,31 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <variant/variants.h> #include "variants/baseboard/include/eeprom.h" -static fsp_params parmas_list[] = { - GET_VALUE(RMT), - GET_VALUE(HyperThreading), - GET_VALUE(BootFrequency) +static const fsp_params parmas_list[] = { + GET_VALUE_FSP_M_CONFIG(RMT), + GET_VALUE_FSP_M_CONFIG(HyperThreading), + GET_VALUE_FSP_M_CONFIG(BootFrequency), + GET_VALUE_FSP_M_TEST_CONFIG(VtdDisable), }; void mainboard_memory_init_params(FSPM_UPD *memupd) { + bool ret; memupd->FspmConfig.UserBd = 7; memupd->FspmTestConfig.SmbusSpdWriteDisable = 0; memupd->FspmConfig.IedSize = 0x400000; cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); // Overwrite memupd - if (!check_signature(I2C_ADDR_EEPROM)) + if (!check_fsp_signature(I2C_ADDR_EEPROM, + offsetof(struct eeprom_layout, FSPM_UPD), + FSPM_UPD_SIGNATURE)) return; for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) { - read_write_config(I2C_ADDR_EEPROM, memupd, EEPROM_OFFSET_FSP_CONFIG + - parmas_list[i].offset, - EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, - parmas_list[i].size); + ret = read_write_config(I2C_ADDR_EEPROM, memupd, + parmas_list[i].eeprom_offset, + parmas_list[i].fsp_upd_offset, + parmas_list[i].size); + if (ret) { + printk(BIOS_ERR, "MB: Failed to read from EEPROM at addr. 0x%zx\n", + parmas_list[i].eeprom_offset); + } } } diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index c41ead2..2da4317 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -7,27 +7,50 @@ #define HOSTC_I2C_EN (1 << 2) #define I2C_ADDR_EEPROM 0x57 -#if ENV_ROMSTAGE -#define FSP_UPD_SIGNATURE FSPM_UPD_SIGNATURE -#define EEPROM_OFFSET_FSP_SIGNATURE 0 -#define EEPROM_OFFSET_FSP_CONFIG 0 +struct eeprom_board_settings { + uint32_t signature; + uint8_t secureboot; + uint8_t primary_video; + uint8_t deep_s5; + uint8_t wake_on_usb; + uint8_t wake_on_lan; +} __packed; -#define GET_VALUE(x) {.offset = sizeof(FSP_UPD_HEADER) + sizeof(FSPM_ARCH_UPD) \ - + offsetof(FSP_M_CONFIG, x), .size = member_size(FSP_M_CONFIG, x)} -#else +/* The EEPROM on address 0x57 has the following vendor defined layout: */ +struct eeprom_layout { + uint8_t FSPM_UPD[0x600]; + uint8_t FSPS_UPD[0x600]; + uint8_t BoardLayout[0x400]; + uint8_t BootOrder[0xF00]; + union { + uint8_t RawBoardSetting[0x100]; + struct eeprom_board_settings BoardSettings; + }; +} __packed; -#define FSP_UPD_SIGNATURE FSPS_UPD_SIGNATURE -#define EEPROM_OFFSET_FSP_SIGNATURE 0x0600 -#define EEPROM_OFFSET_FSP_CONFIG (EEPROM_OFFSET_FSP_SIGNATURE + sizeof(FSP_UPD_HEADER)) -#define GET_VALUE(x) {.offset = offsetof(FSP_S_CONFIG, x), \ - .size = member_size(FSP_S_CONFIG, x)} -#endif // ENV_ROMSTAGE +_Static_assert(sizeof(struct eeprom_layout) == 0x2000, "EEPROM layout size missmatch"); +/* + * As reading the whole FSP UPD would take too much time only single UPDs of interrest are + * loaded at runtime. The following code eases the EEPROM to FSP UPD offset mappings. + */ typedef struct { - size_t offset; + size_t eeprom_offset; + size_t fsp_upd_offset; size_t size; } fsp_params; +/* Example: RMT, FSP_M_CONFIG, x:FspmTestConfig, y: FSPM_UPD */ +#define GET_VALUE(a, b, x, y) {.eeprom_offset = offsetof(struct eeprom_layout, y) + \ + offsetof(y, x) + offsetof(b, a), .fsp_upd_offset = \ + offsetof(y, x) + offsetof(b, a), .size = member_size(b, a)} + +#define GET_VALUE_FSP_M_CONFIG(x) GET_VALUE(x, FSP_M_CONFIG, FspmConfig, FSPM_UPD) +#define GET_VALUE_FSP_M_TEST_CONFIG(x) GET_VALUE(x, FSP_M_TEST_CONFIG, FspmTestConfig, FSPM_UPD) +#define GET_VALUE_FSP_S_CONFIG(x) GET_VALUE(x, FSP_S_CONFIG, FspsConfig, FSPS_UPD) +#define GET_VALUE_FSP_S_TEST_CONFIG(x) GET_VALUE(x, FSP_S_TEST_CONFIG, FspsTestConfig, FSPS_UPD) + bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, size_t size); -int check_signature(u8 addr); +int check_fsp_signature(u8 addr, size_t offset, uint64_t fsp_signature); +int check_board_settings_signature(u8 addr); -- To view, visit https://review.coreboot.org/c/coreboot/+/45686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f83d1ddb455a3d0aaec9757666d161f2091cec2 Gerrit-Change-Number: 45686 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: [UNTESTED] nb/intel/ironlake: Fix some replay issues
by Angel Pons (Code Review) 24 Feb '21

24 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45606 ) Change subject: [UNTESTED] nb/intel/ironlake: Fix some replay issues ...................................................................... [UNTESTED] nb/intel/ironlake: Fix some replay issues Dummy reads followed by writes are actually read-modify-write operations in disassembled binaries. Handling of the scratchpad register 0x2ca8 is still nonsense, but that should be taken care of in a separate commit. Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 64 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45606/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 6c480de..6293c0e 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -316,12 +316,22 @@ MCHBAR16(0x2b9 + (channel << 10)) = si; } +static void toggle_1d0_142_5ff(void) +{ + u32 reg32 = gav(read_1d0(0x142, 3)); + if (reg32 & (1 << 1)) + write_1d0(0, 0x142, 3, 1); + + MCHBAR8(0x5ff) = 0x0; + MCHBAR8(0x5ff) = 0x80; + if (reg32 & (1 << 1)) + write_1d0(0x2, 0x142, 3, 1); +} + static u32 get_580(int channel, u8 addr) { u32 ret; - gav(read_1d0(0x142, 3)); - MCHBAR8(0x5ff) = 0x0; - MCHBAR8(0x5ff) = 0x80; + toggle_1d0_142_5ff(); MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr; MCHBAR8_OR(0x580 + (channel << 10), 1); while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000)) @@ -373,10 +383,9 @@ gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); } - gav(read_1d0(0x142, 3)); // = 0x10408118 - MCHBAR8(0x5ff) = 0x0; - MCHBAR8(0x5ff) = 0x80; + toggle_1d0_142_5ff(); write_1d0(0x2, 0x142, 3, 1); + for (lane = 0; lane < 8; lane++) { // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); info->training.lane_timings[2][channel][slot][rank][lane] = @@ -4176,11 +4185,10 @@ MCHBAR16(0x1220) = 0x1388; } - MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! - MCHBAR32(0x1c04); // !!!! - MCHBAR32(0x1804) = 0x406080; + MCHBAR32_OR(0x2c80, (1 << 24)); + MCHBAR32(0x1804) = MCHBAR32(0x1c04) & ~(1 << 27); - MCHBAR8(0x2ca8); + MCHBAR8(0x2ca8); // !!!! if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); @@ -4195,15 +4203,26 @@ MCHBAR32_OR(0x1af0, 0x10); halt(); } + MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); // !!!! - MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); - MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! + MCHBAR32_AND(0x2c80, ~(1 << 24)); + pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); - MCHBAR16(0x2c20); // !!!! - MCHBAR16(0x2c10); // !!!! - MCHBAR16(0x2c00); // !!!! - MCHBAR16(0x2c00) = 0x8c0; - udelay(1000); + + { + u8 x2c20 = (MCHBAR16(0x2c20) >> 8) & 3; + u16 x2c10 = MCHBAR16(0x2c10); + u16 value = MCHBAR16(0x2c00); + if (x2c20 == 0 && (x2c10 & 0x300) == 0) + value |= (1 << 7); + else + value &= ~(1 << 0); + + MCHBAR16(0x2c00) = value; + } + + udelay(1000); // !!!! + write_1d0(0, 0x33d, 0, 0); write_500(&info, 0, 0, 0xb61, 0, 0); write_500(&info, 1, 0, 0xb61, 0, 0); @@ -4306,8 +4325,9 @@ MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! MCHBAR32(0x1f0) = 0x1d000200; - MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! - MCHBAR8(0x1f0); // !!!! + MCHBAR8_OR(0x1f0, 0x1); + while (MCHBAR8(0x1f0) & 1) + ; program_board_delay(&info); @@ -4318,25 +4338,20 @@ MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ? while (MCHBAR32(0x130) & 1) ; - gav(read_1d0(0x14b, 7)); // = 0x81023100 - write_1d0(0x30, 0x14b, 7, 1); - read_1d0(0xd6, 6); // = 0xfa008080 // !!!! - write_1d0(7, 0xd6, 6, 1); - read_1d0(0x328, 6); // = 0xfa018080 // !!!! - write_1d0(7, 0x328, 6, 1); + + rmw_1d0(0x14b, 0x47, 0x30, 7, 1); + rmw_1d0(0xd6, 0x38, 7, 6, 1); + rmw_1d0(0x328, 0x38, 7, 6, 1); for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 8 : 0); - read_1d0(0x116, 4); // = 0x4040432 // !!!! - write_1d0(2, 0x116, 4, 1); - read_1d0(0xae, 6); // = 0xe8088080 // !!!! - write_1d0(0, 0xae, 6, 1); - read_1d0(0x300, 4); // = 0x48088080 // !!!! - write_1d0(0, 0x300, 6, 1); - MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!! - MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!! + rmw_1d0(0x116, 0xe, 0, 4, 1); + rmw_1d0(0xae, 0x3e, 0, 6, 1); + rmw_1d0(0x300, 0x3e, 0, 6, 1); + MCHBAR16_AND(0x356, 0x7fff); + MCHBAR16_AND(0x756, 0x7fff); MCHBAR32_AND(0x140, ~0x07000000); MCHBAR32_AND(0x138, ~0x07000000); MCHBAR32(0x130) = 0x31111301; @@ -4370,10 +4385,8 @@ write_1d0(2, 0xae, 6, 1); write_1d0(2, 0x300, 6, 1); write_1d0(2, 0x121, 3, 1); - read_1d0(0xd6, 6); // = 0xfa00c0c7 // !!!! - write_1d0(4, 0xd6, 6, 1); - read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!! - write_1d0(4, 0x328, 6, 1); + rmw_1d0(0xd6, 0x38, 4, 6, 1); + rmw_1d0(0x328, 0x38, 4, 6, 1); for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, @@ -4383,12 +4396,17 @@ (info.populated_ranks[0][0][0] << 29); while (MCHBAR8(0x130) & 1) ; - read_1d0(0xa1, 6); // = 0x1cf4054 // !!!! - read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! - read_1d0(0x21c, 6); // = 0xafa00c0 // !!!! - write_1d0(0, 0x21c, 6, 1); - read_1d0(0x14b, 7); // = 0x810231b0 // !!!! - write_1d0(0x35, 0x14b, 7, 1); + + { + u32 reg32 = read_1d0(0xa1, 6); + read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! + rmw_1d0(0x21c, 0x38, 0, 6, 1); + u8 reg8 = 0; + reg8 |= (reg32 >> 4) & (1 << 0); + reg8 |= (reg32 >> 2) & (1 << 1); + reg8 |= (reg32 >> 0) & (1 << 2); + rmw_1d0(0x14b, 0x78, reg8, 7, 1); + } for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, @@ -4443,8 +4461,8 @@ MCHBAR8(0x12c) = 0x9f; - MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!! - MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! + MCHBAR8_AND_OR(0x271, 0xcf, 0xe); + MCHBAR8_AND_OR(0x671, 0xcf, 0xe); if (!s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -4469,8 +4487,7 @@ write_1d0(7, 0x1c0, 3, 1); write_1d0(4, 0x1c6, 4, 1); write_1d0(4, 0x1cc, 4, 1); - read_1d0(0x151, 4); // = 0x408c6d74 // !!!! - write_1d0(4, 0x151, 4, 1); + rmw_1d0(0x151, 0xf, 0x4, 4, 1); MCHBAR32(0x584) = 0xfffff; MCHBAR32(0x984) = 0xfffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/45606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec Gerrit-Change-Number: 45606 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/prodrive/hermes/hda_verb: Fix some issues
by Patrick Rudolph (Code Review) 24 Feb '21

24 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44772 ) Change subject: mb/prodrive/hermes/hda_verb: Fix some issues ...................................................................... mb/prodrive/hermes/hda_verb: Fix some issues * Use correct NID port mapping * Fix verb count in ACL888 header * Fix NID in Intel codec verbs * Add more NIDs Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/hda_verb.c 1 file changed, 74 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44772/1 diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 59b8aa6..6cde639 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -5,47 +5,11 @@ const u32 cim_verb_data[] = { 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ 0x10ec0888, /* Subsystem ID */ - 10, /* Number of 4 dword sets */ + 13, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10ec0888), - /* Port A: Front, Audio Header #1 */ - AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( - INTEGRATED, - INTERNAL, - SPECIAL7, - LINE_OUT, - OTHER_ANALOG, - COLOR_UNKNOWN, - false, - 0xf, - 0 - )), - /* Port B: Mic1, Line input (pink) */ - AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( - JACK, - EXTERNAL_PRIMARY_CHASSIS, - REAR, //FIXME - LINE_IN, - STEREO_MONO_1_8, - PINK, - false, - 0xf, - 0 - )), - /* Port C: Line, Speaker (only L) */ - AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( - INTEGRATED, - INTERNAL, - NA, - SPEAKER, - TYPE_UNKNOWN, - COLOR_UNKNOWN, - false, - 0xf, - 0 - )), /* Port D: Sidesurr, Line out (green) */ - AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC( + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( //JACK, LINE_OUT, EXTERNAL_PRIMARY_CHASSIS, @@ -57,14 +21,50 @@ 0xf, 0 )), - /* Port E: Line2, Line input (blue) */ + /* Port A: Front, Audio Header #1 */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + INTEGRATED, + INTERNAL, + SPECIAL7, + LINE_OUT, + OTHER_ANALOG, + COLOR_UNKNOWN, + false, + 0xf, + 0 + )), + /* Port G: Not connected */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + NC, + LOCATION_OTHER, + NA, + DEVICE_OTHER, + TYPE_OTHER, + COLOR_OTHER, + true, + 0, + 0 + )), + /* Port H: Not connected */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC( + NC, + LOCATION_OTHER, + NA, + DEVICE_OTHER, + TYPE_OTHER, + COLOR_OTHER, + true, + 0, + 0 + )), + /* Port B: Mic1, Line input (pink) */ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( JACK, EXTERNAL_PRIMARY_CHASSIS, REAR, //FIXME LINE_IN, STEREO_MONO_1_8, - BLUE, + PINK, false, 0xf, 0 @@ -81,20 +81,32 @@ 0xf, 0 )), - /* Port G: Not connected */ + /* Port C: Line, Speaker (only L) */ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( - NC, - LOCATION_OTHER, + INTEGRATED, + INTERNAL, NA, - DEVICE_OTHER, - TYPE_OTHER, - COLOR_OTHER, - true, - 0, + SPEAKER, + TYPE_UNKNOWN, + COLOR_UNKNOWN, + false, + 0xf, 0 )), - /* Port H: Not connected */ + /* Port E: Line2, Line input (blue) */ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + JACK, + EXTERNAL_PRIMARY_CHASSIS, + REAR, //FIXME + LINE_IN, + STEREO_MONO_1_8, + BLUE, + false, + 0xf, + 0 + )), + /* Port CD: Not connected */ + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_DESC( NC, LOCATION_OTHER, NA, @@ -105,6 +117,8 @@ 0, 0 )), + /* BEEPIN: This NID is also used as SSID. Use magic constant to satisfy the driver. */ + AZALIA_PIN_CFG(0, 0x1d, 0x4000c601), /* S/PDIF-OUT */ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( @@ -131,16 +145,16 @@ 0 )), - //FIXME COdec ID /* * VerbTable: CFL Display Audio Codec * Revision ID = 0xFF * Codec Vendor: 0x8086280B */ - 0x8086280B, 0xFFFFFFFF, - 5, /* Number of 4 dword sets */ + 6, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), /* * Display Audio Verb Table @@ -148,10 +162,10 @@ * Port to be exposed to the inbox driver in the vanilla mode * PORT C - BIT[7:6] = 01b */ - 0x00878140, - 0x00878140, - 0x00878140, - 0x00878140, + 0x02878140, + 0x02878140, + 0x02878140, + 0x02878140, /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ AZALIA_PIN_CFG(2, 0x05, 0x18560010), /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ @@ -159,10 +173,10 @@ /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ AZALIA_PIN_CFG(2, 0x07, 0x18560030), /* Disable the third converter and third Pin (NID 08h) */ - 0x00878140, - 0x00878140, - 0x00878140, - 0x00878140, + 0x02878140, + 0x02878140, + 0x02878140, + 0x02878140, }; const u32 pc_beep_verbs[0] = {}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef Gerrit-Change-Number: 44772 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: soc/intel/cannonlake: Improve memcfg comments
by Angel Pons (Code Review) 23 Feb '21

23 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46250 ) Change subject: soc/intel/cannonlake: Improve memcfg comments ...................................................................... soc/intel/cannonlake: Improve memcfg comments Instead of repeating what the FSP-M UPDs say, explain how to correctly configure these settings. DQ and DQS byte maps differ between actual Cannon Lake and Coffee Lake et alia, so skip these comments for now. Change-Id: I1142ab500fd18176b174a5080f78c5c566c9ce25 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 1 file changed, 29 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46250/1 diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index 28af731..2e4dfcf 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -32,7 +32,7 @@ enum mem_info_read_type { NOT_EXISTING, /* No memory in this slot */ - READ_SMBUS, /* Read on-module spd by SMBUS. */ + READ_SMBUS, /* Read on-module spd by SMBUS */ READ_SPD_CBFS, /* Find spd file in CBFS. */ READ_SPD_MEMPTR /* Find spd data from pointer. */ }; @@ -40,20 +40,23 @@ struct spd_info { enum mem_info_read_type read_type; union spd_data_by { - /* To read on-module spd when read_type is READ_SMBUS. */ + /* To read on-module spd when read_type is READ_SMBUS */ uint8_t spd_smbus_address; - /* To identify spd file when read_type is READ_SPD_CBFS. */ + /* To identify spd file when read_type is READ_SPD_CBFS */ int spd_index; - /* To find spd data when read_type is READ_SPD_MEMPTR. */ + /* To find spd data when read_type is READ_SPD_MEMPTR */ struct spd_by_pointer spd_data_ptr_info; } spd_spec; }; -/* Board-specific memory dq mapping information */ +/* Board-specific memory parameters */ struct cnl_mb_cfg { - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + /* + * Specify where to find the memory parameters for each slot, or the + * memory-down equivalent of a slot. Leave unpopulated slots blank. + */ struct spd_info spd[NUM_DIMM_SLOT]; /* @@ -83,39 +86,45 @@ uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + * Rcomp resistor values in ohms. For socketed platforms, they are + * located on the CPU package itself and their values are always + * the same. For soldered CPUs, the resistors are on the mainboard, + * connected to the DDR_RCOMP_[2:0] pins of the processor. The PDG + * can provide the RCOMP resistor values for each memory topology. + * + * For socketed CPUs, the resistor values are: { 121, 75, 100 }; + * For soldered-down CPUs, check schematics or use the PDG values. */ uint16_t rcomp_resistor[3]; /* - * Rcomp target values. These will typically be the following - * values for Cannon Lake : { 80, 40, 40, 40, 30 } + * Rcomp target values. These depend on the platform topology and + * can be determined using Intel document #573387 or left blank. */ uint16_t rcomp_targets[5]; /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. + * Indicates whether memory is interleaved. Refer to volume 1 of + * the datasheet for pictures of interleaved and non-interleaved + * configurations. Memory will never work with the wrong value. */ uint8_t dq_pins_interleaved; /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + * VREF_CA configuration. For DDR3 and LPDDR, choose config 0. + * Config 1 is not meant to be used. For DDR4, use config 2. */ uint8_t vref_ca_config; - /* Early Command Training Enabled */ + /* + * Early Command Training is a no-op for DDR4, and is necessary + * for LPDDR. If unsure, set to 1. MRC will skip ECT on DDR4. + */ uint8_t ect; }; /* - * Initialize default memory configurations for CannonLake. + * Write memory settings into the corresponding FSP-M UPDs. */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, const struct cnl_mb_cfg *cnl_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/46250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1142ab500fd18176b174a5080f78c5c566c9ce25 Gerrit-Change-Number: 46250 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: sb/intel/i82801gx/acpi/globalnvs.h: Add some Offset lines
by Angel Pons (Code Review) 23 Feb '21

23 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43160 ) Change subject: sb/intel/i82801gx/acpi/globalnvs.h: Add some Offset lines ...................................................................... sb/intel/i82801gx/acpi/globalnvs.h: Add some Offset lines Looks like i82801ix and i82801jx have those. Adding them does no harm. Change-Id: Iad9699709f3e90670f2d4f9b5664a048971ea412 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/acpi/globalnvs.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43160/1 diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 848005d..0a0f255 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -15,6 +15,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ + Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter @@ -32,6 +33,7 @@ LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ + Offset (0x14), ACTT, 8, // 0x14 - active trip point TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 @@ -70,6 +72,7 @@ UTIL, 8, // 0x3a - ACIN, 8, // 0x3b - /* Integrated Graphics Device */ + Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List -- To view, visit https://review.coreboot.org/c/coreboot/+/43160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad9699709f3e90670f2d4f9b5664a048971ea412 Gerrit-Change-Number: 43160 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: device/pci: Ensure full 16-bit VGA port i/o decoding
by Nico Huber (Code Review) 22 Feb '21

22 Feb '21

Hello Kyösti Mälkki, Patrick Rudolph, Michael Niewöhner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35516 to review the following change. Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding ...................................................................... device/pci: Ensure full 16-bit VGA port i/o decoding So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in random conflicts. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As we don't want to clutter our i/o port space, we'll now simply fail for VGA behind bridges that don't support it. Famous last words: I assume there can't be many bridges left that don't support this bit ;) Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/device.c M src/device/pci_device.c M src/include/device/device.h M src/include/device/pci_def.h 4 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35516/1 diff --git a/src/device/device.c b/src/device/device.c index 44d1f95..523bd1c 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -757,6 +757,12 @@ while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { if (!dev->enabled) continue; + if (dev->bus->no_vga) { + printk(BIOS_WARNING, "Ignoring VGA at %s" + ", a bridge on the path isn't supported", + dev_path(dev)); + continue; + } printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); @@ -797,7 +803,7 @@ while (bus) { printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", dev_path(bus->dev)); - bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; + bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16; bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ecb652..2fadb55 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -788,6 +788,43 @@ }; /** + * Check for compatibility to route legacy VGA cycles through a bridge. + * + * Originally, when decoding i/o ports for legacy VGA cycles, bridges + * should only consider the 10 least significant bits of the port address. + * This means all VGA registers were aliased every 1024 ports! + * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. + * + * To avoid this mess, a bridge control bit (VGA16) was introduced in + * 2003 to enable decoding of 16-bit port addresses. As we don't want + * to clutter our i/o port space, we simply fail for VGA behind bridges + * that don't support it (set .no_vga = 1). + */ +static void pci_bridge_vga_compat(struct bus *const bus) +{ + uint16_t bridge_ctrl; + + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + /* Ensure VGA decoding is disabled during probing (it should + be by default, but we run blobs nowadays) */ + bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + + /* If the upstream bridge doesn't support VGA, we don't have to check */ + bus->no_vga |= bus->dev->bus->no_vga; + if (bus->no_vga) + return; + + /* Test if we can enable 16-bit decoding */ + bridge_ctrl |= PCI_BRIDGE_CTL_VGA16; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + bus->no_vga = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16); +} + +/** * Detect the type of downstream bridge. * * This function is a heuristic to detect which type of bus is downstream @@ -1288,6 +1325,8 @@ bus = dev->link_list; + pci_bridge_vga_compat(bus); + pci_bridge_route(bus, PCI_ROUTE_SCAN); do_scan_bus(bus, 0x00, 0xff); diff --git a/src/include/device/device.h b/src/include/device/device.h index b2221cc..78e234e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -94,6 +94,7 @@ unsigned int reset_needed : 1; unsigned int disable_relaxed_ordering : 1; unsigned int ht_link_up : 1; + unsigned int no_vga : 1; /* We can't support VGA behind this bridge */ }; /* diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..c8b86d5 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -138,6 +138,7 @@ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ /* Fast Back2Back enabled on secondary interface */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Gerrit-Change-Number: 35516 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 26

Change in coreboot[master]: Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"
by Angel Pons (Code Review) 21 Feb '21

21 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46955 ) Change subject: Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL" ...................................................................... Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL" This reverts commit 1a25c9cdfd3fd391328133ba94c63ecd1083e4f8. Reason for revert: No longer necessary. Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/gpio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46955/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 358bdec..6ae1f0f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -18,7 +18,7 @@ 0x00000000, // AddressMinimum 0x00000000, // AddressMaximum 0x00000000, // AddressTranslation - 0x00000001, // RangeLength + 0x00000000, // RangeLength , // ResourceSourceIndex , // ResourceSource BAR0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842 Gerrit-Change-Number: 46955 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020