coreboot-gerrit October 2020

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Change in coreboot[master]: src/cpu/x86/mtrr: Convert to 96 characters line length
by HAOUAS Elyes (Code Review) 09 Feb '21

09 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44309 ) Change subject: src/cpu/x86/mtrr: Convert to 96 characters line length ...................................................................... src/cpu/x86/mtrr: Convert to 96 characters line length Change-Id: I2525c2f3cbdd7b7137c3b60ad8a44ed6ebdb8909 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/mtrr/debug.c 1 file changed, 12 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44309/1 diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index 4ecae06..f7eb97e 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -18,8 +18,8 @@ } } -static void display_mtrr_fixed_types(uint64_t msr, - uint32_t starting_address, uint32_t memory_size) +static void display_mtrr_fixed_types(uint64_t msr, uint32_t starting_address, + uint32_t memory_size) { uint32_t base_address; uint32_t index; @@ -31,25 +31,21 @@ base_address = starting_address; next_address = base_address; for (index = 0; index < 64; index += 8) { - next_address = starting_address + (memory_size * - ((index >> 3) + 1)); + next_address = starting_address + (memory_size * ((index >> 3) + 1)); next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; if (next_type != type) { printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, - display_mtrr_type(type)); + base_address, next_address - 1, display_mtrr_type(type)); base_address = next_address; type = next_type; } } if (base_address != next_address) - printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", - base_address, next_address - 1, + printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", base_address, next_address - 1, display_mtrr_type(type)); } -static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) +static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, const char *name) { union { uint64_t u64; @@ -61,8 +57,7 @@ display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } -static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, - const char *name) +static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, const char *name) { union { uint64_t u64; @@ -91,8 +86,7 @@ msr_t msr; msr = rdmsr(MTRR_CAP_MSR); - printk(BIOS_DEBUG, - "0x%08x%08x: IA32_MTRRCAP: %s%s%s%s%u variable MTRRs\n", + printk(BIOS_DEBUG, "0x%08x%08x: IA32_MTRRCAP: %s%s%s%s%u variable MTRRs\n", msr.hi, msr.lo, (msr.lo & MTRR_CAP_PRMRR) ? "PRMRR, " : "", (msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "", @@ -113,8 +107,7 @@ msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - display_mtrr_type((uint32_t)(msr.u64 & - MTRR_DEF_TYPE_MASK))); + display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); } static void display_variable_mtrr(int index, uint64_t address_mask) @@ -137,19 +130,16 @@ if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; - printk(BIOS_DEBUG, - "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", + printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", msr_a.u64, index, base_address, display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; length = (~mask & address_mask) + 1; - printk(BIOS_DEBUG, - "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", + printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Length = 0x%016llx, Valid\n", msr_m.u64, index, length); } else { printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d\n", msr_a.u64, index); - printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", - msr_m.u64, index); + printk(BIOS_DEBUG, "0x%016llx: PHYMASK%d: Disabled\n", msr_m.u64, index); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2525c2f3cbdd7b7137c3b60ad8a44ed6ebdb8909 Gerrit-Change-Number: 44309 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch: Simplify PCI RMW operations
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46891 ) Change subject: soc/intel/broadwell/pch: Simplify PCI RMW operations ...................................................................... soc/intel/broadwell/pch: Simplify PCI RMW operations This reduces the differences between Lynx Point and Broadwell. Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/broadwell/pch/pcie.c 3 files changed, 33 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46891/1 diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/soc/intel/broadwell/pch/early_pch.c index 0c4dd7b..b0fd801 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/soc/intel/broadwell/pch/early_pch.c @@ -73,7 +73,7 @@ enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ - pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); - pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); - pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); + pci_and_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60); + pci_or_config32(_PCH_DEV(PCIE, 0), 0xf4, 0x80); + pci_or_config32(_PCH_DEV(PCIE, 0), 0xe2, 0x30); } diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c index c9debf2..4b8f3a7 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -167,8 +167,6 @@ static void broadwell_pch_enable_dev(struct device *dev) { - u16 reg16; - if (dev->path.type != DEVICE_PATH_PCI) return; @@ -187,10 +185,8 @@ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable this device if possible */ pch_disable_devfn(dev); diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 7b7b504..f43fa78 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -120,7 +120,7 @@ rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); - pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_or_config8(dev, 0xe2, 3 << 4); const struct soc_intel_broadwell_pch_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; } @@ -150,7 +150,7 @@ break; } - pci_update_config32(dev, 0x418, 0, 0x02000430); + pci_write_config32(dev, 0x418, 0x02000430); if (root_port_is_first(dev)) { /* @@ -212,23 +212,23 @@ if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pci_update_config8(dev, 0xe1, 0xc3, 0x3c); + pci_or_config8(dev, 0xe1, 0x3c); - pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_or_config8(dev, 0xe2, 3 << 4); + pci_or_config32(dev, 0x420, 1 << 31); /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) - pci_update_config32(dev, 0x420, ~0, (3 << 29)); + pci_or_config32(dev, 0x420, 3 << 29); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } else if (rp == 5 || rp == 6) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } continue; } @@ -236,17 +236,17 @@ enabled_ports++; /* Enable dynamic clock gating. */ - pci_update_config8(dev, 0xe1, 0xfc, 0x03); - pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_or_config8(dev, 0xe1, 0x03); + pci_or_config8(dev, 0xe2, 1 << 6); pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); /* Update PECR1 register. */ - pci_update_config8(dev, 0xe8, ~0, 3); + pci_or_config8(dev, 0xe8, 3); + if (is_broadwell) { - pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)), - ((1 << 5) | (1 << 14))); + pci_or_config32(dev, 0x324, (1 << 5) | (1 << 14)); } else { - pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5)); + pci_or_config32(dev, 0x324, 1 << 5); } /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) @@ -254,19 +254,18 @@ * In addition to D28Fx PCICFG 420h[30:29] = 11b, * set 420h[17] = 0b and 420[0] = 1b for L1 SubState. */ - pci_update_config32(dev, 0x420, ~0x20000, - (3 << 29) | 1); + pci_update_config32(dev, 0x420, ~(1 << 17), (3 << 29) | 1); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pci_update_config8(dev, 0xe1, 0xc3, 0x3c); + pci_or_config8(dev, 0xe1, 0x3c); /* CLKREQ# VR Idle Enable */ RCBA32_OR(0x2b1c, (1 << (16 + i))); } if (!enabled_ports) - pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_or_config8(rpc.ports[0], 0xe1, 1 << 6); } static void root_port_commit_config(void) @@ -298,7 +297,7 @@ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ - pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26); + pci_or_config32(dev, 0x338, 1 << 26); do { reg32 = pci_read_config32(dev, 0x328); @@ -312,7 +311,7 @@ printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n", dev_path(dev)); - pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27); + pci_or_config32(dev, 0x408, 1 << 27); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -536,17 +535,15 @@ pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74); /* Set Invalid Receive Range Check Enable in MPC register. */ - pci_update_config32(dev, 0xd8, ~0, (1 << 25)); + pci_or_config32(dev, 0xd8, 1 << 25); - pci_update_config8(dev, 0xf5, 0x0f, 0); + pci_and_config8(dev, 0xf5, 0x0f); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ if (CONFIG(PCIEXP_AER)) - pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, - (1 << 29) | 0x10001); + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); else - pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, - (1 << 29)); + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ if (CONFIG(PCIEXP_L1_SUB_STATE)) @@ -554,10 +551,10 @@ else pci_update_config32(dev, 0x200, ~0xfffff, 0); - pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), - (1 << 20) | (3 << 6)); + pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); + /* Enable Relaxed Order from Root Port. */ - pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23)); + pci_or_config32(dev, 0x320, 3 << 23); if (rp == 1 || rp == 5 || rp == 6) pci_update_config8(dev, 0xf7, ~0xc, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/46891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472 Gerrit-Change-Number: 46891 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Use common MADT code
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46889 ) Change subject: soc/intel/broadwell: Use common MADT code ...................................................................... soc/intel/broadwell: Use common MADT code Change-Id: I48d4b522009eee9053d247217ca03d8bfea80cdf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pch/Makefile.inc D src/soc/intel/broadwell/pch/acpi.c 3 files changed, 1 insertion(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46889/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6e57f0a..ecb8299 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -19,6 +19,7 @@ select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 119534f..1c19613 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -1,6 +1,5 @@ bootblock-y += bootblock.c -ramstage-y += acpi.c ramstage-y += adsp.c romstage-y += early_pch.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c deleted file mode 100644 index 4b307a1..0000000 --- a/src/soc/intel/broadwell/pch/acpi.c +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 0, 2, 0); - - /* SCI */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48d4b522009eee9053d247217ca03d8bfea80cdf Gerrit-Change-Number: 46889 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch: Drop `acpi_sci_irq` function
by Angel Pons (Code Review) 09 Feb '21

09 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46888 ) Change subject: soc/intel/broadwell/pch: Drop `acpi_sci_irq` function ...................................................................... soc/intel/broadwell/pch: Drop `acpi_sci_irq` function The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using common MADT code on Broadwell, hardcode it as 9 everywhere. Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/pmutil.c 4 files changed, 2 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46888/1 diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 14aa9ce..4b307a1 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -1,18 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <acpi/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <types.h> -#include <soc/intel/broadwell/pch/pch.h> -#include <soc/intel/broadwell/pch/pm.h> unsigned long acpi_fill_madt(unsigned long current) { - int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - /* Local APICs */ current = acpi_create_madt_lapics(current); @@ -22,14 +15,9 @@ /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 0, 2, 0); - if (sci >= 20) - flags |= MP_IRQ_POLARITY_LOW; - else - flags |= MP_IRQ_POLARITY_HIGH; - /* SCI */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, sci, sci, flags); + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); return current; } diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index e30941e..5679541 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -10,7 +10,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = 9; if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/soc/intel/broadwell/pch/pm.h index 352394c..40467ed 100644 --- a/src/soc/intel/broadwell/pch/pm.h +++ b/src/soc/intel/broadwell/pch/pm.h @@ -139,9 +139,6 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); -/* Return the selected ACPI SCI IRQ */ -int acpi_sci_irq(void); - /* STM Support */ uint16_t get_pmbase(void); diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 401431a..cc61715 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -413,34 +413,6 @@ outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } -int acpi_sci_irq(void) -{ - int scis = pci_read_config32(PCH_DEV_LPC, ACPI_CNTL) & SCI_IRQ_SEL; - int sci_irq = 9; - - /* Determine how SCI is routed. */ - switch (scis) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = scis - SCIS_IRQ9 + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = scis - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - int platform_is_resuming(void) { if (!(inw(get_pmbase() + PM1_STS) & WAK_STS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/46888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922 Gerrit-Change-Number: 46888 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/aopen: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 09 Feb '21

09 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46075 ) Change subject: mb/aopen: Convert to ASL 2.0 syntax ...................................................................... mb/aopen: Convert to ASL 2.0 syntax Change-Id: Ib473121acfc0e985d4c0debecffdc1efbd9c3d66 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl M src/mainboard/aopen/dxplplusu/acpi/i82801db.asl 2 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46075/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl index 7216d33..dd8689b 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -36,26 +36,26 @@ CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM) CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM) - And (\_SB.PCI0.RLAR, 0x03FF, Local1) - Increment (Local1) - If (LGreater (Local1, 0x40)) + Local1 = \_SB.PCI0.RLAR & 0x03FF + Local1++ + If (Local1 > 0x40) { - ShiftLeft (Local1, 0x1A, LELM) + LELM = Local1 << 26 } CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00) CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01) CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2) - And (\_SB.PCI0.TOLM, 0xF800, Local1) - ShiftRight (Local1, 0x04, Local1) - Decrement (Local1) - If (LGreater (Local1, 0x10)) + Local1 = \_SB.PCI0.TOLM & 0xF800 + Local1 >>= 4 + Local1-- + If (Local1 > 0x10) { - Subtract (Local1, 0x0F, Local1) - Store (ShiftLeft (Local1, 0x14), MEM2) - Store (0x01000000, MS00) - Store (MS00, MS01) + Local1 -= 15 + MEM2 = Local1 << 20 + MS00 = 0x01000000 + MS01 = MS00 } Return (MSBF) diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index 20400c3..4c91abc 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -112,29 +112,29 @@ CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2) CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL) - Store (PBAR, Local0) - If ( Land(Local0, 0x01) ) + Local0 = PBAR + If (Local0 & 0x01) { - And (Local0, 0xFFFE, Local0) - Store (Local0, IOA1) - Store (Local0, IOA2) - Store (0x80, IOAL) + Local0 &= 0xFFFE + IOA1 = Local0 + IOA2 = Local0 + IOAL = 0x80 } Else { - Store (0x00, IOAL) + IOAL = 0x00 } CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1) CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2) CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL) - Store (GBAR, Local0) - If ( Land(Local0, 0x01) ) { - And (Local0, 0xFFFE, Local0) - Store (Local0, IOS1) - Store (Local0, IOS2) - Store (0x40, IOSL) + Local0 = GBAR + If (Local0 & 0x01) { + Local0 &= 0xFFFE + IOS1 = Local0 + IOS2 = Local0 + IOSL = 0x40 } Else { - Store (0x00, IOSL) + IOSL = 0x00 } Return (MSBF) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib473121acfc0e985d4c0debecffdc1efbd9c3d66 Gerrit-Change-Number: 46075 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/amd/stoneyridge: Move some SMI utility functions
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42989 ) Change subject: soc/amd/stoneyridge: Move some SMI utility functions ...................................................................... soc/amd/stoneyridge: Move some SMI utility functions Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/gpio.c D src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c 5 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42989/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0d7b5d1..09320b2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -64,7 +64,6 @@ ramstage-y += pmutil.c ramstage-y += sata.c ramstage-y += memmap.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index a595014..bd9d1b1 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -33,11 +33,6 @@ { GPIO_69, GEVENT_17 }, }; -void soc_route_sci(uint8_t event) -{ - smi_write8(SMI_SCI_MAP(event), event); -} - void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { *table = gpio_event_table; diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c deleted file mode 100644 index fb6d348..0000000 --- a/src/soc/amd/stoneyridge/smi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> -#include <soc/smi.h> - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b..b65bfc0 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> @@ -56,6 +57,27 @@ smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + /** * Configure generation of SCIs. */ diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index be55458..a36ab73 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -287,10 +287,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Gerrit-Change-Number: 42989 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/amd/picasso: Move some SMI utility functions
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42988 ) Change subject: soc/amd/picasso: Move some SMI utility functions ...................................................................... soc/amd/picasso: Move some SMI utility functions Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/gpio.c D src/soc/amd/picasso/smi.c M src/soc/amd/picasso/smi_util.c M src/soc/amd/picasso/smihandler.c 5 files changed, 22 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42988/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..9a72d60 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -61,7 +61,6 @@ ramstage-y += acp.c ramstage-y += sata.c ramstage-y += memmap.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c index c402fb5..47c005e 100644 --- a/src/soc/amd/picasso/gpio.c +++ b/src/soc/amd/picasso/gpio.c @@ -33,11 +33,6 @@ { GPIO_129, GEVENT_17 }, }; -void soc_route_sci(uint8_t event) -{ - smi_write8(SMI_SCI_MAP(event), event); -} - void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { *table = gpio_event_table; diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c deleted file mode 100644 index fb6d348..0000000 --- a/src/soc/amd/picasso/smi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <amdblocks/acpimmio.h> -#include <soc/southbridge.h> -#include <soc/smi.h> - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b..b65bfc0 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> @@ -56,6 +57,27 @@ smi_write32(SMI_REG_SMITRIG0, reg32); } +/** Set the EOS bit and enable SMI generation from southbridge */ +void global_smi_enable(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + /** * Configure generation of SCIs. */ diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 992dc2b..a9a2b2e 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -291,10 +291,3 @@ if (smi_src & SMI_STATUS_SRC_4) process_smi_sources(SMI_REG_SMISTS4); } - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Gerrit-Change-Number: 42988 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd/picasso: Move APM_CNT_SMMINFO callsite
by Kyösti Mälkki (Code Review) 09 Feb '21

09 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42987 ) Change subject: soc/amd/picasso: Move APM_CNT_SMMINFO callsite ...................................................................... soc/amd/picasso: Move APM_CNT_SMMINFO callsite Triggering SMI is not part of the semantics of global_smi_enable(). Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/smi.c 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/42987/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c42f400..6c6149f 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -85,12 +85,18 @@ smm_state->smbase = staggered_smbase; } +static void post_mp_init(void) +{ + global_smi_enable(); + apm_control(APM_CNT_SMMINFO); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = relocation_handler, - .post_mp_init = global_smi_enable, + .post_mp_init = post_mp_init, }; void mp_init_cpus(struct bus *cpu_bus) diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 125dde6..fb6d348 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -4,7 +4,6 @@ * Utilities for SMM setup */ -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <amdblocks/acpimmio.h> @@ -18,6 +17,4 @@ reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); - - outb(APM_CNT_SMMINFO, APM_CNT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Gerrit-Change-Number: 42987 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/amd/gardenia: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 09 Feb '21

09 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46145 ) Change subject: mb/amd/gardenia: Convert to ASL 2.0 syntax ...................................................................... mb/amd/gardenia: Convert to ASL 2.0 syntax Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/gardenia/acpi/sleep.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46145/1 diff --git a/src/mainboard/amd/gardenia/acpi/sleep.asl b/src/mainboard/amd/gardenia/acpi/sleep.asl index 89c6fa1..0cbf8e3 100644 --- a/src/mainboard/amd/gardenia/acpi/sleep.asl +++ b/src/mainboard/amd/gardenia/acpi/sleep.asl @@ -26,10 +26,10 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, PEWD) - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + PEWD = 0 + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 } /* End Method(\_PTS) */ /* -- To view, visit https://review.coreboot.org/c/coreboot/+/46145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec Gerrit-Change-Number: 46145 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/amd/olivehill: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 09 Feb '21

09 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46147 ) Change subject: mb/amd/olivehill: Convert to ASL 2.0 syntax ...................................................................... mb/amd/olivehill: Convert to ASL 2.0 syntax Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/olivehill/acpi/sleep.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46147/1 diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl index 47dd146..fc26c30 100644 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ b/src/mainboard/amd/olivehill/acpi/sleep.asl @@ -30,9 +30,9 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -56,7 +56,7 @@ /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ - Store(1,USBS) + USBS = 1 \_SB.AWAK(Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669 Gerrit-Change-Number: 46147 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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