coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Angel Pons, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45954 to look at the new patch set (#17). Change subject: soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling ...................................................................... soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0. Test: clevo/l140cu and supermicro/x11ssm-f have the PM ACPI timer disable bit set when EnableTcoTimer=0. Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c 4 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45954/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/45954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Gerrit-Change-Number: 45954 Gerrit-PatchSet: 17 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skl: guard ACPI PM timer emulation enablement
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45953 to look at the new patch set (#18). Change subject: soc/intel/skl: guard ACPI PM timer emulation enablement ...................................................................... soc/intel/skl: guard ACPI PM timer emulation enablement Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. This is what FSP does and what coreboot does for CNL. Test: supermicro/x11ssm-f boots fine without any errors in dmesg Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/cpu.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45953/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/45953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Gerrit-Change-Number: 45953 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skl: guard ACPI PM timer emulation enablement
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45953 to look at the new patch set (#17). Change subject: soc/intel/skl: guard ACPI PM timer emulation enablement ...................................................................... soc/intel/skl: guard ACPI PM timer emulation enablement Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. This is what FSP does and what coreboot does for CNL. Test: supermicro/x11ssm-f boots fine without any errors in dmesg Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/cpu.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45953/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/45953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Gerrit-Change-Number: 45953 Gerrit-PatchSet: 17 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skl: guard ACPI PM timer emulation enablement
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45953 to look at the new patch set (#16). Change subject: soc/intel/skl: guard ACPI PM timer emulation enablement ...................................................................... soc/intel/skl: guard ACPI PM timer emulation enablement Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. This is what FSP does and what coreboot does for CNL. Test: supermicro/x11ssm-f boots fine without any errors in dmesg Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/cpu.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45953/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/45953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Gerrit-Change-Number: 45953 Gerrit-PatchSet: 16 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45951 to look at the new patch set (#13). Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the socs above. Deduplicate it by moving it to common code. Note: The ACPI timer emulation can only be used by SoCs with ucode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/pm_timer_emulation.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 9 files changed, 41 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Johnny Lin (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Marc Jones, Patrick Georgi, Martin Roth, John Looney, Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45798 to look at the new patch set (#7). Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width, voltage and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ddr.c A src/soc/intel/xeon_sp/cpx/include/soc/ddr.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 6 files changed, 216 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45798/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 7 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17
by Johnny Lin (Code Review) 05 Oct '20

05 Oct '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45799 ) Change subject: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17 ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/45799/5/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/45799/5/src/mainboard/ocp/deltalak… PS5, Line 246: dimm_locator[dimm->channel_num] > I would just do: […] Do you mean like A0, A1 ..,etc? I use the same location string definitions in UEFI BIOS (A0, B0 ..F0). -- To view, visit https://review.coreboot.org/c/coreboot/+/45799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Gerrit-Change-Number: 45799 Gerrit-PatchSet: 7 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 05 Oct 2020 07:15:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Johnny Lin (Code Review) 05 Oct '20

05 Oct '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 41: save_dimm_info > that's a candidate for soc/intel/common, isn't it? The save_dimm_info() and the SystemMemoryMapHob struct are both Cooper Lake specific, they cannot be used for other Intel platforms so I'm not sure if it can be moved to intel/common. https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 79: 0x1a > Why hardcode? actKeyByte2 might work. actKeyByte2 is SPD Byte 3: Module type information for SPD_RDIMM, SPD_UDIMM, SPD_SODIMM., etc. https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 88: 1200 > Looks like FSP might store this in the SystemMemoryMapHob struct but headers expose it as reserved. Yes you are right, but CPX does not support DDR5 and DDR4 should be the only option in use, I am not sure if adding the code for them are beneficial. If it's preferred then I will need to expose more hob data. -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 05 Oct 2020 07:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field
by Johnny Lin (Code Review) 05 Oct '20

05 Oct '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/memory.h: https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… PS4, Line 47: uint16_t get_max_memory_speed(uint32_t commonTck) > It is large, though. I'd move it into its own . […] Add the .c and move them to CB:45798 ddr.h ddr.c -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 05 Oct 2020 06:53:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Johnny Lin (Code Review) 05 Oct '20

05 Oct '20

Hello Marc Jones, Patrick Georgi, Martin Roth, John Looney, Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45798 to look at the new patch set (#6). Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width, voltage and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ddr.c A src/soc/intel/xeon_sp/cpx/include/soc/ddr.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 6 files changed, 217 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45798/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020