coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Nico Huber (Code Review) 04 Oct '20

04 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… PS10, Line 389: freq Below `frequency` means the timer. Name it `clock`? -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 04 Oct 2020 16:26:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: drop duplicate PM ACPI timer ...
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45958 to look at the new patch set (#15). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: drop duplicate PM ACPI timer disabling ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there is no need to do it again in coreboot. Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/finalize.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 17 files changed, 4 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45952 to look at the new patch set (#13). Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... soc/intel/common: add Kconfig to enable/disable the ACPI PM timer Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Also, make the TCO SMI option depend on ACPI PM timer, since it won't work without it. The Kconfig option depends on CTC (Common Timer Copy), which the SoC has to support to do PM ACPI timer emulation. This new Kconfig gets used in the follow-up commits of this series. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/smm/Kconfig 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/45952/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45951 to look at the new patch set (#10). Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the socs above. Deduplicate it by moving it to common code. Note: The ACPI timer emulation can only be used by SoCs with ucode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 8 files changed, 40 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/*: conversion from constant to Kconfig for XTAL frequency
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46018 to look at the new patch set (#5). Change subject: soc/intel/*: conversion from constant to Kconfig for XTAL frequency ...................................................................... soc/intel/*: conversion from constant to Kconfig for XTAL frequency This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/elkhartlake/include/soc/cpu.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/cpu.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/cpu.h 25 files changed, 68 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46018/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Angel Pons (Code Review) 04 Oct '20

04 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/45951/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45951/9//COMMIT_MSG@7 PS9, Line 7: elh EHL: ElkHartLake -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 04 Oct 2020 15:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl
by Subrata Banik (Code Review) 04 Oct '20

04 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46004 ) Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ...................................................................... soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl This patch moves common PCIE RP ASL devices into common block acpi directory as part of pcie_rp_xx_xx to avoid duplicating the same ASL code block across SoC directory. For PCH-LP pcie_rp_1_8.asl => To hold RP01-RP08 entries refer as 0:0x1C.0-7 pcie_rp_9_12.asl => To hold RP09-RP12 entries refer as 0:0x1D.0-3 pcie_rp_13_16.asl => To hold RP13-RP16 entries refer as 0:0x1D.4-7 For PCH-H pcie_rp_17_24.asl => To hold RP17-RP24 entries refer as 0:0x1B.0-7 Also create pcie_port.asl for common RP number using PCI configuration space and calling _PRT method from common pci_rp_xx_xx.asl file. TEST=Able to build and boot CML and TGL platform. 1) Dump and disassemble DSDT, verify RP01-RP12 device present inside common pcie asl is still there for TGL and RP01-RP16 for CML. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Iaff9decb63ed88eb64c9e61a57d6adf69a46d3d4 --- M src/soc/intel/cannonlake/acpi/pcie.asl R src/soc/intel/common/block/acpi/acpi/pcie_port.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl M src/soc/intel/denverton_ns/acpi/pcie.asl M src/soc/intel/elkhartlake/acpi/pcie.asl M src/soc/intel/icelake/acpi/pcie.asl M src/soc/intel/jasperlake/acpi/pcie.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/pcie.asl 12 files changed, 217 insertions(+), 1,607 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46004/1 diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 302863b..8d3a7cc 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -111,413 +111,14 @@ } } } - -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> +/* RP13-RP16 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl> #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) -Device (RP17) -{ - Name (_ADR, 0x001B0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP18) -{ - Name (_ADR, 0x001B0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP19) -{ - Name (_ADR, 0x001B0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP20) -{ - Name (_ADR, 0x001B0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP21) -{ - Name (_ADR, 0x001B0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP22) -{ - Name (_ADR, 0x001B0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP23) -{ - Name (_ADR, 0x001B0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP24) -{ - Name (_ADR, 0x001B0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP17-RP24 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl> #endif diff --git a/src/soc/intel/denverton_ns/acpi/pcie_port.asl b/src/soc/intel/common/block/acpi/acpi/pcie_port.asl similarity index 85% rename from src/soc/intel/denverton_ns/acpi/pcie_port.asl rename to src/soc/intel/common/block/acpi/acpi/pcie_port.asl index d48ecd0..9046eff 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie_port.asl +++ b/src/soc/intel/common/block/acpi/acpi/pcie_port.asl @@ -9,3 +9,8 @@ , 24, RPPN, 8, // Root Port Number } + +Method (_PRT) +{ + Return (IRQM (RPPN)) +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl new file mode 100644 index 0000000..25be54d --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + #include "pcie_port.asl" +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + #include "pcie_port.asl" +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + #include "pcie_port.asl" +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl new file mode 100644 index 0000000..32ef7d1 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + #include "pcie_port.asl" +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + #include "pcie_port.asl" +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + #include "pcie_port.asl" +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + #include "pcie_port.asl" +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + #include "pcie_port.asl" +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + #include "pcie_port.asl" +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + #include "pcie_port.asl" +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl new file mode 100644 index 0000000..f0027f1 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + #include "pcie_port.asl" +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + #include "pcie_port.asl" +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + #include "pcie_port.asl" +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + #include "pcie_port.asl" +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + #include "pcie_port.asl" +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + #include "pcie_port.asl" +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + #include "pcie_port.asl" +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl new file mode 100644 index 0000000..e44e65b --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + #include "pcie_port.asl" +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + #include "pcie_port.asl" +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + #include "pcie_port.asl" +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index a34884e..026ecd9 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -252,94 +252,54 @@ { Name (_ADR, 0x00090000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP02) { Name (_ADR, 0x000A0000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP03) { Name (_ADR, 0x000B0000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP04) { Name (_ADR, 0x000C0000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP05) { Name (_ADR, 0x000E0000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP06) { Name (_ADR, 0x000F0000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP07) { Name (_ADR, 0x00100000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } Device (RP08) { Name (_ADR, 0x00110000) - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl index a19feb7..586a041 100644 --- a/src/soc/intel/elkhartlake/acpi/pcie.asl +++ b/src/soc/intel/elkhartlake/acpi/pcie.asl @@ -96,206 +96,7 @@ } } -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> diff --git a/src/soc/intel/icelake/acpi/pcie.asl b/src/soc/intel/icelake/acpi/pcie.asl index 9c0933f..b646c42 100644 --- a/src/soc/intel/icelake/acpi/pcie.asl +++ b/src/soc/intel/icelake/acpi/pcie.asl @@ -96,274 +96,9 @@ } } -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> +/* RP13-RP16 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl> diff --git a/src/soc/intel/jasperlake/acpi/pcie.asl b/src/soc/intel/jasperlake/acpi/pcie.asl index a19feb7..586a041 100644 --- a/src/soc/intel/jasperlake/acpi/pcie.asl +++ b/src/soc/intel/jasperlake/acpi/pcie.asl @@ -96,206 +96,7 @@ } } -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 6f4aa82f..286f006 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -96,274 +96,9 @@ } } -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> +/* RP13-RP16 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl> diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index a19feb7..9f32b6b 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -95,207 +95,7 @@ } } } - -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/46004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaff9decb63ed88eb64c9e61a57d6adf69a46d3d4 Gerrit-Change-Number: 46004 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: intel/common: Add new mmc apis
by Angel Pons (Code Review) 04 Oct '20

04 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44492 ) Change subject: intel/common: Add new mmc apis ...................................................................... Patch Set 2: (7 comments) Some minor nits on the commit message https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@7 PS2, Line 7: apis nit: APIs https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@7 PS2, Line 7: intel/common nit: soc/intel/common https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@9 PS2, Line 9: apis nit: APIs https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@9 PS2, Line 9: dll nit: DLL https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@9 PS2, Line 9: emmc nit: eMMC https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@13 PS2, Line 13: emmc nit: eMMC https://review.coreboot.org/c/coreboot/+/44492/2//COMMIT_MSG@13 PS2, Line 13: dll nit: DLL -- To view, visit https://review.coreboot.org/c/coreboot/+/44492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Gerrit-Change-Number: 44492 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Oct 2020 15:37:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intel/common: Add new mmc apis
by Angel Pons (Code Review) 04 Oct '20

04 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44492 ) Change subject: intel/common: Add new mmc apis ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/44492/2/src/soc/intel/common/block… File src/soc/intel/common/block/scs/mmc.c: https://review.coreboot.org/c/coreboot/+/44492/2/src/soc/intel/common/block… PS2, Line 27: EMMC_TX_CMD_CNTL_OFFSET); nit: these lines should fit in 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/44492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70f14d95f81d30360f5a68fbb34b50425e98ece Gerrit-Change-Number: 44492 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Oct 2020 15:35:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sdhci: Add new error return code
by Angel Pons (Code Review) 04 Oct '20

04 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44491 ) Change subject: sdhci: Add new error return code ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76d565b1f3d5843fb9d7c66efcb1319f305ac1c6 Gerrit-Change-Number: 44491 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Oct 2020 15:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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