coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/common/block/acpi: Factor out common pch_glan.asl
by Subrata Banik (Code Review) 05 Oct '20

05 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45975 ) Change subject: soc/intel/common/block/acpi: Factor out common pch_glan.asl ...................................................................... soc/intel/common/block/acpi: Factor out common pch_glan.asl This patch moves pch_glan.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify GLAN device present inside common pch_glan.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef --- M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/pch_glan.asl D src/soc/intel/elkhartlake/acpi/pch_glan.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl D src/soc/intel/icelake/acpi/pch_glan.asl M src/soc/intel/icelake/acpi/southbridge.asl D src/soc/intel/jasperlake/acpi/pch_glan.asl M src/soc/intel/jasperlake/acpi/southbridge.asl D src/soc/intel/tigerlake/acpi/pch_glan.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 10 files changed, 12 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45975/1 diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index a6b0237..0c54877 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -44,7 +44,7 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* GBe 0:1f.6 */ -#include "pch_glan.asl" +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> /* PMC Core */ #include <soc/intel/common/block/acpi/acpi/pmc.asl> diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/common/block/acpi/acpi/pch_glan.asl similarity index 90% rename from src/soc/intel/cannonlake/acpi/pch_glan.asl rename to src/soc/intel/common/block/acpi/acpi/pch_glan.asl index 97faf7a..6bf733d 100644 --- a/src/soc/intel/cannonlake/acpi/pch_glan.asl +++ b/src/soc/intel/common/block/acpi/acpi/pch_glan.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Intel Gigabit Ethernet Controller 0:1f.6 */ +#include <soc/gpe.h> Device (GLAN) { diff --git a/src/soc/intel/elkhartlake/acpi/pch_glan.asl b/src/soc/intel/elkhartlake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7a..0000000 --- a/src/soc/intel/elkhartlake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index fd87469..f84539b 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -43,3 +43,6 @@ /* EMMC/SD card */ #include "scs.asl" + +/* GBe 0:1f.6 */ +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/icelake/acpi/pch_glan.asl b/src/soc/intel/icelake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7a..0000000 --- a/src/soc/intel/icelake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 474c6cc..56e19bb 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -39,4 +39,4 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* GBe 0:1f.6 */ -#include "pch_glan.asl" +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/jasperlake/acpi/pch_glan.asl b/src/soc/intel/jasperlake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7a..0000000 --- a/src/soc/intel/jasperlake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 48411e4..c19791b 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -49,3 +49,6 @@ /* EMMC/SD card */ #include "scs.asl" + +/* GBe 0:1f.6 */ +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7a..0000000 --- a/src/soc/intel/tigerlake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index ff683cf..23fdb17 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -43,3 +43,6 @@ /* PMC Core*/ #include <soc/intel/common/block/acpi/acpi/pmc.asl> + +/* GBe 0:1f.6 */ +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef Gerrit-Change-Number: 45975 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 05 Oct '20

05 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/42745/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/5//COMMIT_MSG@11 PS5, Line 11: > I think that the default can be changed. […] The Kconfig defaults preserve the old behaviour and I've noted this in the commit message. Besides, see CB:41763. The logic was to align Jasperlake with the other platforms, not to disable the feature. However, other platforms have it enabled. https://review.coreboot.org/c/coreboot/+/42745/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42745/7//COMMIT_MSG@10 PS7, Line 10: protection > That would be covered as part of the quoted definition. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 04 Oct 2020 23:04:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 05 Oct '20

05 Oct '20

Hello build bot (Jenkins), Justin TerAvest, Angel Pons, Subrata Banik, Ronak Kanabar, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42745 to look at the new patch set (#9). Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... soc/intel: Configure PAVP at compile-time Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Note that Jasperlake can now enable PAVP, whereas previously it was disabled. Also add a period at the end of Kconfig help for MMA while editing the file. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/Kconfig.common M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c 6 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42745/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 05 Oct '20

05 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: > Patch Set 25: Code-Review+1 > > > Patch Set 25: > > > > > Patch Set 25: > > > > > > > Patch Set 25: Code-Review+1 > > > > > > > > LGTM. Are there any interdependencies with any of the other PCIe PM-related settings? > > > > > > Perhaps that "PcieRpAspm" doesn't disable L1 for a given root port? > > > > should coreboot automatically disable L1SS on a given port if PcieRpAspm is disabled for that port? Or are we just depending on the board config to be sane? > > pciexp_config_L1_sub_state() checks for the capabilities. If we tell FSP > that it's not capable, the root port's capability regs should reflect > that (I never tested it, though). > > One dependency for L1 substates is clock PM (i.e. a usable clockreq > signal). There is no capability for that. It's currently only > configurable globally via Kconfig (cf. CB:41696). Do you think that L1 substates should be guarded by that Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Oct 2020 22:49:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superio/acpi: Convert *.asl to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Oct '20

04 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46003 ) Change subject: superio/acpi: Convert *.asl to ASL 2.0 syntax ...................................................................... superio/acpi: Convert *.asl to ASL 2.0 syntax Change-Id: I359bf81f14a35737688804f8ac1f0370307fa77b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/acpi/pnp.asl M src/superio/acpi/pnp_config.asl M src/superio/acpi/pnp_generic.asl M src/superio/acpi/pnp_kbc.asl M src/superio/acpi/pnp_uart.asl 5 files changed, 35 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46003/1 diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl index d5a26a7..aa21692 100644 --- a/src/superio/acpi/pnp.asl +++ b/src/superio/acpi/pnp.asl @@ -44,18 +44,18 @@ #define PNP_GENERIC_STA(LDN) \ ENTER_CONFIG_MODE (LDN)\ If (PNP_DEVICE_ACTIVE) {\ - Store (DEVICE_PRESENT_ACTIVE, Local0)\ + Local0 = DEVICE_PRESENT_ACTIVE\ }\ Else\ {\ - Store (DEVICE_PRESENT_INACTIVE, Local0)\ + Local0 = DEVICE_PRESENT_INACTIVE\ }\ EXIT_CONFIG_MODE ()\ Return (Local0)\ #define PNP_GENERIC_DIS(LDN) \ ENTER_CONFIG_MODE (LDN)\ - Store (Zero, PNP_DEVICE_ACTIVE)\ + PNP_DEVICE_ACTIVE = 0\ EXIT_CONFIG_MODE ()\ @@ -63,7 +63,7 @@ * Current power state (returns the chip's state) */ #define PNP_DEFAULT_PSC \ - Store(^^_PSC (), Local0)\ + Local0 = ^^_PSC ()\ Return (Local0) /* @@ -76,24 +76,24 @@ * bit */ #define PNP_GENERIC_PSC(PM_REG, PM_VAL, PM_LDN) \ - Store(^^_PSC (), Local0)\ + Local0 = ^^_PSC ()\ If (Local0) { Return (Local0) }\ ENTER_CONFIG_MODE (PM_LDN)\ - Store (PM_REG, Local0)\ + Local0 = PM_REG\ EXIT_CONFIG_MODE ()\ - If (LEqual(Local0, PM_VAL)) { Return (3) }\ + If (Local0 == PM_VAL) { Return (3) }\ Else { Return (0) }\ /* Disable power saving mode */ #define PNP_GENERIC_PS0(PM_REG, PM_VAL, PM_LDN) \ ENTER_CONFIG_MODE (PM_LDN)\ - Store (Not(PM_VAL), PM_REG)\ + PM_REG = ~PM_VAL\ EXIT_CONFIG_MODE () /* Enable power saving mode */ #define PNP_GENERIC_PS3(PM_REG, PM_VAL, PM_LDN) \ ENTER_CONFIG_MODE (PM_LDN)\ - Store (PM_VAL, PM_REG)\ + PM_REG = PM_VAL\ EXIT_CONFIG_MODE () @@ -102,29 +102,29 @@ #define PNP_READ_IO(IO_FROM, RESOURCE_TEMPLATE, IO_TAG) \ CreateWordField (RESOURCE_TEMPLATE, IO_TAG._MIN, IO_TAG##I)\ CreateWordField (RESOURCE_TEMPLATE, IO_TAG._MAX, IO_TAG##A)\ - Or (ShiftLeft (IO_FROM##_HIGH_BYTE, 8), IO_FROM##_LOW_BYTE, Local0)\ - Store (Local0, IO_TAG##I)\ - Store (Local0, IO_TAG##A) + Local0 = (IO_FROM##_HIGH_BYTE << 8) | IO_FROM##_LOW_BYTE\ + IO_TAG##I = Local0\ + IO_TAG##A = Local0 #define PNP_READ_IRQ(IRQ_FROM, RESOURCE_TEMPLATE, IRQ_TAG) \ CreateWordField (RESOURCE_TEMPLATE, IRQ_TAG._INT, IRQ_TAG##W)\ - ShiftLeft (One, IRQ_FROM, IRQ_TAG##W) + IRQ_TAG##W = 1 << IRQ_FROM #define PNP_READ_DMA(DMA_FROM, RESOURCE_TEMPLATE, DMA_TAG) \ CreateByteField (RESOURCE_TEMPLATE, DMA_TAG._DMA, DMA_TAG##W)\ - ShiftLeft (One, DMA_FROM, DMA_TAG##W) + DMA_TAG##W = 1 << DMA_FROM #define PNP_WRITE_IO(IO_TO, RESOURCE, IO_TAG) \ CreateWordField (RESOURCE, IO_TAG._MIN, IO_TAG##I)\ - Store (And(IO_TAG##I, 0xff), IO_TO##_LOW_BYTE)\ - Store (ShiftRight(IO_TAG##I, 8), IO_TO##_HIGH_BYTE) + IO_TO##_LOW_BYTE = IO_TAG##I & 0xff\ + IO_TO##_HIGH_BYTE = IO_TAG##I << 8 #define PNP_WRITE_IRQ(IRQ_TO, RESOURCE, IRQ_TAG) \ CreateWordField (RESOURCE, IRQ_TAG._INT, IRQ_TAG##W)\ - Subtract (FindSetLeftBit (IRQ_TAG##W), 1, IRQ_TO) + IRQ_TO = FindSetLeftBit (IRQ_TAG##W) - 1 #define PNP_WRITE_DMA(DMA_TO, RESOURCE, DMA_TAG) \ CreateByteField (RESOURCE, DMA_TAG._DMA, DMA_TAG##W)\ - Subtract (FindSetLeftBit (DMA_TAG##W), 1, DMA_TO) + DMA_TO = FindSetLeftBit (DMA_TAG##W) - 1 #endif diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl index ff74153..5e7a076 100644 --- a/src/superio/acpi/pnp_config.asl +++ b/src/superio/acpi/pnp_config.asl @@ -35,19 +35,19 @@ { Acquire (CONF_MODE_MUTEX, 0xFFFF) #ifdef PNP_ENTER_MAGIC_1ST - Store (PNP_ENTER_MAGIC_1ST, PNP_ADDR_REG) + PNP_ADDR_REG = PNP_ENTER_MAGIC_1ST #ifdef PNP_ENTER_MAGIC_2ND - Store (PNP_ENTER_MAGIC_2ND, PNP_ADDR_REG) + PNP_ADDR_REG = PNP_ENTER_MAGIC_2ND #ifdef PNP_ENTER_MAGIC_3RD - Store (PNP_ENTER_MAGIC_3RD, PNP_ADDR_REG) + PNP_ADDR_REG = PNP_ENTER_MAGIC_3RD #ifdef PNP_ENTER_MAGIC_4TH - Store (PNP_ENTER_MAGIC_4TH, PNP_ADDR_REG) + PNP_ADDR_REG = PNP_ENTER_MAGIC_4TH #endif #endif #endif #endif - If (LLess(Arg0, PNP_NO_LDN_CHANGE)) { - Store(Arg0, PNP_LOGICAL_DEVICE) + If (Arg0 < PNP_NO_LDN_CHANGE) { + PNP_LOGICAL_DEVICE = Arg0 } } @@ -58,10 +58,10 @@ Method (EXIT_CONFIG_MODE) { #ifdef PNP_EXIT_MAGIC_1ST - Store (PNP_EXIT_MAGIC_1ST, PNP_ADDR_REG) + PNP_ADDR_REG = PNP_EXIT_MAGIC_1ST #endif #if defined(PNP_EXIT_SPECIAL_REG) && defined(PNP_EXIT_SPECIAL_VAL) - Store (PNP_EXIT_SPECIAL_VAL, PNP_EXIT_SPECIAL_REG) + PNP_EXIT_SPECIAL_REG = PNP_EXIT_SPECIAL_VAL #endif Release (CONF_MODE_MUTEX) } @@ -72,5 +72,5 @@ */ Method (SWITCH_LDN, 1) { - Store(Arg0, PNP_LOGICAL_DEVICE) + PNP_LOGICAL_DEVICE = Arg0 } diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index d0d9a2d..ac60e8a 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -168,7 +168,7 @@ #ifdef SUPERIO_PNP_DMA PNP_WRITE_DMA(PNP_DMA0, Arg0, DM0) #endif - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () } } diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index 22a0556..b0055be 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -46,7 +46,7 @@ Method (_DIS) { ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) - Store (Zero, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 0 EXIT_CONFIG_MODE () #if defined(SUPERIO_KBC_PS2LDN) Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) @@ -95,7 +95,7 @@ PNP_WRITE_IO(PNP_IO0, Arg0, IO0) PNP_WRITE_IO(PNP_IO1, Arg0, IO1) PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () #if defined(SUPERIO_KBC_PS2LDN) Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) @@ -155,8 +155,8 @@ Method (_STA) { - Store (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA (), Local0) - If (LEqual (Local0, DEVICE_PRESENT_ACTIVE)) { + Local0 = ^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA () + If (Local0 == DEVICE_PRESENT_ACTIVE) { PNP_GENERIC_STA(SUPERIO_KBC_PS2LDN) } Else { Return (Local0) @@ -166,7 +166,7 @@ Method (_DIS) { ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) - Store (Zero, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 0 EXIT_CONFIG_MODE () } @@ -200,7 +200,7 @@ }) ENTER_CONFIG_MODE (SUPERIO_KBC_PS2LDN) PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR1) - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () } } diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index f780063..b5b22f7 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -112,7 +112,7 @@ ENTER_CONFIG_MODE (SUPERIO_UART_LDN) PNP_WRITE_IO(PNP_IO0, Arg0, IO0) PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I359bf81f14a35737688804f8ac1f0370307fa77b Gerrit-Change-Number: 46003 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: src/soc/intel/common/block: add Kconfig for PM Timer emulation support
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Nico Huber, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46017 to look at the new patch set (#4). Change subject: src/soc/intel/common/block: add Kconfig for PM Timer emulation support ...................................................................... src/soc/intel/common/block: add Kconfig for PM Timer emulation support Add a Kconfig for SoCs to indicate PM ACPI timer emulation support. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 7 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46017/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Gerrit-Change-Number: 46017 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… PS10, Line 393: BIOS_WARNING > BIOS_NOTICE for unexpected things that don't affect booting. obsolete now -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 04 Oct 2020 17:21:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… PS10, Line 389: freq > Below `frequency` means the timer. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 04 Oct 2020 17:17:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45951 to look at the new patch set (#11). Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation The code for enabling ACPI timer emulation is the same for the socs above. Deduplicate it by moving it to common code. Note: The ACPI timer emulation can only be used by SoCs with ucode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/pm_timer_emulation.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 9 files changed, 41 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/45951/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Nico Huber (Code Review) 04 Oct '20

04 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/45951/10/src/soc/intel/common/bloc… PS10, Line 393: BIOS_WARNING BIOS_NOTICE for unexpected things that don't affect booting. -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 04 Oct 2020 16:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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