coreboot-gerrit September 2019

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Change in ...coreboot[master]: src/mainboard: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 26 Sep '19

26 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33684 Change subject: src/mainboard: Use 'include <stdlib.h>' when appropriate ...................................................................... src/mainboard: Use 'include <stdlib.h>' when appropriate Change-Id: I8a63f98c61eb7773ce94b4efc446b8d0149db5a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/gardenia/gpio.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/esd/atom15/gpio.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/urara/boardid.c M src/mainboard/intel/bayleybay_fsp/gpio.c M src/mainboard/intel/kunimitsu/mainboard.c M src/mainboard/intel/minnowmax/gpio.c M src/mainboard/intel/strago/gpio.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c M src/mainboard/roda/rk886ex/m3885.c M src/mainboard/scaleway/tagada/bmcinfo.c M src/mainboard/siemens/mc_tcu3/gpio.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c M src/mainboard/ti/beaglebone/leds.c 20 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33684/1 diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 7c5f47b..2013fa5 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -14,8 +14,8 @@ */ #include <soc/southbridge.h> -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> #include "gpio.h" diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 3acb11e..66c49ad 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/acpi.h> #include <commonlib/endian.h> +#include <stdlib.h> #include "fw_cfg.h" #include "fw_cfg_if.h" diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c index b9c7829..248e6d8 100644 --- a/src/mainboard/esd/atom15/gpio.c +++ b/src/mainboard/esd/atom15/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 9db26c7..9916df4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -16,7 +16,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/southbridge.h> -#include <stdlib.h> +#include <stddef.h> #include <boardid.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..feb8c02 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 37c7853..6d180fd 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 731b357..4049b2d 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 9a6b64e..14298d4 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -14,9 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> +#include <stddef.h> #include <string.h> - #include <boardid.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/mainboard/intel/bayleybay_fsp/gpio.c b/src/mainboard/intel/bayleybay_fsp/gpio.c index 27b22c5..0ac1f9b 100644 --- a/src/mainboard/intel/bayleybay_fsp/gpio.c +++ b/src/mainboard/intel/bayleybay_fsp/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4c93051..801dbc8 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -19,9 +19,9 @@ #include <console/console.h> #include <device/device.h> #include <gpio.h> -#include <stdlib.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> + #include "ec.h" #include "gpio.h" diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index b0f78c8..08b89d1 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index ed9ae4b..0fe55d2 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -16,8 +16,8 @@ #include "irqroute.h" #include <soc/gpio.h> -#include <stdlib.h> #include <boardid.h> + #include "onboard.h" #include "gpio.h" diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c index 757d8da..9924ec0 100644 --- a/src/mainboard/lippert/frontrunner-af/sema.c +++ b/src/mainboard/lippert/frontrunner-af/sema.c @@ -11,16 +11,15 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <delay.h> #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ - #include <Porting.h> #include <AGESA.h> #include <northbridge/amd/agesa/dimmSpd.h> + #include "sema.h" /* Write data block to slave on SMBUS0. */ diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c index 78d1ad6..32edaf5 100644 --- a/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/rotundu/gpio.c @@ -15,8 +15,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "../../irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c index c9d5426..e280e7c 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c @@ -15,8 +15,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "../../irqroute.h" #define GPIO_FUNC3_PULL_UP_20K GPIO_FUNC(3, PULL_UP, 20K) diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 60a4f48..4b97dfc 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -15,12 +15,11 @@ */ #include <types.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <delay.h> - #include <ec/acpi/ec.h> + #include "m3885.h" #define TH0LOW 80 diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 237d551..3530ff4 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -14,8 +14,8 @@ * */ +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <arch/early_variables.h> #include <console/console.h> #include <console/uart.h> diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index 23c6f96..d6d7106 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/gpio.h> +#include <stddef.h> + #include "irqroute.h" /* NCORE GPIOs */ diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 8ac6ff1..3d43181 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include <string.h> #include <console/console.h> #include <soc/otp.h> diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index a4889b9..97b544a 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -13,8 +13,8 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <cpu/ti/am335x/gpio.h> -#include <stdlib.h> #include "leds.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a63f98c61eb7773ce94b4efc446b8d0149db5a9 Gerrit-Change-Number: 33684 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK
by Kyösti Mälkki (Code Review) 26 Sep '19

26 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35599 ) Change subject: arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK ...................................................................... arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/mips/include/arch/header.ld M src/arch/ppc64/include/arch/header.ld 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35599/1 diff --git a/src/arch/mips/include/arch/header.ld b/src/arch/mips/include/arch/header.ld index 6650132..7f832eb 100644 --- a/src/arch/mips/include/arch/header.ld +++ b/src/arch/mips/include/arch/header.ld @@ -19,7 +19,7 @@ to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK ENTRY(_start) #else ENTRY(stage_entry) diff --git a/src/arch/ppc64/include/arch/header.ld b/src/arch/ppc64/include/arch/header.ld index 349fd51..badeefd 100644 --- a/src/arch/ppc64/include/arch/header.ld +++ b/src/arch/ppc64/include/arch/header.ld @@ -19,7 +19,7 @@ to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK ENTRY(_start) #else ENTRY(stage_entry) -- To view, visit https://review.coreboot.org/c/coreboot/+/35599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Gerrit-Change-Number: 35599 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superiotool: add basic support for SCH5545
by Alexander Couzens (Code Review) 26 Sep '19

26 Sep '19

Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20237 ) Change subject: superiotool: add basic support for SCH5545 ...................................................................... Patch Set 4: I think we can merge it anyways, because it's only the superiotool part. -- To view, visit https://review.coreboot.org/c/coreboot/+/20237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Gerrit-Change-Number: 20237 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 26 Sep 2019 16:42:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superiotool: add basic support for SCH5545
by Alexander Couzens (Code Review) 26 Sep '19

26 Sep '19

Hello Christoph Pomaska, Felix Held, Paul Menzel, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/20237 to look at the new patch set (#4). Change subject: superiotool: add basic support for SCH5545 ...................................................................... superiotool: add basic support for SCH5545 Based on the SCH5627 datasheet which is similiar SCH5545 id 0xc4, SCH5627 id 0xc6. Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M util/superiotool/smsc.c 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/20237/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/20237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Gerrit-Change-Number: 20237 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb,sb: Use get_acpi_table_revision()
by HAOUAS Elyes (Code Review) 26 Sep '19

26 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33437 Change subject: mb,sb: Use get_acpi_table_revision() ...................................................................... mb,sb: Use get_acpi_table_revision() Change-Id: Icce0e8c01732ec0d5797554c0c35606686c2b0e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/torpedo/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/nvidia/mcp55/fadt.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33437/1 diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 3400fcb..9d11378 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -50,7 +50,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 7669761..afe72c0 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -39,7 +39,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 6aaa702..d72ad63 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -39,7 +39,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/33437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icce0e8c01732ec0d5797554c0c35606686c2b0e7 Gerrit-Change-Number: 33437 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: superiotool: add basic support for SCH5545
by Alexander Couzens (Code Review) 26 Sep '19

26 Sep '19

Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20237 ) Change subject: superiotool: add basic support for SCH5545 ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/20237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Gerrit-Change-Number: 20237 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 26 Sep 2019 16:39:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device: Introduce pcidev_on_root() and friends
by Aaron Durbin (Code Review) 26 Sep '19

26 Sep '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26447 ) Change subject: device: Introduce pcidev_on_root() and friends ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/c/coreboot/+/26447/25/src/device/device_const.c File src/device/device_const.c: https://review.coreboot.org/c/coreboot/+/26447/25/src/device/device_const.c… PS25, Line 43: result = 0; Why didn't we put a comment here indicating why this function sometimes doesn't work? I assume it's because ->secondary isn't initialized until after enumeration. Correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/26447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie20598d48b4cf6e35e45fc90804bad4728437fc6 Gerrit-Change-Number: 26447 Gerrit-PatchSet: 25 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 26 Sep 2019 15:04:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by mturney mturney (Code Review) 26 Sep '19

26 Sep '19

mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 4: > Patch Set 4: > > Where do I get the firmware blobs from? Needs to be documented. Working through this with legal reviews, etc. Please feel free to discuss with Julius Werner. -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 4 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Sep 2019 14:48:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot/Makefile: display error when spaces in path of toplevel make...
by Name of user not set (Code Review) 26 Sep '19

26 Sep '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35434 ) Change subject: coreboot/Makefile: display error when spaces in path of toplevel makefile ...................................................................... coreboot/Makefile: display error when spaces in path of toplevel makefile coreboot toplevel makefile breaks when path to the coreboot directory contains spaces. This patch displays a reasonable message to the user whenever spaces are found within the path to the coreboot direcrory. Change-Id: Id11deffa01ddca1ff9332d67c7aa33a382b4cdc7 Signed-off-by: Sourabh Kashyap <sourabhka(a)hcl.com> --- M Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35434/1 diff --git a/Makefile b/Makefile index f0a22a5..7911801 100644 --- a/Makefile +++ b/Makefile @@ -30,6 +30,9 @@ ## SUCH DAMAGE. ## +ifneq ($(words $(CURDIR)),1) + $(error Error: Path to the main directory cannot contain spaces) +endif top := $(CURDIR) src := src srck := $(top)/util/kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/35434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11deffa01ddca1ff9332d67c7aa33a382b4cdc7 Gerrit-Change-Number: 35434 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 26 Sep '19

26 Sep '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 19: (4 comments) https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 10: 3 > Then, maybe its better to just have this as a macro if you are not expecting it to change? For chrome systems, CSE region will have 3 paritions only if CSE supports FW update. Otherwise , CSE will have only 2 partitions. The valid boot partition are BP1, and BP2 in chrome systems. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 781: partition_id != BP1 && partition_id != BP2 > Those details should be captured in comments. […] Sure, I will capture the details in the comments.I will check on spec, and get back to you on it. https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/12/src/soc/intel/common/bloc… PS12, Line 153: enum > Can those instances use something like BP(1) and BP(2)? For chrome system,CSE region will have max 3 partitions. So, no change to existing enum definations. Thanks https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block… PS6, Line 147: MAX_ME_PARTITIONS > Yes, that would be ideal. I will move definition of CSE_MAX_BOOT_PARTITIONS to header file. -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 19 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Sep 2019 12:05:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2019