coreboot-gerrit September 2019

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Change in coreboot[master]: Kconfig: Make it more clear what CONFIG_CBFS_SIZE is for
by Arthur Heymans (Code Review) 28 Sep '19

28 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35597 ) Change subject: Kconfig: Make it more clear what CONFIG_CBFS_SIZE is for ...................................................................... Kconfig: Make it more clear what CONFIG_CBFS_SIZE is for CONFIG_CBFS_SIZE should only be used as a parameter to generate the default FMAP. Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35597/1 diff --git a/src/Kconfig b/src/Kconfig index a1c016e..e9287d3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -356,7 +356,8 @@ to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE - binaries. + binaries. This symbol should only used to generate a default FMAP and + is unused when a separate fmd file is specified. config FMDFILE string "fmap description file in fmd format" -- To view, visit https://review.coreboot.org/c/coreboot/+/35597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e Gerrit-Change-Number: 35597 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x131e: enable mSATA slot
by James (Code Review) 28 Sep '19

28 Sep '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31364 Change subject: mb/lenovo/x131e: enable mSATA slot ...................................................................... mb/lenovo/x131e: enable mSATA slot Per google/stout. Functionality untested. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 --- M src/mainboard/lenovo/x131e/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31364/1 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 628c4eb..d20abdf 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -49,8 +49,8 @@ register "gpi6_routing" = "2" register "gpi13_routing" = "2" - # Enable SATA ports - register "sata_port_map" = "0x1" + # Enable SATA ports 0 (2.5 inch) and 1 (mSATA) + register "sata_port_map" = "0x3" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" -- To view, visit https://review.coreboot.org/c/coreboot/+/31364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Gerrit-Change-Number: 31364 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "lib/fmap: Cache FMAP in cbmem"
by Subrata Banik (Code Review) 28 Sep '19

28 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35637 ) Change subject: Revert "lib/fmap: Cache FMAP in cbmem" ...................................................................... Revert "lib/fmap: Cache FMAP in cbmem" This reverts commit 6d787c2590920fc5ea222d692004818bbed6b3e5. Change-Id: I2ac50f6c0d650ed4d92163288a3aa69e1714bf88 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M src/lib/fmap.c 4 files changed, 2 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/35637/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88a..8d0ca46 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -76,7 +76,6 @@ #define CBMEM_ID_ROM1 0x524f4d31 #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 -#define CBMEM_ID_FMAP 0x464d4150 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -135,6 +134,5 @@ { CBMEM_ID_ROM0, "VGA ROM #0 "}, \ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ - { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ - { CBMEM_ID_FMAP, "FMAP "}, + { CBMEM_ID_ROM3, "VGA ROM #3 "}, #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6816670..7bded2a 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -89,7 +89,6 @@ LB_TAG_VBOOT_WORKBUF = 0x0034, LB_TAG_MMC_INFO = 0x0035, LB_TAG_TCPA_LOG = 0x0036, - LB_TAG_FMAP = 0x0037, LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9c5942f..66afcf3 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -345,8 +345,7 @@ {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, {CBMEM_ID_VPD, LB_TAG_VPD}, {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, - {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG}, - {CBMEM_ID_FMAP, LB_TAG_FMAP}, + {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG} }; int i; diff --git a/src/lib/fmap.c b/src/lib/fmap.c index f007418..2b4e3ba 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -20,7 +20,6 @@ #include <commonlib/fmap_serialized.h> #include <stddef.h> #include <string.h> -#include <cbmem.h> #include "fmap_config.h" @@ -29,7 +28,6 @@ */ static int fmap_print_once CAR_GLOBAL; -static struct mem_region_device fmap_cache CAR_GLOBAL; int find_fmap_directory(struct region_device *fmrd) { @@ -38,16 +36,6 @@ size_t fmap_size; size_t offset = FMAP_OFFSET; - if (cbmem_possibly_online() && !ENV_SMM) { - /* Try FMAP cache first */ - const struct mem_region_device *cache; - - cache = car_get_var_ptr(&fmap_cache); - if (region_device_sz(&cache->rdev)) - return rdev_chain(fmrd, &cache->rdev, 0, - region_device_sz(&cache->rdev)); - } - boot_device_init(); boot = boot_device_ro(); @@ -207,53 +195,3 @@ return -1; return rdev_writeat(&rdev, buffer, 0, size); } - -static void fmap_register_cache(int unused) -{ - const struct cbmem_entry *e; - struct mem_region_device *mdev; - - mdev = car_get_var_ptr(&fmap_cache); - - /* Find the FMAP cache installed by previous stage */ - e = cbmem_entry_find(CBMEM_ID_FMAP); - /* Don't set fmap_cache so that find_fmap_directory will use regular path */ - if (!e) - return; - - mem_region_device_ro_init(mdev, cbmem_entry_start(e), cbmem_entry_size(e)); -} - -/* - * The main reason to copy the FMAP into CBMEM is to make it available to the - * OS on every architecture. As side effect use the CBMEM copy as cache. - */ -static void fmap_setup_cache(int unused) -{ - struct region_device fmrd; - - if (find_fmap_directory(&fmrd)) - return; - - /* Reloads the FMAP even on ACPI S3 resume */ - const size_t s = region_device_sz(&fmrd); - struct fmap *fmap = cbmem_add(CBMEM_ID_FMAP, s); - if (!fmap) { - printk(BIOS_ERR, "ERROR: Failed to allocate CBMEM\n"); - return; - } - - const ssize_t ret = rdev_readat(&fmrd, fmap, 0, s); - if (ret != s) { - printk(BIOS_ERR, "ERROR: Failed to read FMAP into CBMEM\n"); - cbmem_entry_remove(cbmem_entry_find(CBMEM_ID_FMAP)); - return; - } - - /* Finally advertise the cache for the current stage */ - fmap_register_cache(unused); -} - -ROMSTAGE_CBMEM_INIT_HOOK(fmap_setup_cache) -RAMSTAGE_CBMEM_INIT_HOOK(fmap_register_cache) -POSTCAR_CBMEM_INIT_HOOK(fmap_register_cache) -- To view, visit https://review.coreboot.org/c/coreboot/+/35637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac50f6c0d650ed4d92163288a3aa69e1714bf88 Gerrit-Change-Number: 35637 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Nico Huber (Code Review) 28 Sep '19

28 Sep '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 8: > @Nico what's missing to merge it? *sigh* honestly I don't care anymore. It would be nice to mention what mod board was tested, though. I digged around a little, and all I could find is that the Nitrocaster mod makes the ThinkPad even more proprietary. It's undocumented and seems to include unnecessary active components that maybe are just there to avoid firmware changes. If nobody gets Nitrocaster to docu- ment it, I have zero interest to properly support it. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Sat, 28 Sep 2019 01:09:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Alexander Couzens (Code Review) 28 Sep '19

28 Sep '19

Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 8: @Nico what's missing to merge it? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Sat, 28 Sep 2019 00:35:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Alexander Couzens (Code Review) 28 Sep '19

28 Sep '19

Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 8: > Patch Set 7: > > > Patch Set 7: > > > > patchset 6 works for me on my x230 with a full hd display. even using qubes/xen :) > > just to make sure: with the current patchset you get graphics output before the kernel starts, right? if so, i'll merge this :) yes i do. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Sat, 28 Sep 2019 00:35:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Kyösti Mälkki (Code Review) 27 Sep '19

27 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > > Patch Set 5: > > > > > > > Patch Set 5: > > > > > > > > This is very much incomplete. > > > > > > > > But idea is, that as PCI bus gets enumerated, each secondary side PCI device path.pci.devfn is updated with the bus number. Changing path.pci structure may be painful, so much of that is open-coded. > > > > > > $ git grep 'pci[.]devfn' > > > > > > Oh man. That's quiet a bit of slop in there to clean up. I could give it a pass if you want. We likely need it so that there's only a few touch points to adjust when we need to make changes. Let me know what you guys think. > > > > Luckily, I don't see this so urgent. I need to check the asm again, but it was something like 12 instructions per accessed PCI device (not per register) this would save. And actual MMIO is a completely different magnitude in execution speed. > > > > I just noticed we are not consistent about pci_devfn_t and we assign values with both PCI_DEVFN() and PCI_DEV(b,d,f), latter is left-shifted 12 bits. If we add bus there, calling it .devfn sounds odd too. > > Completely agree about the naming. I was thinking of just removing the open coding at first so we can manipulate things easier. Ya, the 2 macro usages should hopefully be fixed up in the process as well. > > As for urgency it may be worth at least starting a clean up. If I feel ambitious I may give it a go. Indeed. I'll ping you here I complete pushing my related work. I think there is huge potential for merge conflicts here. And we may need to touch entire soc/intel in one commit. We'll see how it goes. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Sep 2019 23:13:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Aaron Durbin (Code Review) 27 Sep '19

27 Sep '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > > Patch Set 5: > > > > > > This is very much incomplete. > > > > > > But idea is, that as PCI bus gets enumerated, each secondary side PCI device path.pci.devfn is updated with the bus number. Changing path.pci structure may be painful, so much of that is open-coded. > > > > $ git grep 'pci[.]devfn' > > > > Oh man. That's quiet a bit of slop in there to clean up. I could give it a pass if you want. We likely need it so that there's only a few touch points to adjust when we need to make changes. Let me know what you guys think. > > Luckily, I don't see this so urgent. I need to check the asm again, but it was something like 12 instructions per accessed PCI device (not per register) this would save. And actual MMIO is a completely different magnitude in execution speed. > > I just noticed we are not consistent about pci_devfn_t and we assign values with both PCI_DEVFN() and PCI_DEV(b,d,f), latter is left-shifted 12 bits. If we add bus there, calling it .devfn sounds odd too. Completely agree about the naming. I was thinking of just removing the open coding at first so we can manipulate things easier. Ya, the 2 macro usages should hopefully be fixed up in the process as well. As for urgency it may be worth at least starting a clean up. If I feel ambitious I may give it a go. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Sep 2019 23:05:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Kyösti Mälkki (Code Review) 27 Sep '19

27 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > This is very much incomplete. > > > > But idea is, that as PCI bus gets enumerated, each secondary side PCI device path.pci.devfn is updated with the bus number. Changing path.pci structure may be painful, so much of that is open-coded. > > $ git grep 'pci[.]devfn' > > Oh man. That's quiet a bit of slop in there to clean up. I could give it a pass if you want. We likely need it so that there's only a few touch points to adjust when we need to make changes. Let me know what you guys think. Luckily, I don't see this so urgent. I need to check the asm again, but it was something like 12 instructions per accessed PCI device (not per register) this would save. And actual MMIO is a completely different magnitude in execution speed. I just noticed we are not consistent about pci_devfn_t and we assign values with both PCI_DEVFN() and PCI_DEV(b,d,f), latter is left-shifted 12 bits. If we add bus there, calling it .devfn sounds odd too. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Sep 2019 23:02:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x131e: correct USB port config
by James (Code Review) 27 Sep '19

27 Sep '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31365 Change subject: mb/lenovo/x131e: correct USB port config ...................................................................... mb/lenovo/x131e: correct USB port config Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc --- M src/mainboard/lenovo/x131e/romstage.c 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31365/1 diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 43e0bd7..7e326e7 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -38,20 +38,20 @@ } const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 1, 0}, - {1, 1, 0}, - {0, 1, 1}, - {1, 1, 1}, - {1, 0, 2}, - {1, 0, 2}, - {0, 0, 3}, - {0, 0, 3}, - {0, 1, 4}, - {1, 1, 4}, - {0, 0, 5}, - {0, 0, 5}, - {0, 0, 6}, - {1, 0, 6}, + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 0, -1}, /* P13: Bluetooth (no OC) */ }; void mainboard_get_spd(spd_raw_data *spd, bool id_only) -- To view, visit https://review.coreboot.org/c/coreboot/+/31365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Gerrit-Change-Number: 31365 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019