coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE
by Aaron Durbin (Code Review) 27 Sep '19

27 Sep '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35654 ) Change subject: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE ...................................................................... Patch Set 2: Code-Review+2 Why did you make me look at this code? That's not very pretty. ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/35654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Gerrit-Change-Number: 35654 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Sep 2019 22:22:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Aaron Durbin (Code Review) 27 Sep '19

27 Sep '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 5: > Patch Set 5: > > This is very much incomplete. > > But idea is, that as PCI bus gets enumerated, each secondary side PCI device path.pci.devfn is updated with the bus number. Changing path.pci structure may be painful, so much of that is open-coded. $ git grep 'pci[.]devfn' Oh man. That's quiet a bit of slop in there to clean up. I could give it a pass if you want. We likely need it so that there's only a few touch points to adjust when we need to make changes. Let me know what you guys think. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Sep 2019 22:20:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Aaron Durbin (Code Review) 27 Sep '19

27 Sep '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/31757/5/src/include/device/pci_ops… File src/include/device/pci_ops.h: https://review.coreboot.org/c/coreboot/+/31757/5/src/include/device/pci_ops… PS5, Line 46: return dev->path.pci.devfn; > This seems to be the meat of the patch, but doesn't that need various changes elsewhere to work? Ya. Enumeration needs to update the bus values of the struct devices that are hanging off the bus. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Sep 2019 22:18:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE
by Kyösti Mälkki (Code Review) 27 Sep '19

27 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35654 ) Change subject: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE ...................................................................... Patch Set 2: This is mostly for consistency and to remove __SIMPLE_DEVICE__ strings from my grep results. -- To view, visit https://review.coreboot.org/c/coreboot/+/35654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Gerrit-Change-Number: 35654 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Sep 2019 22:16:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
by Kyösti Mälkki (Code Review) 27 Sep '19

27 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31757 ) Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree ...................................................................... Patch Set 5: This is very much incomplete. But idea is, that as PCI bus gets enumerated, each secondary side PCI device path.pci.devfn is updated with the bus number. Changing path.pci structure may be painful, so much of that is open-coded. -- To view, visit https://review.coreboot.org/c/coreboot/+/31757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf Gerrit-Change-Number: 31757 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 27 Sep 2019 22:11:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: fmap: Add get_fmap_flash_offset()
by Furquan Shaikh (Code Review) 27 Sep '19

27 Sep '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35639 ) Change subject: fmap: Add get_fmap_flash_offset() ...................................................................... fmap: Add get_fmap_flash_offset() CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/fmap.h M src/lib/coreboot_table.c M src/lib/fmap.c 3 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35639/1 diff --git a/src/include/fmap.h b/src/include/fmap.h index ab7e5ab..f989e5d 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -48,4 +48,8 @@ /* Write provided buffer into fmap area. * Return size written on success, < 0 on error. */ ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size); + +/* Get offset of FMAP in flash. */ +uint64_t get_fmap_flash_offset(void); + #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9c5942f..d3576e6 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -256,7 +256,6 @@ struct lb_boot_media_params *bmp; struct cbfs_props props; const struct region_device *boot_dev; - struct region_device fmrd; boot_device_init(); @@ -275,9 +274,7 @@ bmp->cbfs_size = props.size; bmp->boot_media_size = region_device_sz(boot_dev); - bmp->fmap_offset = ~(uint64_t)0; - if (find_fmap_directory(&fmrd) == 0) - bmp->fmap_offset = region_device_offset(&fmrd); + bmp->fmap_offset = get_fmap_flash_offset(); } static void lb_ram_code(struct lb_header *header) diff --git a/src/lib/fmap.c b/src/lib/fmap.c index f007418..027d6ac 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -31,6 +31,11 @@ static int fmap_print_once CAR_GLOBAL; static struct mem_region_device fmap_cache CAR_GLOBAL; +uint64_t get_fmap_flash_offset(void) +{ + return FMAP_OFFSET; +} + int find_fmap_directory(struct region_device *fmrd) { const struct region_device *boot; -- To view, visit https://review.coreboot.org/c/coreboot/+/35639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Gerrit-Change-Number: 35639 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: add commentary to dev_find_slot()
by Aaron Durbin (Code Review) 27 Sep '19

27 Sep '19

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35632 ) Change subject: device: add commentary to dev_find_slot() ...................................................................... device: add commentary to dev_find_slot() dev_find_slot() can fail sometimes fail to return the desired device object prior to full PCI enumeration. Comment the declaration and implementation accordingly to help the user understand the problem and avoid its usage. Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/device/device_const.c M src/include/device/device.h 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35632/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index 5143563..27197f2 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -24,6 +24,12 @@ /** * Given a PCI bus and a devfn number, find the device structure. * + * Note that this function can return the incorrect device prior + * to PCI enumeration because the secondary field of the bus object + * is 0. The failing scenario is determined by the order of the + * devices in all_devices singly-linked list as well as the time + * when this function is called (secondary reflecting topology). + * * @param bus The bus number. * @param devfn A device/function number. * @return Pointer to the device structure (if found), 0 otherwise. diff --git a/src/include/device/device.h b/src/include/device/device.h index b2221cc..f24e4b2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -298,7 +298,14 @@ DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); -/* To be deprecated, avoid using. */ +/* To be deprecated, avoid using. + * + * Note that this function can return the incorrect device prior + * to PCI enumeration because the secondary field of the bus object + * is 0. The failing scenario is determined by the order of the + * devices in all_devices singly-linked list as well as the time + * when this function is called (secondary reflecting topology). + */ DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn); DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func); -- To view, visit https://review.coreboot.org/c/coreboot/+/35632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Gerrit-Change-Number: 35632 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot_table: Add copy of FMAP
by Patrick Rudolph (Code Review) 27 Sep '19

27 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35377 ) Change subject: coreboot_table: Add copy of FMAP ...................................................................... coreboot_table: Add copy of FMAP For platform independend exposure of FMAP through a kernel module expose the FMAP through coreboot tables. Create a copy of FMAP and place it in CBMEM. Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 3 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35377/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 8d0ca46..30bf88a 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -76,6 +76,7 @@ #define CBMEM_ID_ROM1 0x524f4d31 #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 +#define CBMEM_ID_FMAP 0x464d4150 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -134,5 +135,6 @@ { CBMEM_ID_ROM0, "VGA ROM #0 "}, \ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ - { CBMEM_ID_ROM3, "VGA ROM #3 "}, + { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ + { CBMEM_ID_FMAP, "FMAP "}, #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7bded2a..6816670 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -89,6 +89,7 @@ LB_TAG_VBOOT_WORKBUF = 0x0034, LB_TAG_MMC_INFO = 0x0035, LB_TAG_TCPA_LOG = 0x0036, + LB_TAG_FMAP = 0x0037, LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 95c2ae6..a72150c 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -336,7 +336,8 @@ {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, {CBMEM_ID_VPD, LB_TAG_VPD}, {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, - {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG} + {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG}, + {CBMEM_ID_FMAP, LB_TAG_FMAP}, }; int i; @@ -476,6 +477,34 @@ return (unsigned long)rec + rec->size; } +static void add_fmap_copy_cbmem(void) +{ + struct region_device fmrd; + + if (find_fmap_directory(&fmrd)) { + printk(BIOS_ERR, "Failed to find FMAP\n"); + return; + } + + void *fmap_cbmem = cbmem_add(CBMEM_ID_FMAP, region_device_sz(&fmrd)); + if (!fmap_cbmem) { + printk(BIOS_ERR, "Failed to allocate CBMEM\n"); + return; + } + + void *fmap_reg = rdev_mmap_full(&fmrd); + if (!fmap_reg) { + printk(BIOS_ERR, "Failed to mmap FMAP device\n"); + return; + } + + memcpy(fmap_cbmem, fmap_reg, region_device_sz(&fmrd)); + printk(BIOS_ERR, "fmap_cbmem %x\n", *((uint32_t*)(fmap_cbmem))); + printk(BIOS_ERR, "fmap_cbmem %x\n", *((uint32_t*)(fmap_cbmem+4))); + + rdev_munmap(&fmrd, fmap_reg); +} + size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) { struct lb_header *head; @@ -563,6 +592,8 @@ if (CONFIG(BOOT_DEVICE_SPI_FLASH)) lb_spi_flash(head); + /* Add copy of FMAP to CBMEM */ + add_fmap_copy_cbmem(); add_cbmem_pointers(head); /* Add board-specific table entries, if any. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5 Gerrit-Change-Number: 35377 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11: remove vendor id config
by Michael Niewöhner (Code Review) 27 Sep '19

27 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35524 ) Change subject: mb/supermicro/x11: remove vendor id config ...................................................................... mb/supermicro/x11: remove vendor id config The vendor id option is useless here as the SSVID is set to the default value from the PCI Cfg register anyway. Besides that the Kconfig option isn't meant for retrofit ports (see 7e1c83). The right place would be the devicetree. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: If67c679bb342f63096902535734106e4f1651118 --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35524/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 28b3495..3aaf1d3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -66,10 +66,6 @@ int default 8 -config SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config CONSOLE_POST bool default y -- To view, visit https://review.coreboot.org/c/coreboot/+/35524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If67c679bb342f63096902535734106e4f1651118 Gerrit-Change-Number: 35524 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Build test CONFIG_BOOTSPLASH
by Patrick Rudolph (Code Review) 27 Sep '19

27 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35615 ) Change subject: configs: Build test CONFIG_BOOTSPLASH ...................................................................... configs: Build test CONFIG_BOOTSPLASH Change-Id: I306d107720d51c2b378f739f68c31b8642f7354a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M configs/config.emulation_qemu_x86_i440fx_noserial 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/35615/1 diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial index 66b46c7..8000a23 100644 --- a/configs/config.emulation_qemu_x86_i440fx_noserial +++ b/configs/config.emulation_qemu_x86_i440fx_noserial @@ -4,3 +4,4 @@ CONFIG_CONSOLE_POST=y CONFIG_LINEAR_FRAMEBUFFER=y # CONFIG_CONSOLE_SERIAL is not set +CONFIG_BOOTSPLASH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/35615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I306d107720d51c2b378f739f68c31b8642f7354a Gerrit-Change-Number: 35615 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019