coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

1 participants
1442 discussions

Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 26 Sep '19

26 Sep '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#19). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs GET_BOOT_PARTITION_INFO - provides info on available partitions in the cse region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Also, made minor changes to group macro definitions of group ids, command ids and renamed macro definitions of hmrfpo commands. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 404 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 19 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 26 Sep '19

26 Sep '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#18). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs GET_BOOT_PARTITION_INFO - provides info on available partitions in the cse region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Also, made minor changes to group macro definitions of group ids, command ids and renamed macro definitions of hmrfpo commands. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 405 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 18 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 26 Sep '19

26 Sep '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#17). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs GET_BOOT_PARTITION_INFO - provides info on available partitions in the cse region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Also, made minor changes to group macro definitions of group ids, command ids and renamed macro definitions of hmrfpo commands. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M 3rdparty/blobs M 3rdparty/intel-microcode M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 6 files changed, 407 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/superio: add support to dump all ldns
by Alexander Couzens (Code Review) 26 Sep '19

26 Sep '19

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35608 ) Change subject: util/superio: add support to dump all ldns ...................................................................... util/superio: add support to dump all ldns The dump of all LDNs shows all registers while iterating over the LDN address space. Change-Id: I52450725a21a9ecf0bd0d5fd06a8ac5918d17523 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M util/superiotool/ite.c M util/superiotool/superiotool.c M util/superiotool/superiotool.h 3 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35608/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 2e21e80..d17149d 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1496,6 +1496,7 @@ static void probe_idregs_ite_helper(const char *init, uint16_t port) { uint16_t id, chipver, ecport; + uint16_t ldn, reg, i; probing_for("ITE", init, port); @@ -1536,6 +1537,22 @@ printf("BRAM (0x%04x)\n", ecport); dump_superio("ITE-BRAM", bram_table, ecport, id, LDN_SEL); } + + if (full_dump) { + for (ldn = 0; ldn <= 0xff; ldn++) { + regwrite(port, LDN_SEL, ldn); /* Select LDN 16 (BRAM). */ + printf("LDN 0x%02x\n", ldn); + for (reg = 0; reg < 0x100; reg +=8) { + printf("0x%02x: ", reg); + for (i=0; i < 8; i++) + if (i < 7) + printf("%02x ", regval(port, reg + i)); + else + printf("%02x", regval(port, reg + i)); + printf("\n"); + } + } + } } void probe_idregs_ite(uint16_t port) diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index 3e21b0c..17f41ee 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -25,7 +25,7 @@ #endif /* Command line options. */ -int dump = 0, verbose = 0, extra_dump = 0, alternate_dump = 0; +int dump = 0, verbose = 0, extra_dump = 0, alternate_dump = 0, full_dump = 0; /* Global flag which indicates whether a chip was detected at all. */ int chip_found = 0; @@ -292,6 +292,7 @@ #endif static const struct option long_options[] = { + {"full-dump", no_argument, NULL, 'D'}, {"dump", no_argument, NULL, 'd'}, {"extra-dump", no_argument, NULL, 'e'}, {"alternate-dump", no_argument, NULL, 'a'}, @@ -302,9 +303,12 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "dealVvh", + while ((opt = getopt_long(argc, argv, "DdealVvh", long_options, &option_index)) != EOF) { switch (opt) { + case 'D': + full_dump = 1; + break; case 'd': dump = 1; break; diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index d3b9fd0..950f9f7 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -111,6 +111,7 @@ #define USAGE "Usage: superiotool [-d] [-e] [-a] [-l] [-V] [-v] [-h]\n\n\ -d | --dump Dump Super I/O register contents\n\ -e | --extra-dump Dump secondary registers too (e.g. EC registers)\n\ + -D | --full-dump Dump ALL Super I/O register contents regardless off visiability\n\ -a | --alternate-dump Use alternative dump format, more suitable for diff\n\ -l | --list-supported Show the list of supported Super I/O chips\n\ -V | --verbose Verbose mode\n\ @@ -147,7 +148,7 @@ #define WINBOND_HWM_SEL 0x4e /* Hardware monitor bank select */ /* Command line parameters. */ -extern int dump, verbose, extra_dump; +extern int dump, verbose, extra_dump, full_dump; extern int chip_found; -- To view, visit https://review.coreboot.org/c/coreboot/+/35608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52450725a21a9ecf0bd0d5fd06a8ac5918d17523 Gerrit-Change-Number: 35608 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/supermicro: convert x11ssh to variants-capable tree structure
by Michael Niewöhner (Code Review) 26 Sep '19

26 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35426 ) Change subject: mb/supermicro: convert x11ssh to variants-capable tree structure ...................................................................... mb/supermicro: convert x11ssh to variants-capable tree structure Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M Documentation/mainboard/index.md R Documentation/mainboard/supermicro/x11/ssh-tf/x11ssh-tf.md R Documentation/mainboard/supermicro/x11/ssh-tf/x11ssh_flash.jpg R src/mainboard/supermicro/x11/Kconfig A src/mainboard/supermicro/x11/Kconfig.name R src/mainboard/supermicro/x11/Makefile.inc R src/mainboard/supermicro/x11/acpi/ec.asl R src/mainboard/supermicro/x11/acpi/mainboard.asl R src/mainboard/supermicro/x11/acpi/superio.asl R src/mainboard/supermicro/x11/acpi_tables.c R src/mainboard/supermicro/x11/bootblock.c R src/mainboard/supermicro/x11/cmos.layout R src/mainboard/supermicro/x11/devicetree.cb R src/mainboard/supermicro/x11/dsdt.asl R src/mainboard/supermicro/x11/ramstage.c R src/mainboard/supermicro/x11/romstage.c A src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig A src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig.name R src/mainboard/supermicro/x11/variants/ssh-tf/board_info.txt A src/mainboard/supermicro/x11/variants/ssh-tf/devicetree.cb R src/mainboard/supermicro/x11/variants/ssh-tf/include/variant/gpio.h R src/mainboard/supermicro/x11/vboot-ro-rwab.fmd D src/mainboard/supermicro/x11ssh/Kconfig.name D src/mainboard/supermicro/x11ssh/board_info.txt 24 files changed, 164 insertions(+), 148 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35426/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 08689b7..62d8dd3 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -111,7 +111,7 @@ ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) -- [X11SSH-TF](supermicro/x11ssh-tf.md) +- [X11SSH-TF](supermicro/x11/ssh-tf/x11ssh-tf.md) ## UP diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11/ssh-tf/x11ssh-tf.md similarity index 100% rename from Documentation/mainboard/supermicro/x11ssh-tf.md rename to Documentation/mainboard/supermicro/x11/ssh-tf/x11ssh-tf.md diff --git a/Documentation/mainboard/supermicro/x11ssh_flash.jpg b/Documentation/mainboard/supermicro/x11/ssh-tf/x11ssh_flash.jpg similarity index 100% rename from Documentation/mainboard/supermicro/x11ssh_flash.jpg rename to Documentation/mainboard/supermicro/x11/ssh-tf/x11ssh_flash.jpg Binary files differ diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11/Kconfig similarity index 74% rename from src/mainboard/supermicro/x11ssh/Kconfig rename to src/mainboard/supermicro/x11/Kconfig index 4f18a80..98e1125 100644 --- a/src/mainboard/supermicro/x11ssh/Kconfig +++ b/src/mainboard/supermicro/x11/Kconfig @@ -1,5 +1,7 @@ -config BOARD_SUPERMICRO_BASEBOARD_X11SSH - def_bool n +if BOARD_SUPERMICRO_X11SSH_TF + +config BOARD_SPECIFIC_OPTIONS + def_bool y select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -12,7 +14,17 @@ select GENERATE_SMBIOS_TABLES select IPMI_KCS -if BOARD_SUPERMICRO_BASEBOARD_X11SSH +config MAINBOARD_DIR + string + default "supermicro/x11" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config MAINBOARD_FAMILY + string + default "Supermicro_X11" config VBOOT select VBOOT_NO_BOARD_SUPPORT @@ -28,34 +40,18 @@ hex default 0x2a +config CBFS_SIZE + hex + default 0xb00000 if VBOOT + config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB -config CBFS_SIZE - hex - default 0x009aa000 if !VBOOT - config IRQ_SLOT_COUNT int default 18 -config MAINBOARD_DIR - string - default "supermicro/x11ssh" - -config VARIANT_DIR - string - default "tf" if BOARD_SUPERMICRO_X11SSH_PLUS_TF - -config DEVICETREE - string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" - -config MAINBOARD_PART_NUMBER - string - default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_PLUS_TF - config MAX_CPUS int default 8 @@ -76,4 +72,6 @@ int default 512 -endif # BOARD_SUPERMICRO_BASEBOARD_X11SSH +source "src/mainboard/supermicro/x11/variants/*/Kconfig" + +endif # BOARD_SUPERMICRO_X11SSH_TF diff --git a/src/mainboard/supermicro/x11/Kconfig.name b/src/mainboard/supermicro/x11/Kconfig.name new file mode 100644 index 0000000..ec23e7d --- /dev/null +++ b/src/mainboard/supermicro/x11/Kconfig.name @@ -0,0 +1 @@ +source "src/mainboard/supermicro/x11/variants/*/Kconfig.name" diff --git a/src/mainboard/supermicro/x11ssh/Makefile.inc b/src/mainboard/supermicro/x11/Makefile.inc similarity index 100% rename from src/mainboard/supermicro/x11ssh/Makefile.inc rename to src/mainboard/supermicro/x11/Makefile.inc diff --git a/src/mainboard/supermicro/x11ssh/acpi/ec.asl b/src/mainboard/supermicro/x11/acpi/ec.asl similarity index 100% rename from src/mainboard/supermicro/x11ssh/acpi/ec.asl rename to src/mainboard/supermicro/x11/acpi/ec.asl diff --git a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl b/src/mainboard/supermicro/x11/acpi/mainboard.asl similarity index 100% rename from src/mainboard/supermicro/x11ssh/acpi/mainboard.asl rename to src/mainboard/supermicro/x11/acpi/mainboard.asl diff --git a/src/mainboard/supermicro/x11ssh/acpi/superio.asl b/src/mainboard/supermicro/x11/acpi/superio.asl similarity index 100% rename from src/mainboard/supermicro/x11ssh/acpi/superio.asl rename to src/mainboard/supermicro/x11/acpi/superio.asl diff --git a/src/mainboard/supermicro/x11ssh/acpi_tables.c b/src/mainboard/supermicro/x11/acpi_tables.c similarity index 100% rename from src/mainboard/supermicro/x11ssh/acpi_tables.c rename to src/mainboard/supermicro/x11/acpi_tables.c diff --git a/src/mainboard/supermicro/x11ssh/bootblock.c b/src/mainboard/supermicro/x11/bootblock.c similarity index 97% rename from src/mainboard/supermicro/x11ssh/bootblock.c rename to src/mainboard/supermicro/x11/bootblock.c index 8bc8ab0..27653f5 100644 --- a/src/mainboard/supermicro/x11ssh/bootblock.c +++ b/src/mainboard/supermicro/x11/bootblock.c @@ -15,7 +15,7 @@ #include <bootblock_common.h> #include <soc/gpio.h> -#include "gpio.h" +#include <variant/gpio.h> #include <superio/aspeed/common/aspeed.h> #include <superio/aspeed/ast2400/ast2400.h> #include <delay.h> diff --git a/src/mainboard/supermicro/x11ssh/cmos.layout b/src/mainboard/supermicro/x11/cmos.layout similarity index 100% rename from src/mainboard/supermicro/x11ssh/cmos.layout rename to src/mainboard/supermicro/x11/cmos.layout diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11/devicetree.cb similarity index 60% rename from src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb rename to src/mainboard/supermicro/x11/devicetree.cb index ce6bfa5..ea4f7a1 100644 --- a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb +++ b/src/mainboard/supermicro/x11/devicetree.cb @@ -5,19 +5,6 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - register "gen1_dec" = "0x007c0a01" # Super IO SWC - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - register "gen3_dec" = "0x000c03e1" # UART3 - register "gen4_dec" = "0x000c02e1" # UART4 - # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -102,23 +89,6 @@ # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" - # PCIe configuration - # Enable JPCIE1 - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "0" - - # Enable ASpeed PCI bridge - register "PcieRpEnable[2]" = "1" - register "PcieRpClkReqSupport[2]" = "0" - - # Enable X550T (10GbE) - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "0" - - # Enable M.2 - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "0" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02" @@ -201,90 +171,25 @@ device lapic 0 on end end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 on end # unused - device pci 01.1 on - smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" - end # PCIE Slot (JPCIE1) - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 17.0 on end # SATA - device pci 1c.0 on - smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" - end # PCI Express Port 1 (Slot JPCIE1) - device pci 1c.2 on - device pci 00.0 on - device pci 00.0 on end # Aspeed 2400 VGA - end - end # PCI Express Port 3 - device pci 1c.4 on - device pci 00.0 on end # 10GbE - device pci 00.1 on end # 10GbE - end # PCI Express Port 5 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" - end # PCI Express Port 9 - device pci 1f.0 on - chip drivers/ipmi - # On cold boot it takes a while for the BMC to start the IPMI service - register "wait_for_bmc" = "1" - register "bmc_boot_timeout" = "60" - device pnp ca2.0 on end # IPMI KCS - end + device pci 00.0 on end # Host Bridge + device pci 04.0 on end # SA thermal subsystem + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 17.0 on end # SATA + device pci 1f.0 on # LPC Interface chip superio/common - device pnp 2e.0 on - chip superio/aspeed/ast2400 - device pnp 2e.2 on # SUART1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # SUART2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 on # SWC - io 0x60 = 0xa00 - io 0x62 = 0xa10 - io 0x64 = 0xa20 - io 0x66 = 0xa30 - irq 0x70 = 0xb - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 0xc - end - device pnp 2e.7 on # GPIO - end - device pnp 2e.b on # SUART3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.c on # SUART4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.d on # iLPC2AHB - end - device pnp 2e.e on # Mailbox - io 0x60 = 0xa40 - irq 0x70 = 0x00 - end - end - end + device pnp 2e.0 on end end - chip drivers/pc80/tpm + chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI Controller + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI Controller end end diff --git a/src/mainboard/supermicro/x11ssh/dsdt.asl b/src/mainboard/supermicro/x11/dsdt.asl similarity index 100% rename from src/mainboard/supermicro/x11ssh/dsdt.asl rename to src/mainboard/supermicro/x11/dsdt.asl diff --git a/src/mainboard/supermicro/x11ssh/ramstage.c b/src/mainboard/supermicro/x11/ramstage.c similarity index 96% rename from src/mainboard/supermicro/x11ssh/ramstage.c rename to src/mainboard/supermicro/x11/ramstage.c index 2672f73..f27aefc 100644 --- a/src/mainboard/supermicro/x11ssh/ramstage.c +++ b/src/mainboard/supermicro/x11/ramstage.c @@ -13,7 +13,7 @@ #include <bootstate.h> #include <soc/ramstage.h> -#include "gpio.h" +#include <variant/gpio.h> void mainboard_silicon_init_params(FSP_SIL_UPD *params) { diff --git a/src/mainboard/supermicro/x11ssh/romstage.c b/src/mainboard/supermicro/x11/romstage.c similarity index 100% rename from src/mainboard/supermicro/x11ssh/romstage.c rename to src/mainboard/supermicro/x11/romstage.c diff --git a/src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig b/src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig new file mode 100644 index 0000000..f8954da --- /dev/null +++ b/src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig @@ -0,0 +1,15 @@ +if BOARD_SUPERMICRO_X11SSH_TF + +config VARIANT_DIR + string + default "ssh-tf" + +config MAINBOARD_PART_NUMBER + string + default "X11SSH-TF" + +config CBFS_SIZE + hex + default 0x009aa000 if !VBOOT + +endif # BOARD_SUPERMICRO_X11SSH_TF diff --git a/src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig.name b/src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig.name new file mode 100644 index 0000000..fe3bf71 --- /dev/null +++ b/src/mainboard/supermicro/x11/variants/ssh-tf/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X11SSH_TF + bool "X11SSH-TF" diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt b/src/mainboard/supermicro/x11/variants/ssh-tf/board_info.txt similarity index 61% rename from src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt rename to src/mainboard/supermicro/x11/variants/ssh-tf/board_info.txt index f3eb3ef..893ccf4 100644 --- a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt +++ b/src/mainboard/supermicro/x11/variants/ssh-tf/board_info.txt @@ -1,6 +1,7 @@ +Category: server Vendor name: Supermicro Board name: X11SSH-TF -Category: server +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-TF ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/supermicro/x11/variants/ssh-tf/devicetree.cb b/src/mainboard/supermicro/x11/variants/ssh-tf/devicetree.cb new file mode 100644 index 0000000..f979b67 --- /dev/null +++ b/src/mainboard/supermicro/x11/variants/ssh-tf/devicetree.cb @@ -0,0 +1,103 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # PCIe configuration + # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + + # Enable ASpeed PCI bridge + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + + # Enable X550T (10GbE) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + + # Enable M.2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + + device domain 0 on + device pci 01.0 on end # unused + device pci 01.1 on + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" + end # PCIE Slot (JPCIE1) + device pci 1c.0 on + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" + end # PCI Express Port 1 (Slot JPCIE1) + device pci 1c.2 on + device pci 00.0 on + device pci 00.0 on end # Aspeed 2400 VGA + end + end # PCI Express Port 3 + device pci 1c.4 on + device pci 00.0 on end # 10GbE + device pci 00.1 on end # 10GbE + end # PCI Express Port 5 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" + end # PCI Express Port 9 + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 0xc + end + device pnp 2e.7 on end # GPIO + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on end # iLPC2AHB + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end diff --git a/src/mainboard/supermicro/x11ssh/gpio.h b/src/mainboard/supermicro/x11/variants/ssh-tf/include/variant/gpio.h similarity index 100% rename from src/mainboard/supermicro/x11ssh/gpio.h rename to src/mainboard/supermicro/x11/variants/ssh-tf/include/variant/gpio.h diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11/vboot-ro-rwab.fmd similarity index 100% rename from src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd rename to src/mainboard/supermicro/x11/vboot-ro-rwab.fmd diff --git a/src/mainboard/supermicro/x11ssh/Kconfig.name b/src/mainboard/supermicro/x11ssh/Kconfig.name deleted file mode 100644 index a9b351b..0000000 --- a/src/mainboard/supermicro/x11ssh/Kconfig.name +++ /dev/null @@ -1,3 +0,0 @@ -config BOARD_SUPERMICRO_X11SSH_PLUS_TF - bool "X11SSH+-TF" - select BOARD_SUPERMICRO_BASEBOARD_X11SSH diff --git a/src/mainboard/supermicro/x11ssh/board_info.txt b/src/mainboard/supermicro/x11ssh/board_info.txt deleted file mode 100644 index 029d2a9..0000000 --- a/src/mainboard/supermicro/x11ssh/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Supermicro -Board name: X11SSH Baseboard -Category: server -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -- To view, visit https://review.coreboot.org/c/coreboot/+/35426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29 Gerrit-Change-Number: 35426 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

8 65

Change in coreboot[master]: soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code
by Richard Spiegel (Code Review) 26 Sep '19

26 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35589 ) Change subject: soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code ...................................................................... soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code All solid state devices have vendor id defined by JEDEC specification JEP106, which originally allocated only 7 bits for it plus parity. When number of vendors exploded beyond 126, a banking proposition came maintaining compatibility with older vendors while allowing for 4 extra bits (16 banks) through the introduction of the concept "Continuation code", denoted by the byte value of 0x7f. Examples: 0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o 0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2 BUG=b:141535133 TEST=Build and boot grunt. Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/include/amdblocks/fch_spi.h M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/common/block/spi/fch_spi_table.c 3 files changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35589/1 diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h index cfbdf19..8e28828 100644 --- a/src/soc/amd/common/block/include/amdblocks/fch_spi.h +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -23,7 +23,14 @@ #define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000) #define SPI_PAGE_WRITE 0x02 #define SPI_WRITE_ENABLE 0x06 -#define IDCODE_CONT_LEN 0 +/* + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + */ +#define IDCODE_CONT_CODE 0x7f +#define IDCODE_CONT_LEN 1 /* currently support only bank 0 */ #define IDCODE_PART_LEN 5 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 4299e4f..a7d9c77 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -278,12 +278,26 @@ printk(BIOS_SPEW, "\n"); } - /* count the number of continuation bytes */ - for (shift = 0, idp = idcode; shift < IDCODE_CONT_LEN && *idp == 0x7f; - ++shift, ++idp) - continue; + /* + * All solid state devices have vendor id defined by JEDEC specification JEP106, + * which originally allocated only 7 bits for it plus parity. When number of + * vendors exploded beyond 126, a banking proposition came maintaining + * compatibility with older vendors while allowing for 4 extra bits (16 banks) + * through the introduction of the concept "Continuation Code", denoted by the + * byte value of 0x7f. + * Examples: + * 0xfe, 0x60, 0x18, 0x00, 0x00, 0x00 => vendor 0xfe of bank o + * 0x7f, 0x7f, 0xfe, 0x60, 0x18, 0x00 => vendor 0xfe of bank 2 + * count the number of continuation code bytes + */ + for (shift = 0, idp = idcode; *idp == IDCODE_CONT_CODE; ++shift, ++idp) { + if (shift < IDCODE_CONT_LEN) + continue; + printk(BIOS_ERR, "unsupported ID code bank\n"); + return -1; + } - printk(BIOS_INFO, "Manufacturer: %02x\n", *idp); + printk(BIOS_INFO, "Manufacturer: %02x on bank %d\n", *idp, shift); /* search the table for matches in shift and id */ for (i = 0; i < table_size; ++i) { diff --git a/src/soc/amd/common/block/spi/fch_spi_table.c b/src/soc/amd/common/block/spi/fch_spi_table.c index 8c0108a..acea241 100644 --- a/src/soc/amd/common/block/spi/fch_spi_table.c +++ b/src/soc/amd/common/block/spi/fch_spi_table.c @@ -30,11 +30,6 @@ * Several matching entries are permitted, they will be tried * in sequence until a probe function returns non NULL. * - * IDCODE_CONT_LEN may be redefined if a device needs to declare a - * larger "shift" value. IDCODE_PART_LEN generally shouldn't be - * changed. This is the max number of bytes probe functions may - * examine when looking up part-specific identification info. - * * Probe functions will be given the idcode buffer starting at their * manu id byte (the "idcode" in the table below). In other words, * all of the continuation bytes will be skipped (the "shift" below). -- To view, visit https://review.coreboot.org/c/coreboot/+/35589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c Gerrit-Change-Number: 35589 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/fsp_broadwell_de: move get_busno1() into vtd.c
by Andrey Petrov (Code Review) 26 Sep '19

26 Sep '19

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35585 ) Change subject: soc/intel/fsp_broadwell_de: move get_busno1() into vtd.c ...................................................................... soc/intel/fsp_broadwell_de: move get_busno1() into vtd.c TEST=just build it Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/fsp_broadwell_de/include/soc/vtd.h M src/soc/intel/fsp_broadwell_de/vtd.c 3 files changed, 15 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35585/1 diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 7b8a788..f0944da 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -16,6 +16,7 @@ romstage-y += tsc_freq.c romstage-y += smbus-imc.c romstage-y += ubox.c +romstage-y += vtd.c postcar-y += tsc_freq.c diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h index 814cba0..f1087d1 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h @@ -30,13 +30,6 @@ #define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29) #define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30) -static inline uint8_t get_busno1(void) -{ - uint32_t reg32; - - /* Figure out what bus number is assigned for CPUBUSNO(1) */ - reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO); - return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK); -} +uint8_t get_busno1(void); #endif diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c index 318927a..9e03e9b 100644 --- a/src/soc/intel/fsp_broadwell_de/vtd.c +++ b/src/soc/intel/fsp_broadwell_de/vtd.c @@ -18,8 +18,10 @@ #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <soc/acpi.h> +#include <soc/vtd.h> #include <soc/broadwell_de.h> +#if ENV_RAMSTAGE static void vtd_read_resources(struct device *dev) { @@ -44,3 +46,14 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = VTD_DEVID, }; + +#endif + +uint8_t get_busno1(void) +{ + uint32_t reg32; + + /* Figure out what bus number is assigned for CPUBUSNO(1) */ + reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO); + return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7 Gerrit-Change-Number: 35585 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Huayang Duan (Code Review) 26 Sep '19

26 Sep '19

Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 11: Code-Review+2 > Patch Set 11: Code-Review-1 > > @huayang Do we still need this CL? yes,must have those patch -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 11 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Sep 2019 08:51:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Yu-Ping Wu (Code Review) 26 Sep '19

26 Sep '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 11: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 11 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Sep 2019 08:47:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Yu-Ping Wu (Code Review) 26 Sep '19

26 Sep '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 11: Code-Review-1 @huayang Do we still need this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 11 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Sep 2019 08:47:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2019