coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/mainboard/hatch: support elan touchpad for Akemi
by Peichao Li (Code Review) 26 Sep '19

26 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35551 ) Change subject: mb/mainboard/hatch: support elan touchpad for Akemi ...................................................................... mb/mainboard/hatch: support elan touchpad for Akemi BUG=b:141519690 TEST=build bios and verify elan touchpad work fine Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35551/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 88d33e7..c34168a 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -64,7 +64,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" register "probed" = "1" device i2c 15 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/35551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 Gerrit-Change-Number: 35551 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by Patrick Rudolph (Code Review) 26 Sep '19

26 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 ) Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... Patch Set 4: Where do I get the firmware blobs from? Needs to be documented. -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 4 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 26 Sep 2019 05:59:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Patrick Rudolph (Code Review) 26 Sep '19

26 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 16: The motivation as well as documentation is missing. Which code will use it and why? -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Sep 2019 05:51:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: google/grunt: add new two DDR source for Treeya
by Peichao Li (Code Review) 26 Sep '19

26 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35590 ) Change subject: google/grunt: add new two DDR source for Treeya ...................................................................... google/grunt: add new two DDR source for Treeya new DDR particle: 1. Samung K4A8G165WC-BCWE 2. Hynix H5AN8G6NCJR-XNC BUG=b:139085024 BRANCH=master TEST=rework new source to DUT and re-flash bios to DUT and verify DUT will bring up successfully Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5 --- A src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex A src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex M src/mainboard/google/kahlee/variants/treeya/Makefile.inc A src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc 4 files changed, 103 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35590/1 diff --git a/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex b/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex new file mode 100644 index 0000000..6b68ce2 --- /dev/null +++ b/src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex @@ -0,0 +1,34 @@ +# H5AN8G6NCJR-XNC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 +36 43 4A 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + diff --git a/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex new file mode 100644 index 0000000..9cbc023 --- /dev/null +++ b/src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex @@ -0,0 +1,34 @@ +# Samsung-K4A8G165WC-BCWE +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 43 42 30 2D 43 57 45 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index 0579e18..17ea78e 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -subdirs-y += ../baseboard/spd +subdirs-y += ./spd romstage-y += ../baseboard/romstage.c diff --git a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc new file mode 100644 index 0000000..a478ed5 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 +SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 +SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 +SPD_SOURCES += micron-MT40A1G16KNR-075-E # 0b0011 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100 +SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101 +SPD_SOURCES += micron-MT40A512M16LY-075-E # 0b0110 +SPD_SOURCES += hynix-H5ANAG6NCMR-VKC # 0b0111 +SPD_SOURCES += hynix-H5AN8G6NCJR-VKC # 0b1000 +SPD_SOURCES += samsung-K4A8G165WC-BCTD # 0b1001 +SPD_SOURCES += samsung-K4AAG165WB-MCTD # 0b1010 +SPD_SOURCES += micron-MT40A512M16TB-062E-J # 0b1011 +SPD_SOURCES += samsung-K4A8G165WC-BCWE.spd.hex # 0b1100 +SPD_SOURCES += hynix-H5AN8G6NCJR-XNC.spd.hex # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 -- To view, visit https://review.coreboot.org/c/coreboot/+/35590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5 Gerrit-Change-Number: 35590 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/: Clean up microcode update from __PRE_RAM__
by Kyösti Mälkki (Code Review) 26 Sep '19

26 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35587 ) Change subject: cpu/intel/: Clean up microcode update from __PRE_RAM__ ...................................................................... cpu/intel/: Clean up microcode update from __PRE_RAM__ Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35587/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index ed660a7..feb73c8 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -24,11 +24,9 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> - -#if !defined(__PRE_RAM__) #include <smp/spinlock.h> + DECLARE_SPIN_LOCK(microcode_lock) -#endif struct microcode { u32 hdrver; /* Header Version */ @@ -225,15 +223,11 @@ { const void *patch = intel_microcode_find(); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_lock(&microcode_lock); -#endif intel_microcode_load_unlocked(patch); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_unlock(&microcode_lock); -#endif } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/35587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27 Gerrit-Change-Number: 35587 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__
by Kyösti Mälkki (Code Review) 26 Sep '19

26 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35586 ) Change subject: cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__ ...................................................................... cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__ It is only called in ramstage. Even if it was called in romstage, execution flow is such that BSP and AP CPUs should not be able to enter update_microcode() routine concurrently. Also the Kconfig guarding the spin_lock() calls are not selected nor are the lock variables declared for these platforms. Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/amd/pi/00730F01/microcode_fam16h.c 2 files changed, 1 insertion(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35586/1 diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 5e49869..c4a92cf 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -12,8 +12,6 @@ # romstage-y += fixme.c -romstage-y += update_microcode.c -romstage-y += microcode_fam16h.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/pi/00730F01/microcode_fam16h.c b/src/cpu/amd/pi/00730F01/microcode_fam16h.c index 1251c38..1f1dbd9 100644 --- a/src/cpu/amd/pi/00730F01/microcode_fam16h.c +++ b/src/cpu/amd/pi/00730F01/microcode_fam16h.c @@ -16,8 +16,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> #include <cbfs.h> -#include <arch/io.h> -#include <smp/spinlock.h> /* * Values and header structure from: @@ -122,22 +120,12 @@ "Skipping microcode patch!\n"); return; } -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_lock(romstage_microcode_cbfs_lock()); -#endif -#endif ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. " "Skipping updates.\n"); -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif return; } @@ -145,21 +133,8 @@ ucode_len < F16H_MPB_DATA_OFFSET) { printk(BIOS_DEBUG, "microcode file invalid. Skipping " "updates.\n"); -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif return; } - amd_update_microcode(ucode, ucode_len, - equivalent_processor_rev_id); - -#ifdef __PRE_RAM__ -#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) - spin_unlock(romstage_microcode_cbfs_lock()); -#endif -#endif - + amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c Gerrit-Change-Number: 35586 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: export gpio config
by Alexander Couzens (Code Review) 26 Sep '19

26 Sep '19

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35609 ) Change subject: util/inteltool: export gpio config ...................................................................... util/inteltool: export gpio config TODO: add a switch for inteltool to print this version Change-Id: I16d625f6a844bc328fd95d4661ed56db246ca76b Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M util/inteltool/gpio_groups.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35609/1 diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97..2310c5e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2179,7 +2179,7 @@ { size_t p; - printf("%s\n", group->display); + printf("/* %s */\n", group->display); for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) { const uint32_t dw0 = read_pcr32(pid, pad_cfg); @@ -2187,7 +2187,11 @@ const char *const pad_name = group->pad_names[p * group->func_count]; - printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, + printf("\t// %s,\n", decode_pad_mode(group, p, dw0)); + printf("\t_PAD_CFG_STRUCT(%s\t0x%08x, 0x%08x),\n", + pad_name[0] == '*' ? &pad_name[1] : pad_name, dw0, dw1); + + fprintf(stderr, "0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, (uint64_t)dw1 << 32 | dw0, pad_name[0] == '*' ? &pad_name[1] : pad_name, decode_pad_mode(group, p, dw0)); @@ -2200,7 +2204,7 @@ size_t group, pad_count; size_t pad_cfg; /* offset in bytes under this communities PCR port */ - printf("%s\n\nPCR Port ID: 0x%06zx\n\n", + printf("/* %s\n\nPCR Port ID: 0x%06zx */\n\n", community->name, (size_t)community->pcr_port_id << 16); for (group = 0, pad_count = 0; group < community->group_count; ++group) -- To view, visit https://review.coreboot.org/c/coreboot/+/35609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16d625f6a844bc328fd95d4661ed56db246ca76b Gerrit-Change-Number: 35609 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK
by mturney mturney (Code Review) 25 Sep '19

25 Sep '19

Hello ashk(a)codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35508 to look at the new patch set (#4). Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... HACK trogdor: SoC makefile BLOB support HACK Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 114 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35508/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 4 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 25 Sep '19

25 Sep '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 16: (5 comments) https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 59: static struct cse_boot_partition_info cse_bp_info; : static bool cse_bp_init = false; > With this approach, complete response structure will be static. […] Done https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 125: memcpy((void *)&cse_bp_info, (void *)&info_resp.bp_info, : sizeof(struct cse_boot_partition_info)); > Agreed, please see my earlier response. Done https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 128: return 1; > Please see my earlier response. Done https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 135: static uint8_t cse_init_bp_info(bool force_cse_init) : { : if (cse_bp_init == false || force_cse_init == true) { : if (!cse_update_boot_partition_info()) { : printk(BIOS_ERR, "Boot partition update fail\n"); : return 0; : } : cse_print_boot_partition_info(); : } : cse_bp_init = true; : return 1; : } > This function checks if it needs to update boot partition info or not. […] Done https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 214: if (!cse_init_bp_info(false)) : return 0; > Please see my above response. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Sep 2019 16:44:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Paul Menzel (Code Review) 25 Sep '19

25 Sep '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (10 comments) https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@7 PS4, Line 7: low power idle table Use LPIT here, and the full name in the commit message body. https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@7 PS4, Line 7: src/arch/x86:Add 1. `src/` not needed. 2. Please add a space after the colon https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@9 PS4, Line 9: residency.Residencies Space after . https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@13 PS4, Line 13: CPU PKG C10 (Read via FFH interface) : Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface) Please add blank lines around, and format it as a list. https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@17 PS4, Line 17: /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us : /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Please indent with four spaces, and add blank lines around the block. https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@21 PS4, Line 21: The “low_power_idle_system_residency_us” attribute shows SLP_S0 residency, or Please add a blank line above to separate paragraphs visually. https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@26 PS4, Line 26: Example: Please add a blank line above. https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@28 PS4, Line 28: thet that https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@31 PS4, Line 31: elected selected https://review.coreboot.org/c/coreboot/+/32350/4//COMMIT_MSG@31 PS4, Line 31: thet that -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Sep 2019 16:31:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2019