coreboot-gerrit September 2019

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 25 Sep '19

25 Sep '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 16: (6 comments) https://review.coreboot.org/c/coreboot/+/35402/14//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35402/14//COMMIT_MSG@17 PS14, Line 17: definations > definition Done https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 59: static struct cse_boot_partition_info cse_bp_info; : static bool cse_bp_init = false; > Can we group them into one construct? something like […] With this approach, complete response structure will be static. It also includes the HECI header https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 125: memcpy((void *)&cse_bp_info, (void *)&info_resp.bp_info, : sizeof(struct cse_boot_partition_info)); > we can avoid this memcpy, with the change mentioned at line 59-60. Agreed, please see my earlier response. https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 128: return 1; > initialize = false at the beginning of this function. […] Please see my earlier response. https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 135: static uint8_t cse_init_bp_info(bool force_cse_init) : { : if (cse_bp_init == false || force_cse_init == true) { : if (!cse_update_boot_partition_info()) { : printk(BIOS_ERR, "Boot partition update fail\n"); : return 0; : } : cse_print_boot_partition_info(); : } : cse_bp_init = true; : return 1; : } > The only place force_cse_init is true is when you try to set_next_boot_partition. […] This function checks if it needs to update boot partition info or not. Also, updates the boot partition info based on it's input argument. https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 214: if (!cse_init_bp_info(false)) : return 0; > you can just check for the information is initialized or not, instead of forcing or not forcing the […] Please see my above response. -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Sep 2019 15:36:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 25 Sep '19

25 Sep '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#16). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs GET_BOOT_PARTITION_INFO - provides info on available partitions in the cse region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Also, made minor changes to group macro definitions of group ids, command ids and renamed macro definitions of hmrfpo commands. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 391 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/mainboard/google: Fix hatch variant script
by Edward O'Callaghan (Code Review) 25 Sep '19

25 Sep '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35553 ) Change subject: util/mainboard/google: Fix hatch variant script ...................................................................... util/mainboard/google: Fix hatch variant script The script had a couple of bugs: * It didn't create the required directory under variants/ * It was treating the wildcard as literal and so couldn't find variant files to copy. Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M util/mainboard/google/hatch/create_coreboot_variant.sh 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/35553/1 diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh index 32720ca..352db8d 100755 --- a/util/mainboard/google/hatch/create_coreboot_variant.sh +++ b/util/mainboard/google/hatch/create_coreboot_variant.sh @@ -53,7 +53,8 @@ git checkout -b "create_${variant}_${DATE}" # Copy the template tree to the target -cp -r "${SRC}/template/*" "variants/${variant}/" +mkdir "variants/${variant}/" +cp -vr "${SRC}/template"/* "variants/${variant}/" git add "variants/${variant}/" # Now add the new variant to Kconfig and Kconfig.name -- To view, visit https://review.coreboot.org/c/coreboot/+/35553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7 Gerrit-Change-Number: 35553 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/fsp_broadwell_de: fix flashconsole support for platform
by Matt DeVillier (Code Review) 25 Sep '19

25 Sep '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32880 Change subject: soc/fsp_broadwell_de: fix flashconsole support for platform ...................................................................... soc/fsp_broadwell_de: fix flashconsole support for platform CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert to using own spi implementation, and use CAR_GLOBAL as in early versions of CB:21107 Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/Makefile.inc A src/soc/intel/fsp_broadwell_de/spi.c 3 files changed, 607 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32880/1 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f..85e7249 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -12,12 +12,11 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SOUTHBRIDGE_INTEL_COMMON - select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET select PARALLEL_MP select SMP select IOAPIC + select SPI_FLASH select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 0a23170..4b2a24d 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -12,6 +12,9 @@ subdirs-y += fsp romstage-y += gpio.c +romstage-y += spi.c + +ramstage-y += spi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += northcluster.c diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c new file mode 100644 index 0000000..7eb3b7a --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2016 Siemens AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file is derived from the flashrom project. */ +#include <arch/early_variables.h> +#include <stdint.h> +#include <stdlib.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <spi_flash.h> +#include <spi-generic.h> + +typedef struct spi_slave ich_spi_slave; + +static int g_ichspi_lock CAR_GLOBAL = 0; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __packed ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned int databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller g_cntlr CAR_GLOBAL; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#define SPI_OFFSET_MASK 0x3ff + +static uint8_t readb_(const void *addr) +{ + uint8_t v = read8(addr); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, ((uint32_t) addr) & SPI_OFFSET_MASK); + } + return v; +} + +static uint16_t readw_(const void *addr) +{ + uint16_t v = read16(addr); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, ((uint32_t) addr) & SPI_OFFSET_MASK); + } + return v; +} + +static uint32_t readl_(const void *addr) +{ + uint32_t v = read32(addr); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, ((uint32_t) addr) & SPI_OFFSET_MASK); + } + return v; +} + +static void writeb_(uint8_t b, void *addr) +{ + write8(addr, b); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, ((uint32_t) addr) & SPI_OFFSET_MASK); + } +} + +static void writew_(uint16_t b, void *addr) +{ + write16(addr, b); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, ((uint32_t) addr) & SPI_OFFSET_MASK); + } +} + +static void writel_(uint32_t b, void *addr) +{ + write32(addr, b); + if (CONFIG(DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, ((uint32_t) addr) & SPI_OFFSET_MASK); + } +} + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr->bbar); +} + +void spi_init(void) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + uint8_t bios_cntl; + ich9_spi_regs *ich9_spi; + +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = pcidev_on_root(31, 0); +#endif + + rcba = pci_read_config32(dev, 0xf0); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->bbar = &ich9_spi->bbar; + cntlr->preop = &ich9_spi->preop; + ich_set_bbar(0); + + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = pci_read_config8(dev, 0xdc); + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } + + /* Fast read command is called with 5 bytes instead of 4 */ + if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + --trans->bytesout; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint16_t optypes; + uint8_t opmenu[cntlr->menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!car_get_var(g_ichspi_lock)) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr->optype); + return 0; + } + + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr->menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr->optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", + trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(uint16_t bitmask, int wait_til_set) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + int timeout = 40000; /* This will result in 400 ms */ + uint16_t status = 0; + + while (timeout--) { + status = readw_(cntlr->status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr->status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) +{ + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bytesout, + din, bytesin, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bytesout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bytesin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); + + spi_setup_type(&trans); + opcode_index = spi_setup_opcode(&trans); + if (opcode_index < 0) + return -1; + with_address = spi_setup_offset(&trans); + if (with_address < 0) + return -1; + + if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + writew_(trans.opcode, cntlr->preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr->preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* SPI addresses are 24 bit only */ + if (with_address) + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + + /* + * This is a 'no data' command (like Write Enable), its + * bytesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr->control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + goto spi_xfer_exit; + } + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr->databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr->databytes); + else + data_length = min(trans.bytesin, cntlr->databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr->data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr->databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr->control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr->data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + +spi_xfer_exit: + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr->preop); + + return 0; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); +} + +static const struct spi_ctrlr spi_ctrlr = { + .xfer_vector = xfer_vectors, + .max_xfer_size = member_size(ich9_spi_regs, fdata), +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/32880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Gerrit-Change-Number: 32880 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: mb/google/kukui: Add new build target 'Juniper'
by Hung-Te Lin (Code Review) 25 Sep '19

25 Sep '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35550 ) Change subject: mb/google/kukui: Add new build target 'Juniper' ...................................................................... mb/google/kukui: Add new build target 'Juniper' Add the configuration 'Juniper' for the new mainboard. BUG=b:137517228 TEST=make menuconfig; select 'juniper' and build Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35550/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 24a8e43..2828918 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -56,6 +56,7 @@ default "Kodama" if BOARD_GOOGLE_KODAMA default "Flapjack" if BOARD_GOOGLE_FLAPJACK default "Jacuzzi" if BOARD_GOOGLE_JACUZZI + default "Juniper" if BOARD_GOOGLE_JUNIPER config DRIVER_TPM_SPI_BUS hex @@ -77,4 +78,5 @@ default "KODAMA TEST 7122" if BOARD_GOOGLE_KODAMA default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK default "JACUZZI TEST 6792" if BOARD_GOOGLE_JACUZZI + default "JUNIPER TEST 4819" if BOARD_GOOGLE_JUNIPER endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 33049e3..c7772dd 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -19,3 +19,7 @@ config BOARD_GOOGLE_JACUZZI bool "-> Jacuzzi" select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_JUNIPER + bool "-> Juniper" + select BOARD_GOOGLE_KUKUI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/35550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Gerrit-Change-Number: 35550 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMET...
by Furquan Shaikh (Code Review) 25 Sep '19

25 Sep '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35563 ) Change subject: util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKE ...................................................................... util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKE Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig, utility to create a new variant does not need to do that anymore in Kconfig.name Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/mainboard/google/hatch/kconfig.py 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35563/1 diff --git a/util/mainboard/google/hatch/kconfig.py b/util/mainboard/google/hatch/kconfig.py index 8b54b75..ecc24ee 100755 --- a/util/mainboard/google/hatch/kconfig.py +++ b/util/mainboard/google/hatch/kconfig.py @@ -149,7 +149,6 @@ print('\tbool "-> ' + capitalized + '"', file=outfile) print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) - print('\tselect SOC_INTEL_COMETLAKE', file=outfile) if __name__ == '__main__': -- To view, visit https://review.coreboot.org/c/coreboot/+/35563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62 Gerrit-Change-Number: 35563 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to Kconfig
by Furquan Shaikh (Code Review) 25 Sep '19

25 Sep '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35562 ) Change subject: mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to Kconfig ...................................................................... mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to Kconfig All variants of hatch are using Comet Lake and so the selection can be done in Kconfig without requiring each variant to do the same. Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name 2 files changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/35562/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index c4c9146..d4cf83d 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -20,6 +20,7 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + select SOC_INTEL_COMETLAKE select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 01b6ead..fbc4c15 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -4,35 +4,29 @@ bool "-> Akemi" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE config BOARD_GOOGLE_DRATINI bool "-> Dratini" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 - select SOC_INTEL_COMETLAKE config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 - select SOC_INTEL_COMETLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/35562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Gerrit-Change-Number: 35562 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: Documentation/vendorcode: Add Eltan to vendor index
by Frans Hendriks (Code Review) 25 Sep '19

25 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35557 ) Change subject: Documentation/vendorcode: Add Eltan to vendor index ...................................................................... Documentation/vendorcode: Add Eltan to vendor index Eltan is missing in the vendor index. Documentation of the eltan vendorcode is availlabe already. Add eltan to vendor index. BUG=N/A TEST=N/A Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M Documentation/vendorcode/index.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35557/1 diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md index 3374eaf..ffa5ed5 100644 --- a/Documentation/vendorcode/index.md +++ b/Documentation/vendorcode/index.md @@ -5,3 +5,4 @@ ## Vendor - [Cavium](cavium/index.md) +- [Eltan](eltan/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/35557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146 Gerrit-Change-Number: 35557 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Patrick Rudolph (Code Review) 25 Sep '19

25 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (7 comments) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1244 PS4, Line 1244: * implementation specific.e.e.g, scenerios: no need for SoC comments in arch/x86. https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) no need for weak, code will be removed if not CONFIG(ACPI_LPIT) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1255 PS4, Line 1255: lpit_native->residency_counter.space_id = 0x7F; why is this "the" default for all platforms? https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1275 PS4, Line 1275: header->asl_compiler_revision = 0; header->asl_compiler_revision = asl_revision; https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1278 PS4, Line 1278: lpit->lpit_native.header.type = 0; already cleared by memset https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/include/arch/… File src/arch/x86/include/arch/acpi.h: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/include/arch/… PS4, Line 263: typedef struct acpi_lpi_state_flags { not endian safe https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/include/arch/… PS4, Line 309: } __packed acpi_table_lpit; doesn't follow existing naming scheme -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Sep 2019 11:32:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Rizwan Qureshi (Code Review) 25 Sep '19

25 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 15: (6 comments) https://review.coreboot.org/c/coreboot/+/35402/14//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35402/14//COMMIT_MSG@17 PS14, Line 17: definations definition https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 59: static struct cse_boot_partition_info cse_bp_info; : static bool cse_bp_init = false; Can we group them into one construct? something like struct bp_info { struct get_boot_partition_info_resp info_resp; bool initialized; }; static struct bp_info cse_bp_info; Then use the same in getting the response in receive function. if (!heci_send_receive(&info_req, sizeof(cse_bp_info.info_resp), &cse_bp_info.info_resp, &resp_size)) https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 125: memcpy((void *)&cse_bp_info, (void *)&info_resp.bp_info, : sizeof(struct cse_boot_partition_info)); we can avoid this memcpy, with the change mentioned at line 59-60. https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 128: return 1; initialize = false at the beginning of this function. just set the initialized to true here, if there are no errors. https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 135: static uint8_t cse_init_bp_info(bool force_cse_init) : { : if (cse_bp_init == false || force_cse_init == true) { : if (!cse_update_boot_partition_info()) { : printk(BIOS_ERR, "Boot partition update fail\n"); : return 0; : } : cse_print_boot_partition_info(); : } : cse_bp_init = true; : return 1; : } The only place force_cse_init is true is when you try to set_next_boot_partition. you could just initialize the cse_bp_info everytime you switch the partition. This function may be eliminated, if you insist on having it it could just check if the cse_bp_info initialized or not and take appropriate action. https://review.coreboot.org/c/coreboot/+/35402/14/src/soc/intel/common/bloc… PS14, Line 214: if (!cse_init_bp_info(false)) : return 0; you can just check for the information is initialized or not, instead of forcing or not forcing the update. -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Sep 2019 11:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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