coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Patrick Rudolph (Code Review) 29 Sep '19

29 Sep '19

Hello Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35680 to look at the new patch set (#2). Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... cpu/qemu-x86: Add x86_64 bootblock support Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M Makefile.inc M src/arch/x86/Kconfig M src/cpu/qemu-x86/cache_as_ram_bootblock.S A src/cpu/x86/64bit/entry64.inc A util/pgtblgen/Makefile.inc A util/pgtblgen/description.md A util/pgtblgen/pgtblgen.c 8 files changed, 274 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35680/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Support x86_64 exceptions
by build bot (Jenkins) (Code Review) 29 Sep '19

29 Sep '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 17: (2 comments) https://review.coreboot.org/c/coreboot/+/30117/17/src/arch/x86/include/arch… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/c/coreboot/+/30117/17/src/arch/x86/include/arch… PS17, Line 44: #define QUAD_DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/30117/17/src/arch/x86/include/arch… PS17, Line 50: #define QUAD_DOWNTO16(A) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 29 Sep 2019 10:38:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/boot: Call payload in protected mode
by Patrick Rudolph (Code Review) 29 Sep '19

29 Sep '19

Hello Krystian Hebel, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30118 to look at the new patch set (#17). Change subject: arch/x86/boot: Call payload in protected mode ...................................................................... arch/x86/boot: Call payload in protected mode * On ARCH_RAMSTAGE_X86_64 call the payload in protected mode. * Add a helper function to call arbitraty code in protected mode, similar to the real mode call handler. * Tested on qemu using SeaBios as payload. * Untested for anything else. * Doesn't affect existing x86_32 code. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/boot.c M src/arch/x86/c_start.S M src/include/program_loading.h 4 files changed, 184 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30118/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Support x86_64 exceptions
by Patrick Rudolph (Code Review) 29 Sep '19

29 Sep '19

Hello Krystian Hebel, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30117 to look at the new patch set (#17). Change subject: arch/x86: Support x86_64 exceptions ...................................................................... arch/x86: Support x86_64 exceptions * Tested on qemu using division by zero. • Doesn't affect existing x86_32 code. Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/exception.c M src/arch/x86/idt.S M src/arch/x86/include/arch/registers.h 4 files changed, 141 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/30117/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 29 Sep '19

29 Sep '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30500 to look at the new patch set (#13). Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... arch/x86/postcar: Add x86_64 support * Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Separate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Needs test on real hardware. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/Makefile.inc R src/arch/x86/exit_car_x86_32.S A src/arch/x86/exit_car_x86_64.S M src/arch/x86/gdt_init.S 5 files changed, 155 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30500/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/i945: Define p2peg for PCIe x16 slot
by Arthur Heymans (Code Review) 29 Sep '19

29 Sep '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35675 ) Change subject: intel/i945: Define p2peg for PCIe x16 slot ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35675/1/src/northbridge/intel/i945… File src/northbridge/intel/i945/early_init.c: https://review.coreboot.org/c/coreboot/+/35675/1/src/northbridge/intel/i945… PS1, Line 532: pci_devfn_t > Could be but, but hopefully is not required by style guide. ok -- To view, visit https://review.coreboot.org/c/coreboot/+/35675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Gerrit-Change-Number: 35675 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Sep 2019 07:21:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/i945: Define p2peg for PCIe x16 slot
by Kyösti Mälkki (Code Review) 29 Sep '19

29 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35675 ) Change subject: intel/i945: Define p2peg for PCIe x16 slot ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35675/1/src/northbridge/intel/i945… File src/northbridge/intel/i945/early_init.c: https://review.coreboot.org/c/coreboot/+/35675/1/src/northbridge/intel/i945… PS1, Line 532: pci_devfn_t > const? Could be but, but hopefully is not required by style guide. -- To view, visit https://review.coreboot.org/c/coreboot/+/35675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Gerrit-Change-Number: 35675 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Sep 2019 07:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/i945: Define p2peg for PCIe x16 slot
by Arthur Heymans (Code Review) 29 Sep '19

29 Sep '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35675 ) Change subject: intel/i945: Define p2peg for PCIe x16 slot ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/35675/1/src/northbridge/intel/i945… File src/northbridge/intel/i945/early_init.c: https://review.coreboot.org/c/coreboot/+/35675/1/src/northbridge/intel/i945… PS1, Line 532: pci_devfn_t const? -- To view, visit https://review.coreboot.org/c/coreboot/+/35675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Gerrit-Change-Number: 35675 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Sep 2019 06:54:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: getac/p470: Drop unused PCI secondary bus reset
by Arthur Heymans (Code Review) 29 Sep '19

29 Sep '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35674 ) Change subject: getac/p470: Drop unused PCI secondary bus reset ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I959cdc08d43fea28f8bbc649cd46bab5656d6ca8 Gerrit-Change-Number: 35674 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Sep 2019 06:52:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE
by Kyösti Mälkki (Code Review) 29 Sep '19

29 Sep '19

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35654 ) Change subject: amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE ...................................................................... amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/quadcore/quadcore_id.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/sr5650/cmn.h 6 files changed, 25 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 5b97232..3946b67 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -65,7 +65,7 @@ if (is_fam15h()) { enable_cc6 = 0; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) enable_cc6 = 1; #else diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 2c4d60d..7ec1bdb 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -42,7 +42,7 @@ uint32_t family; uint32_t model; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); #else f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); @@ -109,7 +109,7 @@ uint32_t f5x84; uint8_t core_count; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84); #else f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84); diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 96938b2..ad8d013 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1017,11 +1017,9 @@ struct acpi_rsdp; -#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(struct device *device); -#endif #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 3e8c2fb..23e9232 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,7 +21,7 @@ #include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h> -#ifndef __SIMPLE_DEVICE__ +#if !ENV_PCI_SIMPLE_DEVICE u32 Get_NB32(u32 dev, u32 reg) { return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 1fdbc16..52032e9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -69,7 +69,7 @@ return s3nv_region.region.offset; } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg) #else @@ -79,7 +79,7 @@ { if (is_fam15h()) { uint32_t dword; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -98,7 +98,7 @@ return pci_read_config32(dev, reg); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) #else @@ -108,7 +108,7 @@ { if (is_fam15h()) { uint32_t dword; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -127,7 +127,7 @@ pci_write_config32(dev, reg, value); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static uint32_t read_amd_dct_index_register(pci_devfn_t dev, uint32_t index_ctl_reg, uint32_t index) #else @@ -147,7 +147,7 @@ return dword; } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index) #else @@ -158,7 +158,7 @@ { if (is_fam15h()) { uint32_t dword; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index d70e7a9..9588105 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,7 +34,7 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) #else static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) @@ -44,7 +44,7 @@ return pci_read_config32(dev, index_reg + 0x4); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) #else @@ -56,7 +56,7 @@ pci_write_config32(dev, index_reg + 0x4, data); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) @@ -65,7 +65,7 @@ return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmisc_write_index(struct device *nb_dev, u32 index, @@ -75,7 +75,7 @@ nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -92,7 +92,7 @@ } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 htiu_read_index(struct device *nb_dev, u32 index) @@ -101,7 +101,7 @@ return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) @@ -110,7 +110,7 @@ nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) @@ -119,7 +119,7 @@ return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) @@ -128,7 +128,7 @@ nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -145,7 +145,7 @@ } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -162,7 +162,7 @@ } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) #else @@ -179,7 +179,7 @@ } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -196,7 +196,7 @@ } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, u32 val) #else -- To view, visit https://review.coreboot.org/c/coreboot/+/35654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Gerrit-Change-Number: 35654 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2019