coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

1 participants
1442 discussions

Change in coreboot[master]: util/chromeos: Indent code blocks instead of using ```
by Paul Menzel (Code Review) 19 Nov '19

19 Nov '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35729 ) Change subject: util/chromeos: Indent code blocks instead of using ``` ...................................................................... util/chromeos: Indent code blocks instead of using ``` This uses less lines, is the original Markdown syntax, and for short blocks bette readable. Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/chromeos/README.md 1 file changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35729/1 diff --git a/util/chromeos/README.md b/util/chromeos/README.md index 0b9a7d7..964c6c5 100644 --- a/util/chromeos/README.md +++ b/util/chromeos/README.md @@ -11,14 +11,13 @@ extracts the firmware images from the shell archive. To download all Chrome OS firmware images, run -``` -$ ./crosfirmware.sh -``` + + $ ./crosfirmware.sh + To download, e.g. the Panther firmware image, run -``` -$ ./crosfirmware.sh panther -``` + + $ ./crosfirmware.sh panther ## extract_blobs.sh @@ -33,12 +32,10 @@ compatible format. Usage: -``` -$ ./gen_test_hwid.sh BOARD_NAME -``` + + $ ./gen_test_hwid.sh BOARD_NAME Example: -``` -$ ./gen_test_hwid.sh Kukui -KUKUI TEST 9847 -``` + + $ ./gen_test_hwid.sh Kukui + KUKUI TEST 9847 -- To view, visit https://review.coreboot.org/c/coreboot/+/35729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9 Gerrit-Change-Number: 35729 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: Documentation: Reword Supermicro X10SLM+-F sentence
by Paul Menzel (Code Review) 19 Nov '19

19 Nov '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35486 ) Change subject: Documentation: Reword Supermicro X10SLM+-F sentence ...................................................................... Documentation: Reword Supermicro X10SLM+-F sentence Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/mainboard/supermicro/x10slm-f.md 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35486/1 diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 8a91c89..7abbbfd 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -87,8 +87,7 @@ This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400]. -This chip is an MX25L25635F, whose datasheet can be found -[here][MX25L25635F]. +This chip is an MX25L25635F ([datasheet](MX25L25635F). ### Removing the BMC functionality -- To view, visit https://review.coreboot.org/c/coreboot/+/35486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Gerrit-Change-Number: 35486 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: build system: Add various compiler flags that enable warnings on UB
by Patrick Georgi (Code Review) 18 Nov '19

18 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32814 Change subject: build system: Add various compiler flags that enable warnings on UB ...................................................................... build system: Add various compiler flags that enable warnings on UB Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32814/1 diff --git a/Makefile.inc b/Makefile.inc index 9860da1..f2e010c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -410,6 +410,8 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack +CFLAGS_common += -pedantic-errors -Wnull-dereference +CFLAGS_common += -Wno-aggressive-loop-optimizations -Wreturn-type # cf. commit f69a99db (coreboot: x86: enable gc-sections) CFLAGS_common += -Wno-unused-but-set-variable endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Gerrit-Change-Number: 32814 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 17 Nov '19

17 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32970 Change subject: [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK ...................................................................... [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK untested. Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc A src/soc/intel/baytrail/bootblock/Makefile.inc M src/soc/intel/baytrail/bootblock/bootblock.c R src/soc/intel/baytrail/bootblock/uart.c A src/soc/intel/baytrail/include/soc/bootblock.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c 11 files changed, 118 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32970/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 03ad31d..f71fc02 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -41,14 +41,12 @@ select POSTCAR_CONSOLE select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config MMCONF_BASE_ADDRESS hex @@ -94,6 +92,13 @@ bool "Enable MRC RMT training + debug prints" default n +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE @@ -132,6 +137,13 @@ help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6e6eb9c..e6a5704 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage +subdirs-y += bootblock subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -12,13 +13,16 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c +bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +verstage-y += tsc_freq.c romstage-y += spi.c postcar-y += spi.c ramstage-y += spi.c +verstage-y += spi.c smm-y += spi.c ramstage-y += chip.c ramstage-y += gfx.c @@ -30,6 +34,8 @@ ramstage-y += ramstage.c ramstage-y += gpio.c ramstage-y += cpu.c +bootblock-y += pmutil.c +verstage-y += pmutil.c romstage-y += pmutil.c ramstage-y += pmutil.c smm-y += pmutil.c diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc new file mode 100644 index 0000000..d093550 --- /dev/null +++ b/src/soc/intel/baytrail/bootblock/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += ../../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../../cpu/x86/early_reset.S +bootblock-y += bootblock.c +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d..d371a98 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -18,32 +18,56 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/iosf.h> -#include <cpu/intel/microcode/microcode.c> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/spi.h> +#include <soc/pmc.h> +#include <soc/bootblock.h> +#include <cpu/intel/car/bootblock.h> -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +static void program_base_addresses(void) { - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); } -static void enable_rom_caching(void) +static void spi_init(void) { - msr_t msr; + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); } static void setup_mmconfig(void) @@ -64,12 +88,22 @@ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +void bootblock_early_cpu_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + program_base_addresses(); + tco_disable(); + byt_config_com1_and_enable(); + spi_init(); } diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/bootblock/uart.c similarity index 96% rename from src/soc/intel/baytrail/romstage/uart.c rename to src/soc/intel/baytrail/bootblock/uart.c index f9f2fe4..e5788cb 100644 --- a/src/soc/intel/baytrail/romstage/uart.c +++ b/src/soc/intel/baytrail/bootblock/uart.c @@ -18,7 +18,7 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/bootblock.h> void byt_config_com1_and_enable(void) { diff --git a/src/soc/intel/baytrail/include/soc/bootblock.h b/src/soc/intel/baytrail/include/soc/bootblock.h new file mode 100644 index 0000000..65ba6bb --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/bootblock.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BAYTRAIL_BOOTBLOCK_H_ +#define _BAYTRAIL_BOOTBLOCK_H_ + +#if CONFIG(ENABLE_BUILTIN_COM1) +void byt_config_com1_and_enable(void); +#else +static inline void byt_config_com1_and_enable(void) { } +#endif + + +#endif /* _BAYTRAIL_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 7730893..248112f 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -27,15 +27,8 @@ void mainboard_pre_raminit(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); -void tco_disable(void); void punit_init(void); void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); -#if CONFIG(ENABLE_BUILTIN_COM1) -void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif - #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b740a03..1fa22f6 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -369,7 +369,12 @@ { uint32_t gen_pmcon1; int rtc_fail; + +#if !(ENV_BOOTBLOCK || ENV_VERSTAGE) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); +#else + struct chipset_power_state *ps = NULL; +#endif if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 8f009bd..afab9c0 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,9 +1,7 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c romstage-y += early_spi.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 596ed11..9fc3538 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -27,15 +27,6 @@ #include <soc/romstage.h> #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2a530b4..a9b6566 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -50,51 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -171,16 +126,8 @@ struct chipset_power_state *ps; int prev_sleep_state; - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - console_init(); - spi_init(); - set_max_freq(); punit_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7 Gerrit-Change-Number: 32970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
by Arthur Heymans (Code Review) 17 Nov '19

17 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35722 ) Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ...................................................................... [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR Totest: Does it still boot? Are romstage timestamps affected (does caching work)? Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/romstage.c A src/cpu/intel/car/set_mtrr.S A src/cpu/intel/car/set_mtrr.h M src/cpu/intel/socket_LGA775/Makefile.inc 4 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 547b121..eee3412 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -15,12 +15,17 @@ #include <arch/romstage.h> #include <bootblock_common.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <arch/symbols.h> #include <commonlib/helpers.h> #include <program_loading.h> #include <timestamp.h> +#include <symbols.h> +#include <lib.h> +#include "../car/set_mtrr.h" /* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ @@ -51,6 +56,15 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + u32 program_size = _eprogram - _program; + program_size = 1 << log2_ceil(program_size); + msr_t mtrr_phys_mask; + mtrr_phys_mask.lo = ~(program_size - 1) | MTRR_PHYS_MASK_VALID; + mtrr_phys_mask.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + + set_mtrr_asm(1, ALIGN_DOWN((u32)_program, program_size) | MTRR_TYPE_WRPROT, + mtrr_phys_mask); + mainboard_romstage_entry(); /* Check the stack. */ diff --git a/src/cpu/intel/car/set_mtrr.S b/src/cpu/intel/car/set_mtrr.S new file mode 100644 index 0000000..de8a242 --- /dev/null +++ b/src/cpu/intel/car/set_mtrr.S @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.global set_mtrr_asm + /* ARG0: MTRR_NUM to use (1 dword) + * ARG1: BASE_ARG (1 dword) + * ARG2: MASK_ARG (2 dwords) + * All arguments assume sanity from the caller + */ +.code32 +set_mtrr_asm: + push %ebp + movl %esp, %ebp + push %edi + push %esi + push %ebx + movl (%ebp), %ecx // MTRR_NUM + movl 4(%ebp), %edi // BASE + movl 8(%ebp), %esi // MASK_LO + movl 12(%ebp), %ebx // MASK_HI + + /* Enable Cache-as-RAM mode by disabling cache. + Assume fetching from stack does not work */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + imul $2, %ecx, %ecx + addl $MTRR_PHYS_BASE(0), %ecx + + // MTRR_PHYS_BASE + xorl %edx, %edx + movl %edi, %eax + wrmsr + + // MTRR_PHYS_MASK + addl $1, %ecx + movl %esi, %eax + movl %ebx, %edx + wrmsr + + /* Enable cache again. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + movl %eax, %cr0 + + /* restore regs */ + pop %ebx + pop %esi + pop %edi + pop %ebp + ret diff --git a/src/cpu/intel/car/set_mtrr.h b/src/cpu/intel/car/set_mtrr.h new file mode 100644 index 0000000..41bc430 --- /dev/null +++ b/src/cpu/intel/car/set_mtrr.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SET_MTRR_H +#define _SET_MTRR_H + +#include <cpu/x86/msr.h> + +void set_mtrr_asm(int num_mtrr, u32 phys_base, msr_t phys_mask); + +#endif diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c..fd0d642 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,6 +14,7 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +romstage-y += ../car/set_mtrr.S postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Gerrit-Change-Number: 35722 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: vboot: Unify options to force display init
by Nico Huber (Code Review) 16 Nov '19

16 Nov '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34622 ) Change subject: vboot: Unify options to force display init ...................................................................... vboot: Unify options to force display init We used to let implementations for display init that honor display_init_required() explicitly declare that by selecting VBOOT_MUST_REQUEST_DISPLAY. However, to allow the user to force display initialization, it's simpler to invert this Kconfig option. The new Kconfig VBOOT_FORCE_DISPLAY_INIT has the same effect as ALWAYS_RUN_OPROM for VGA OpRoms. Thus, we can also remove the latter. The inversion adds a little Kconfig noise. However, this can be reduced in the future by honoring display_init_required() where it should be. Change-Id: I52288b0d5f33cd11d84e609e039dc4ea16ff7bdf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/pci_device.c M src/drivers/aspeed/ast2050/Kconfig M src/drivers/emulation/qemu/Kconfig M src/drivers/xgi/z9s/Kconfig M src/lib/bootmode.c M src/mainboard/google/daisy/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/oak/Kconfig M src/mainboard/google/peach_pit/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/x4x/Kconfig M src/security/vboot/Kconfig M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/Kconfig 33 files changed, 51 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34622/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2..d1037da 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -139,13 +139,6 @@ are needed for the kernel's display driver to know how a piece of hardware is configured to be used. -config ALWAYS_RUN_OPROM - def_bool n - depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM - help - Always uncondtionally run the option regardless of other - policies. - config ON_DEVICE_ROM_LOAD bool "Load Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..98ec6fc 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -707,11 +707,6 @@ if (should_run >= 0) return should_run; - if (CONFIG(ALWAYS_RUN_OPROM)) { - should_run = 1; - return should_run; - } - /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. */ diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 337b181..137abd7 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -3,3 +3,10 @@ select DRIVERS_ASPEED_AST_COMMON select HAVE_VGA_TEXT_FRAMEBUFFER select MAINBOARD_HAS_NATIVE_VGA_INIT + +if DRIVERS_ASPEED_AST2050 + +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_DO_NATIVE_VGA_INIT + +endif diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 58daaa44..5ab487f 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -13,14 +13,19 @@ vga (cirrus) is *not* supported, so you have to pick another one explicitly via 'qemu -vga $card'. +if DRIVERS_EMULATION_QEMU_BOCHS + config DRIVERS_EMULATION_QEMU_BOCHS_XRES int "bochs vga xres" default 800 depends on LINEAR_FRAMEBUFFER - depends on DRIVERS_EMULATION_QEMU_BOCHS config DRIVERS_EMULATION_QEMU_BOCHS_YRES int "bochs vga yres" default 600 depends on LINEAR_FRAMEBUFFER - depends on DRIVERS_EMULATION_QEMU_BOCHS + +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT + +endif diff --git a/src/drivers/xgi/z9s/Kconfig b/src/drivers/xgi/z9s/Kconfig index b8000c1..98ad1a1 100644 --- a/src/drivers/xgi/z9s/Kconfig +++ b/src/drivers/xgi/z9s/Kconfig @@ -1,3 +1,10 @@ config DRIVERS_XGI_Z9S bool select DRIVERS_XGI_Z79_COMMON + +if DRIVERS_XGI_Z9S + +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_DO_NATIVE_VGA_INIT + +endif diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 2465966..69ac520 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -35,10 +35,6 @@ { /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { - /* Must always select MUST_REQUEST_DISPLAY when using this - function. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) - dead_code(); return vboot_get_working_data()->flags & VBOOT_WD_FLAG_DISPLAY_INIT; } diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 55e0978..b1e8bd8 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -32,6 +32,7 @@ select MAINBOARD_HAS_TPM1 config VBOOT + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_VBNV_EC config MAINBOARD_DIR diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index b675f33..7437edc 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -17,7 +17,6 @@ bool select SOC_AMD_STONEYRIDGE_FT4 select ALWAYS_LOAD_OPROM - select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -101,6 +100,7 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_LID_SWITCH config VBOOT_VBNV_OFFSET diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index c383fa4..99d206c 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -46,6 +46,7 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_VBNV_FLASH config MAINBOARD_DIR diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 75f0f0a..6dc414f 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -30,6 +30,7 @@ select MISSING_BOARD_RESET config VBOOT + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_VBNV_EC config MAINBOARD_DIR diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index c3d2482..d3b7a9b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -51,4 +51,7 @@ hex default 0x100000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 3678cb8..9937e99 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -44,7 +44,7 @@ and back to the RW region after the binary is done. config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK config VGA_BIOS_ID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index b151e8f..4a7b2a8 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -90,4 +90,7 @@ hex default 0x100000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_DO_NATIVE_VGA_INIT + endif diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 02b6e80..2b3b2a1 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -54,4 +54,7 @@ hex default 0x10000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 37959dd..bf5cafa 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -50,4 +50,7 @@ hex default 0x80000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 53725ca..d7810c8 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -26,6 +26,7 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT select VBOOT_STARTS_IN_ROMSTAGE config USE_NATIVE_RAMINIT diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index ce43936..703e2133 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -51,4 +51,7 @@ hex default 0x100000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea1f738..7c06ce5 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -154,15 +154,15 @@ reboots caused after vboot verification is run. e.g. reboots caused by FSP components on Intel platforms. -config VBOOT_MUST_REQUEST_DISPLAY - bool - default y if VGA_ROM_RUN - default n +config VBOOT_FORCE_DISPLAY_INIT + bool "Force display initialization" + default y if !CHROMEOS help - Set this option to indicate to vboot that this platform will skip its - display initialization on a normal (non-recovery, non-developer) boot. - Unless display is specifically requested, the video option ROM is not - loaded, and any other native display initialization code is not run. + Set this option to indicate to vboot that display initialization shall + always be performed, even on a normal (non-recovery, non-developer) + boot. Without this option, unless display is specifically requested, + the video option ROM is not loaded, and any other native display + initialization code is not run. config VBOOT_HAS_REC_HASH_SPACE bool diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2468f5f..165facc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -359,7 +359,7 @@ ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; /* Mainboard/SoC always initializes display. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + if (CONFIG(VBOOT_FORCE_DISPLAY_INIT)) ctx.flags |= VB2_CONTEXT_DISPLAY_INIT; /* Do early init (set up secdata and NVRAM, load GBB) */ diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cf3d244..796d406 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -117,7 +117,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4b816a2..2a576ce 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -42,7 +42,6 @@ select CPU_HAS_L2_ENABLE_MSR config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7887156..6afaf9b 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -63,7 +63,6 @@ default 0x8000 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE config MMCONF_BASE_ADDRESS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bf6b78c..bfe9519 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -81,7 +81,6 @@ and back to the RW region after the binary is done. config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK config MMCONF_BASE_ADDRESS diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..77f589e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -244,7 +244,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 99000bb..e43feb1 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -156,7 +156,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..e253596 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -108,7 +108,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 6476d42..958d41f 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -14,7 +14,6 @@ if SOC_MEDIATEK_MT8173 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index c60cdea..dd710a8 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -12,7 +12,6 @@ if SOC_MEDIATEK_MT8183 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index c962aea..cc06486 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -16,7 +16,6 @@ if SOC_NVIDIA_TEGRA124 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 0e1efd7..1c99bd6 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -16,7 +16,6 @@ config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index dbe025e..e2eadbb 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -15,7 +15,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK config SDM845_QSPI diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3aebab9..01c3f95 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -33,7 +33,6 @@ if SOC_ROCKCHIP_RK3288 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 7e3c44b..0424664 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -17,7 +17,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK config PMIC_BUS -- To view, visit https://review.coreboot.org/c/coreboot/+/34622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52288b0d5f33cd11d84e609e039dc4ea16ff7bdf Gerrit-Change-Number: 34622 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: mainboard/facebook/fbg1701: Add IFD and ME binary
by Frans Hendriks (Code Review) 15 Nov '19

15 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34448 ) Change subject: mainboard/facebook/fbg1701: Add IFD and ME binary ...................................................................... mainboard/facebook/fbg1701: Add IFD and ME binary Use IFD and ME binary to generate complete SPI image BUG=N/A TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701 Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34448/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 95d8f6c..dce315e 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -19,6 +19,8 @@ def_bool y select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES + select HAVE_IFD_BIN + select HAVE_ME_BIN select HAVE_OPTION_TABLE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 @@ -94,4 +96,12 @@ hex "C Bootblock Size" default 0x4000 +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" + endif # BOARD_FACEBOOK_FBG1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/34448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db Gerrit-Change-Number: 34448 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME
by Frans Hendriks (Code Review) 15 Nov '19

15 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34442 ) Change subject: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME ...................................................................... 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME Upgrade to blobs version with descriptor and Intel ME binary BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34442/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index d7600dd..c7dc4f2 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc +Subproject commit c7dc4f25229fd3c022afdb410264b02f292ddca6 -- To view, visit https://review.coreboot.org/c/coreboot/+/34442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Gerrit-Change-Number: 34442 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489 Change subject: [WIP] soc/amd/common: Use static allocation for params ...................................................................... [WIP] soc/amd/common: Use static allocation for params Lifetime of the structure is the duration of call to AGESA. There is no need to allocate and release these from AGESA's internal heap for every single call. Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 821535d..e769a45 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -410,6 +410,26 @@ } +union AMD_MAX_ALLOC_PARAMS { + AMD_INTERFACE_PARAMS p1; + AMD_RESET_PARAMS p2; + AMD_EARLY_PARAMS p3; + AMD_POST_PARAMS p4; + AMD_RESUME_PARAMS p5; + AMD_ENV_PARAMS p6; + AMD_MID_PARAMS p7; + AMD_LATE_PARAMS p8; +#if 1 + AMD_RTB_PARAMS p9; +#else + AMD_S3SAVE_PARAMS p10; +#endif + AMD_S3LATE_PARAMS p11; + AMD_S3FINAL_PARAMS p12; +}; + +static union AMD_MAX_ALLOC_PARAMS sp; + AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) { AGESA_STATUS status = AGESA_UNSUPPORTED; @@ -417,19 +437,9 @@ AMD_CONFIG_PARAMS *StdHeader = &template; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; - union { - AMD_RESET_PARAMS ResetParams; - AMD_S3LATE_PARAMS S3LateParams; - AMD_S3FINAL_PARAMS S3FinalParams; - } sp; - if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || - (func == AMD_S3FINAL_RESTORE)) { - memset(&sp, 0, sizeof(sp)); - amd_create_struct(aip, func, &sp, sizeof(sp)); - } else { - amd_create_struct(aip, func, NULL, 0); - } + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); StdHeader = aip->NewStructPtr; StdHeader->Func = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/31489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Gerrit-Change-Number: 31489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: cpu/x86: Move some PARALLEL_MP prototypes
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34152 ) Change subject: cpu/x86: Move some PARALLEL_MP prototypes ...................................................................... cpu/x86: Move some PARALLEL_MP prototypes The implementations live inside platform directories, but the function signatures must match those defined by PARALLEL_MP implementation. Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/smm/gen1/smi.h M src/include/cpu/x86/mp.h M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/skylake/include/soc/smm.h 8 files changed, 7 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34152/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cd8d5cb..2c52caf 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -160,13 +160,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Determine if HyperThreading is disabled. The variable is not valid until diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 3d5149a..4c80230 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -24,11 +24,4 @@ bool cpu_has_alternative_smrr(void); /* parallel MP helper functions */ -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); void southbridge_smm_clear_state(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_relocate(void); -void smm_lock(void); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index c04252e..05f2471 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -154,4 +154,11 @@ /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +/* Parallel MP helper functions. */ +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_initialize(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); +void smm_relocate(void); +void smm_lock(void); + #endif /* _X86_MP_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index d3e1cdd..fe38dc9 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -53,13 +53,6 @@ return CONFIG_SMM_TSEG_SIZE; } -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f..5cf7407 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,12 +50,5 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 72aa7fa..a3400ff 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -54,13 +54,6 @@ return CONFIG_SMM_TSEG_SIZE; } -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593..9777599 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,12 +49,5 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e976..4dfa627 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,12 +48,5 @@ int smm_save_state_in_msrs; }; -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2 Gerrit-Change-Number: 34152 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2019