coreboot-gerrit September 2019

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Change in ...coreboot[master]: soc/intel/broadwell: Use common SB RTC code
by Arthur Heymans (Code Review) 10 Nov '19

10 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33202 Change subject: soc/intel/broadwell: Use common SB RTC code ...................................................................... soc/intel/broadwell: Use common SB RTC code Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pmutil.c 2 files changed, 1 insertion(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33202/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 89a3c4c..deb5ef3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -22,6 +22,7 @@ select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 322e96f..00db615 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -451,32 +451,6 @@ return sci_irq; } -int rtc_failure(void) -{ - u8 reg8; - int rtc_failed; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_LPC; -#else - struct device *dev = PCH_DEV_LPC; -#endif - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - } - - return !!rtc_failed; -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} - int vboot_platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/33202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6 Gerrit-Change-Number: 33202 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: sb/intel/common: Make linking rtc.c conditional
by Arthur Heymans (Code Review) 10 Nov '19

10 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33201 Change subject: sb/intel/common: Make linking rtc.c conditional ...................................................................... sb/intel/common: Make linking rtc.c conditional Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 13 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33201/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index d81ab8a..89a3c4c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,6 +20,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER + select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG select IOAPIC diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f..f8c54ca 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -15,6 +15,7 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select PARALLEL_MP select SMP select IOAPIC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..c0d93c9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -30,6 +30,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 42717b0..6189f2f 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -6,6 +6,10 @@ bool select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_RTC + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON + config SOUTHBRIDGE_INTEL_COMMON_PMCLIB def_bool n depends on SOUTHBRIDGE_INTEL_COMMON diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index ac2fd8e..c3523c9 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -66,6 +66,6 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c -$(eval $(call add_to_all_stages,y,rtc.c)) +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC),rtc.c)) endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 4526cb3..8b9a786 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -32,6 +32,7 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_RTC config EHCI_BAR hex diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 6552099..1d984a2 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,6 +2,7 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RTC bool config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 12640b3..cb2bb7a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,6 +22,7 @@ select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d6e938..a6f8d90 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -31,6 +31,7 @@ select INTEL_HAS_TOP_SWAP select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select SOUTHBRIDGE_INTEL_COMMON_RTC if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 5edb8a1..3e53b9d 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b423eca..bf35a6a 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -21,6 +21,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 85c8979..60da867 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -33,6 +33,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 67e20be..2540d8a 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -27,6 +27,7 @@ select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB + select SOUTHBRIDGE_INTEL_COMMON_RTC select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/33201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Gerrit-Change-Number: 33201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: lockdown: lock global reset in skylake, cannonlake, icelake
by Michael Niewöhner (Code Review) 09 Nov '19

09 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35451 ) Change subject: lockdown: lock global reset in skylake, cannonlake, icelake ...................................................................... lockdown: lock global reset in skylake, cannonlake, icelake There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one is actually calling the code. Add the missing calls to skl/cnl/icl. Change-Id: I7c16888bbaa9ddac3adbf8a28f56dd745dd97bba Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/lockdown.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/lockdown.c 6 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35451/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a3252c2..a0294e0 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -188,6 +188,9 @@ */ soc_config_acpibase(); + /* Clear global reset promotion bit */ + pmc_global_reset_enable(0); + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index e2fcc3a..ab4f962 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -54,12 +54,22 @@ write8(pmcbase + GEN_PMCON_B, reg8); } +static void pmc_lock_global_reset(void) +{ + /* Disable global reset, just in case */ + pmc_global_reset_enable(0); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_lock(); +} + static void pmc_lockdown_cfg(int chipset_lockdown) { /* PMSYNC */ pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Lock global reset */ + pmc_lock_global_reset(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index aefcaa5..dabc8e6 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -163,6 +163,9 @@ */ soc_config_acpibase(); + /* Clear global reset promotion bit */ + pmc_global_reset_enable(0); + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index 8fa5e15..99302c3 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -54,12 +54,22 @@ write8(pmcbase + GEN_PMCON_B, reg8); } +static void pmc_lock_global_reset(void) +{ + /* Disable global reset, just in case */ + pmc_global_reset_enable(0); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_lock(); +} + static void pmc_lockdown_cfg(int chipset_lockdown) { /* PMSYNC */ pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Lock global reset */ + pmc_lock_global_reset(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..d4c5404 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -164,6 +164,9 @@ */ soc_config_pwrmbase(); + /* Clear global reset promotion bit */ + pmc_global_reset_enable(0); + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 864cefe..89221cb 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -28,6 +28,14 @@ } } +static void pmc_lock_global_reset(void) +{ + /* Disable global reset, just in case */ + pmc_global_reset_enable(0); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_lock(); +} + static void pmc_lockdown_config(void) { uint8_t *pmcbase; @@ -38,6 +46,9 @@ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); pmsyncreg |= PMSYNC_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + + /* Lock global reset */ + pmc_lock_global_reset(); } void soc_lockdown_config(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/35451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c16888bbaa9ddac3adbf8a28f56dd745dd97bba Gerrit-Change-Number: 35451 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

6 64

Change in ...coreboot[master]: [WIP]mb/asus/p5ql-em: Add mainboard
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31323 Change subject: [WIP]mb/asus/p5ql-em: Add mainboard ...................................................................... [WIP]mb/asus/p5ql-em: Add mainboard Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 1067MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure macaddress in Kconfig) - PEG slot Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI TODO: - BSEL superio pins Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asus/p5ql-em/Kconfig A src/mainboard/asus/p5ql-em/Kconfig.name A src/mainboard/asus/p5ql-em/Makefile.inc A src/mainboard/asus/p5ql-em/acpi/ec.asl A src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl A src/mainboard/asus/p5ql-em/acpi/platform.asl A src/mainboard/asus/p5ql-em/acpi/superio.asl A src/mainboard/asus/p5ql-em/acpi_tables.c A src/mainboard/asus/p5ql-em/board_info.txt A src/mainboard/asus/p5ql-em/cmos.default A src/mainboard/asus/p5ql-em/cmos.layout A src/mainboard/asus/p5ql-em/cstates.c A src/mainboard/asus/p5ql-em/data.vbt A src/mainboard/asus/p5ql-em/devicetree.cb A src/mainboard/asus/p5ql-em/dsdt.asl A src/mainboard/asus/p5ql-em/gma-mainboard.ads A src/mainboard/asus/p5ql-em/gpio.c A src/mainboard/asus/p5ql-em/hda_verb.c A src/mainboard/asus/p5ql-em/romstage.c 19 files changed, 811 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31323/1 diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig new file mode 100644 index 0000000..07af627 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QL_EM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default "asus/p5ql-em" + +config MAINBOARD_PART_NUMBER + string + default "P5QL EM" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5QL_EM diff --git a/src/mainboard/asus/p5ql-em/Kconfig.name b/src/mainboard/asus/p5ql-em/Kconfig.name new file mode 100644 index 0000000..92ead65 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5QL_EM + bool "P5QL EM" diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc new file mode 100644 index 0000000..6b3d94a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -0,0 +1,17 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-y += cstates.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..861561a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5ql-em/acpi/platform.asl b/src/mainboard/asus/p5ql-em/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5ql-em/acpi/superio.asl b/src/mainboard/asus/p5ql-em/acpi/superio.asl new file mode 100644 index 0000000..8f414f5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/superio.asl @@ -0,0 +1 @@ +/* TODO */ diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c new file mode 100644 index 0000000..d609a0e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5ql-em/board_info.txt b/src/mainboard/asus/p5ql-em/board_info.txt new file mode 100644 index 0000000..42d4812 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QC/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5ql-em/cmos.default b/src/mainboard/asus/p5ql-em/cmos.default new file mode 100644 index 0000000..ad822d5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout new file mode 100644 index 0000000..09ba5c5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -0,0 +1,104 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#436 548 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c new file mode 100644 index 0000000..aa7214d --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801jx/i82801jx.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5ql-em/data.vbt b/src/mainboard/asus/p5ql-em/data.vbt new file mode 100644 index 0000000..5dd1803 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/data.vbt Binary files differ diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb new file mode 100644 index 0000000..e13d59b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -0,0 +1,169 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on # Host Bridge + subsystemid 0x1043 0x8336 + end + device pci 1.0 on # PEG + subsystemid 0x1043 0x8336 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1043 0x8336 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1043 0x8336 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + device pci 19.0 off end # GBE + device pci 1a.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1b.0 on # Audio + subsystemid 0x1043 0x82fe + end + device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 on # PCIe 4 1394 controller + device pci 0.0 on + subsystemid 0x1043 0x8313 + end + end + device pci 1c.4 on # PCIe 5 Marvell IDE + device pci 0.0 on + subsystemid 0x1043 0x82a2 + end + end + device pci 1c.5 on # PCIe 6 Realtek LAN + device pci 0.0 on + subsystemid 0x1043 0x82c6 + end + end + device pci 1d.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1043 0x82d4 + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + # global + irq 0x2c = 0x92 + #floppy + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + drq 0x74 = 0x02 + end + device pnp 2e.1 on # Parallel port + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xf0 = 0xf3 + irq 0xf1 = 0x0c + end + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0x06 + irq 0xf5 = 0x06 + end + device pnp 2e.309 on # GPIO5 + irq 0xe0 = 0xdf + irq 0xf3 = 0x09 # RSVD SUSLED settings + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c off end # PECI, SST + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1043 0x82d4 + end + device pci 1f.3 on # SMbus + subsystemid 0x1043 0x82d4 + end + device pci 1f.4 off end + device pci 1f.5 on # IDE + subsystemid 0x1043 0x82d4 + end + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl new file mode 100644 index 0000000..d7ce26e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801jx/i82801jx.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads new file mode 100644 index 0000000..43a7d89 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c new file mode 100644 index 0000000..7bc8b9b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c new file mode 100644 index 0000000..9e54df6 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x104382fe, // Subsystem ID + 13, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c new file mode 100644 index 0000000..da822ac --- /dev/null +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> +#include <northbridge/intel/x4x/iomap.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich10_enable_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + /* HW EC */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); + /* TODO: FSB BSEL pins... */ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups + const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + /* Set southbridge and Super I/O GPIOs. */ + ich10_enable_lpc(); + mb_gpio_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + sdram_initialize(boot_path, spd_addrmap); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Gerrit-Change-Number: 31323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 40

Change in coreboot[master]: configs/config.facebookfbg1710: Add config file
by Frans Hendriks (Code Review) 08 Nov '19

08 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34343 ) Change subject: configs/config.facebookfbg1710: Add config file ...................................................................... configs/config.facebookfbg1710: Add config file BUG=N/A TEST=booting Embedded Linux 4.20 kernel on Facebook FBG1701 Change-Id: Ia2cb3bb873b2d5e7e9031e5b249d86605d8e0945 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A configs/config.facebookfbg1710 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/34343/1 diff --git a/configs/config.facebookfbg1710 b/configs/config.facebookfbg1710 new file mode 100644 index 0000000..be2e6d8 --- /dev/null +++ b/configs/config.facebookfbg1710 @@ -0,0 +1,10 @@ +CONFIG_VENDOR_FACEBOOK=y +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000 +CONFIG_ONBOARD_SAMSUNG_MEM=y +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 +CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC=0xfffe9000 +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_RUN_FSP_GOP=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_PAYLOAD_LINUX=y -- To view, visit https://review.coreboot.org/c/coreboot/+/34343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2cb3bb873b2d5e7e9031e5b249d86605d8e0945 Gerrit-Change-Number: 34343 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: Rangeley: Fix incorrect BCLK
by Name of user not set (Code Review) 07 Nov '19

07 Nov '19

hannah.williams(a)dell.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35348 ) Change subject: Rangeley: Fix incorrect BCLK ...................................................................... Rangeley: Fix incorrect BCLK Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR PSB_CLOCK_STS[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Signed-off-by: Hannah Williams <hannah.williams(a)dell.com> Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f --- M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/model_406dx.h 2 files changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35348/1 diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 6672eab..d6177b6 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -154,6 +154,33 @@ return (int)power; } +static int get_core_frequency_mhz(int ratio) +{ + msr_t msr; + unsigned int cpu_bclk_hz[] = { + 83333333, + 100000000, + 133333333, + 116666666 + }; + int core_freq; + int index; + + /* Get BCLK - different SKUs can have different BCLK */ + msr = rdmsr(MSR_PSB_CLOCK_STS); + index = msr.lo & CPU_BCLK_MASK; + if (index >= ARRAY_SIZE(cpu_bclk_hz)) + index = 0; + + printk(BIOS_DEBUG,"MSR_PSB_CLOCK_STS %x:%x BCLK:%dHz ratio:%d\n", + msr.hi, msr.lo, cpu_bclk_hz[index], ratio); + core_freq = (cpu_bclk_hz[index] * ratio) / 1000000; + if ((cpu_bclk_hz[index] * ratio) % 1000000 > 500000) + core_freq++; + printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq); + return core_freq; +} + static void generate_P_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; @@ -177,7 +204,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * RANGELEY_BCLK; + clock_max = get_core_frequency_mhz(ratio_max); /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -240,7 +267,7 @@ /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * RANGELEY_BCLK; + clock = get_core_frequency_mhz(ratio); acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 53a77a9..dcfe914 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -15,8 +15,6 @@ #ifndef _CPU_INTEL_MODEL_406DX_H #define _CPU_INTEL_MODEL_406DX_H -/* Rangeley bus clock is fixed at 100MHz */ -#define RANGELEY_BCLK 100 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 @@ -27,6 +25,8 @@ #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_PSB_CLOCK_STS 0xcd +#define CPU_BCLK_MASK 0x3 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Gerrit-Change-Number: 35348 Gerrit-PatchSet: 1 Gerrit-Owner: hannah.williams(a)dell.com Gerrit-MessageType: newchange

8 28

Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775 Change subject: cpu/intel/car/core2: Update microcode in CAR setup ...................................................................... cpu/intel/car/core2: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S 1 file changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..4fb8c66 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -111,6 +111,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -131,15 +142,17 @@ invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif +cache_xip: post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to set final MTRRs for speeding up XIP. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -165,8 +178,16 @@ /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Gerrit-Change-Number: 30775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: arch/x86: Create preprocessed __ROMCC__ bootblock source
by Kyösti Mälkki (Code Review) 06 Nov '19

06 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35602 ) Change subject: arch/x86: Create preprocessed __ROMCC__ bootblock source ...................................................................... arch/x86: Create preprocessed __ROMCC__ bootblock source Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35602/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 612424d..055911c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -163,6 +163,8 @@ @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d + $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ + $< > $(objgenerated)/bootblock_romcc.c $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ # bootblock.ld is part of $(bootblock-objs) -- To view, visit https://review.coreboot.org/c/coreboot/+/35602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Gerrit-Change-Number: 35602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/emulation/qemu: Add VBOOT support
by Patrick Rudolph (Code Review) 06 Nov '19

06 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35400 ) Change subject: mb/emulation/qemu: Add VBOOT support ...................................................................... mb/emulation/qemu: Add VBOOT support Add VBOOT support for testing purposes. Add a 16 MiB FMAP containing RO + RW_A. Tested on qemu. Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/cmos.layout A src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/cmos.layout A src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd 6 files changed, 81 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35400/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c5e325..4074fef 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,6 +12,22 @@ select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + + +config VBOOT_SLOTS_RW_A + default y + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_VBNV_OFFSET + hex + default 0x2c config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index b238a37..247a6a0 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -7,6 +7,10 @@ 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd new file mode 100644 index 0000000..aa081b2 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO 0x7ff000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS)@0x20000 0x7df000 + } + } +} diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index bfa38ed..811630c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,6 +11,21 @@ select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2c config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index b238a37..247a6a0 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -7,6 +7,10 @@ 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd new file mode 100644 index 0000000..aa081b2 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO 0x7ff000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS)@0x20000 0x7df000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Gerrit-Change-Number: 35400 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mp_init: Wait longer with serial enabled
by Patrick Rudolph (Code Review) 05 Nov '19

05 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34570 ) Change subject: cpu/x86/mp_init: Wait longer with serial enabled ...................................................................... cpu/x86/mp_init: Wait longer with serial enabled In case of slow serial wait longer for MP init to pickup jobs. This fixes a crash observed on KBL with 8core CPU as the task is stored on the BSP stack, which is reused for something else if the APs are to slow. Tested on SuperMicro X11SSH-TF. Change-Id: Id47df02a9238e66f2b628b9d6805858724bf30a9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34570/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9528149..8ff214e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -892,6 +892,19 @@ } mfence(); + if (CONFIG(CONSOLE_SERIAL)) { + /* The serial console is slow and has a spinlock. + * It can take a while for all APs to pickup the work, + * especially with modern multicore CPUs. + * + * Wait longer than requested, otherwise we will return early + * and the stack containing the AP work will be reused for + * something else, causing the APs to crash. + * + * 100msec seems to be sufficent on 8core platform. + */ + expire_us = 100 * USECS_PER_MSEC; + } /* Wait for all the APs to signal back that call has been accepted. */ if (expire_us > 0) stopwatch_init_usecs_expire(&sw, expire_us); -- To view, visit https://review.coreboot.org/c/coreboot/+/34570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id47df02a9238e66f2b628b9d6805858724bf30a9 Gerrit-Change-Number: 34570 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019