coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

1 participants
1442 discussions

Change in coreboot[master]: crossgcc: Upgrade llvm to version 8.0.1
by HAOUAS Elyes (Code Review) 27 Nov '19

27 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34527 ) Change subject: crossgcc: Upgrade llvm to version 8.0.1 ...................................................................... crossgcc: Upgrade llvm to version 8.0.1 Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum D util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum 9 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34527/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3b..0130e8e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -58,7 +58,7 @@ PYTHON_VERSION=3.7.4 EXPAT_VERSION=2.2.7 # CLANG version number -CLANG_VERSION=8.0.0 +CLANG_VERSION=8.0.1 MAKE_VERSION=4.2.1 CMAKE_VERSION=3.15.0 NASM_VERSION=2.14.02 diff --git a/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 45225c1..0000000 --- a/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -3cb1e10af3955174a3ca5e560f674f24fac2a02f tarballs/cfe-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..08bc694 --- /dev/null +++ b/util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +e1d7f274c4fd623f19255cc52c6d7b39cf8769ee tarballs/cfe-8.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 4a689ab..0000000 --- a/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f341ba17494ba756fd404b2744e6f5991b50389f tarballs/clang-tools-extra-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..f2a1261 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +0174e060781fc01e5f97f2ff9b51a03165d7b37a tarballs/clang-tools-extra-8.0.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 2f6cc292..0000000 --- a/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5af387779120bb2a9fad5d6fff1a3d6f4fa6c352 tarballs/compiler-rt-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..b4af06a --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +f6520fb47fae9cc4362a9d50abee22019c27457a tarballs/compiler-rt-8.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 078a3d0..0000000 --- a/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0689345d73911e24a07b24cc82dab4fb46b8c323 tarballs/llvm-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..d255950 --- /dev/null +++ b/util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +09964f9eabc364f221a3caefbdaea28557273b4a tarballs/llvm-8.0.1.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/34527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1 Gerrit-Change-Number: 34527 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: crossgcc: Upgrade Expat to version 2.2.8
by HAOUAS Elyes (Code Review) 27 Nov '19

27 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35432 ) Change subject: crossgcc: Upgrade Expat to version 2.2.8 ...................................................................... crossgcc: Upgrade Expat to version 2.2.8 Changes: https://github.com/libexpat/libexpat/blob/R_2_2_8/expat/Changes Change-Id: I591e4ed186bc8d46ff64161eddc488b640cad5fc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum A util/crossgcc/sum/expat-2.2.8.tar.bz2.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35432/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9c10c7d..f63cd56 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -56,7 +56,7 @@ GDB_VERSION=8.3 IASL_VERSION=20190703 PYTHON_VERSION=3.7.4 -EXPAT_VERSION=2.2.7 +EXPAT_VERSION=2.2.8 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 diff --git a/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum deleted file mode 100644 index 77f6272..0000000 --- a/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -9c8a268211e3f1ae31c4d550e5be7708973ec6a6 tarballs/expat-2.2.7.tar.bz2 diff --git a/util/crossgcc/sum/expat-2.2.8.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.8.tar.bz2.cksum new file mode 100644 index 0000000..68a6b1c --- /dev/null +++ b/util/crossgcc/sum/expat-2.2.8.tar.bz2.cksum @@ -0,0 +1 @@ +e1665bdab5ceaab47718b5a7f3ffceca7f648433 tarballs/expat-2.2.8.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591e4ed186bc8d46ff64161eddc488b640cad5fc Gerrit-Change-Number: 35432 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: crossgcc: Upgrade GDB to version 8.3.1
by HAOUAS Elyes (Code Review) 27 Nov '19

27 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35513 ) Change subject: crossgcc: Upgrade GDB to version 8.3.1 ...................................................................... crossgcc: Upgrade GDB to version 8.3.1 Change-Id: I380ba8678b22483b0d9c5fc558c0e08fd38778e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gdb-8.3.1_amd64.patch R util/crossgcc/patches/gdb-8.3.1_no-doc.patch R util/crossgcc/patches/gdb-8.3.1_pythonhome.patch A util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum D util/crossgcc/sum/gdb-8.3.tar.xz.cksum 6 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35513/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index eb762a3..d1667f0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -53,7 +53,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 -GDB_VERSION=8.3 +GDB_VERSION=8.3.1 IASL_VERSION=20190703 PYTHON_VERSION=3.7.4 EXPAT_VERSION=2.2.7 diff --git a/util/crossgcc/patches/gdb-8.3_amd64.patch b/util/crossgcc/patches/gdb-8.3.1_amd64.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3_amd64.patch rename to util/crossgcc/patches/gdb-8.3.1_amd64.patch diff --git a/util/crossgcc/patches/gdb-8.3_no-doc.patch b/util/crossgcc/patches/gdb-8.3.1_no-doc.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3_no-doc.patch rename to util/crossgcc/patches/gdb-8.3.1_no-doc.patch diff --git a/util/crossgcc/patches/gdb-8.3_pythonhome.patch b/util/crossgcc/patches/gdb-8.3.1_pythonhome.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3_pythonhome.patch rename to util/crossgcc/patches/gdb-8.3.1_pythonhome.patch diff --git a/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum new file mode 100644 index 0000000..c362858 --- /dev/null +++ b/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum @@ -0,0 +1 @@ +d403ba208945bbf04f8130ea4853730cdf0c8fc7 tarballs/gdb-8.3.1.tar.xz diff --git a/util/crossgcc/sum/gdb-8.3.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.tar.xz.cksum deleted file mode 100644 index bc82f51..0000000 --- a/util/crossgcc/sum/gdb-8.3.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f45de6af561f0fa0241f0d5085198556fcfd1e5e tarballs/gdb-8.3.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/35513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I380ba8678b22483b0d9c5fc558c0e08fd38778e7 Gerrit-Change-Number: 35513 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: /mainboard/pcengines/apu2: implement POSTCAR_STAGE
by Krystian Hebel (Code Review) 27 Nov '19

27 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32363 Change subject: /mainboard/pcengines/apu2: implement POSTCAR_STAGE ...................................................................... /mainboard/pcengines/apu2: implement POSTCAR_STAGE As in [1], POSTCAR_STAGE will be required since October 2019. [1]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/HN… Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf --- M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc M src/mainboard/pcengines/apu2/OemCustomize.c A src/mainboard/pcengines/apu2/postcar.c M src/mainboard/pcengines/apu2/romstage.c A src/mainboard/pcengines/apu2/state_machine.c 7 files changed, 213 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32363/1 diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 535024a..0178018 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -16,6 +16,7 @@ #include <AGESA.h> #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> #include <stdlib.h> @@ -23,7 +24,6 @@ #include "imc.h" #include "hudson.h" -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -34,8 +34,7 @@ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); @@ -56,75 +55,66 @@ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ } -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams) { - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + printk(BIOS_DEBUG, "Done\n"); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams) +{ + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - FchParams->Azalia.AzaliaEnable = AzDisable; + FchParams->Azalia.AzaliaEnable = AzDisable; - /* Fan Control */ - oem_fan_control(FchParams); + /* Fan Control */ + oem_fan_control(FchParams); - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; - /* EHCI configuration */ - FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); - if (CONFIG(BOARD_PCENGINES_APU2)) { - // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = FALSE; - } else { - // Enable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = TRUE; - } + if (CONFIG(BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } - // Enable EHCI 1 (port 4 to 7) - // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. - FchParams->Usb.Ehci2Enable = TRUE; + // Enable EHCI 1 (port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; - /* sata configuration */ - FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP - FchParams->Sata.SataDevSlpPort1 = 0; + /* sata configuration */ + FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort1 = 0; - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; } printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; } static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6c3958b..28f9eb8 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4e6364e..7824996 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,10 +14,14 @@ # GNU General Public License for more details. # +romstage-y += state_machine.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c +postcar-y += postcar.c + +ramstage-y += state_machine.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 700f4c7..7ef7e00 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -14,7 +14,7 @@ */ #include <AGESA.h> -#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -76,25 +76,7 @@ .DdiLinkList = NULL, }; -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->PlatformConfig.CStateMode = CStateModeC6; diff --git a/src/mainboard/pcengines/apu2/postcar.c b/src/mainboard/pcengines/apu2/postcar.c new file mode 100644 index 0000000..b57ea94 --- /dev/null +++ b/src/mainboard/pcengines/apu2/postcar.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> + +void late_car_teardown(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index bd3c421..a6fe713 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -40,9 +40,11 @@ static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + pci_devfn_t dev; + u32 data; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for @@ -57,51 +59,32 @@ hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - pci_devfn_t dev; - u32 data; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + post_code(0x30); + early_lpc_init(); - post_code(0x30); - early_lpc_init(); + hudson_clk_output_48Mhz(); + post_code(0x31); - hudson_clk_output_48Mhz(); - post_code(0x31); + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + console_init(); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); @@ -112,27 +95,17 @@ val |= (1 << 30); pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - - timestamp_add_now(TS_BEFORE_INITRAM); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); - - timestamp_add_now(TS_AFTER_INITRAM); } -void agesa_postcar(struct sysinfo *cb) -{ - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); +//~ void agesa_postcar(struct sysinfo *cb) +//~ { + //~ //PspMboxBiosCmdDramInfo(); + //~ post_code(0x41); + //~ AGESAWRAPPER(amdinitenv); - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -} + //~ outb(0xEA, 0xCD6); + //~ outb(0x1, 0xcd7); +//~ } static void early_lpc_init(void) { diff --git a/src/mainboard/pcengines/apu2/state_machine.c b/src/mainboard/pcengines/apu2/state_machine.c new file mode 100644 index 0000000..4a10df9 --- /dev/null +++ b/src/mainboard/pcengines/apu2/state_machine.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> +#include <binaryPI/FieldAccessors.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} + +AGESA_STATUS +AmdGetValue ( + IN CONST AGESA_FIELD_NAME name, + IN OUT VOID** value, + IN UINT32 size + ) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Gerrit-Change-Number: 32363 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: device/mmio.h: Add bit field helpers
by Hung-Te Lin (Code Review) 27 Nov '19

27 Nov '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35463 ) Change subject: device/mmio.h: Add bit field helpers ...................................................................... device/mmio.h: Add bit field helpers When accessing register with multiple bit fields, the common approach is to use clrsetbits_le32, for example: clrsetbits(&reg, (1 << 0) | (0x3 << 1) | (0x7 << 10), (1 << 0) | (0x1 << 1) | (0x5 << 10)); This hard to maintain because we have to calculate the mask values manually, make sure the duplicated shift (offset) was set correctly. And it may be even worse if the value to set will be based on some runtime values (that many developers will do a if-block with two very similar argument list), and leaving lots of magic numbers. We want to encourage developers always giving field names, and have a better way of setting fields. The proposed utility macros are: DEFINE_BITFIELD(name, start, end) SET_BITFIELDS(addr, name, value, [name2, value2, ...]) Where a developer can easily convert from data sheet like BITS NAME 26:24 SEC_VIO Into a declaration DEFINE_BITFIELD(SEC_VIO, 26, 24) Then, a simple call can set the field as: SET_BITFIELDS(&reg, SEC_VIO, 2); That is much easier to understand than clrsetbits(&reg, 0x7 << 24, 0x2 << 24); Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/include/device/mmio.h 1 file changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35463/1 diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index e40b40f..b3b51c2 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -53,4 +53,82 @@ } #endif /* !__ROMCC__ */ +/* + * Utilities to help processing bit fields. + * + * To define a bit field (usually inside a register, do: + * + * DEFINE_BITFIELD(name, start end) + * + * - name: String for name of the field to access. + * - start: starting (high) bit from data sheet. + * - end: ending (low) bit from data sheet. + * + * Then, set the values using: + * + * SET_BITFIELDS(&reg, name, value, [name, value, ...]) + * + * Example: + * + * DEFINE_BITFIELD(DISP_TYPE, 2, 1); + * DEFINE_BITFIELD(DISP_EN, 0, 0); + * + * SET_BITFIELDS(&disp_regs.ctrl, DISP_TYPE, 2); + * SET_BITFIELDS(&disp_regs.ctrl, DISP_EN, 0); + * + * SET_BITFIELDS(&disp_regs.ctrl, DISP_TYPE, 1, DISP_EN, 1); + * + * This will be translated to: + * + * clrsetbits_le32(&disp_regs.ctrl, 0x6, 0x4); + * clrsetbits_le32(&disp_regs.ctrl, 0x1, 0x0); + * + * clrsetbits_le32(&disp_regs.ctrl, 0x7, 0x3); + */ + +#define DEFINE_BITFIELD(name, start, end) \ + _Static_assert(start >= end, "invalid bit field range"); \ + enum { \ + name##_FIELD_SHIFT = (end), \ + name##_FIELD_SIZE = (start) - (end) + 1 } + +#define _BF_MASK(name, value) \ + (((1 << name##_FIELD_SIZE) - 1) << name##_FIELD_SHIFT) + +#define _BF_VALUE(name, value) \ + ((value) << name##_FIELD_SHIFT) + +#define _BF_APPLY1(op, name, value, ...) (op(name, value)) +#define _BF_APPLY2(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY1(op, __VA_ARGS__)) +#define _BF_APPLY3(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY2(op, __VA_ARGS__)) +#define _BF_APPLY4(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY3(op, __VA_ARGS__)) +#define _BF_APPLY5(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY4(op, __VA_ARGS__)) +#define _BF_APPLY6(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY5(op, __VA_ARGS__)) +#define _BF_APPLY7(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY6(op, __VA_ARGS__)) +#define _BF_APPLY8(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY7(op, __VA_ARGS__)) +#define _BF_APPLYINVALID(...) \ + _Static_assert(0, "Invalid arguments to SET_BITFIELDS"); + +#define _SET_BITFIELDS_IMPL(addr, \ + n1, v1, n2, v2, n3, v3, n4, v4, n5, v5, n6, v6, n7, v7, n8, v8, \ + NARGS, ...) \ + \ + clrsetbits_le32(addr, \ + _BF_APPLY##NARGS(_BF_MASK, n1, v1, n2, v2, n3, v3, n4, v4, \ + n5, v5, n6, v6, n7, v7, n8, v8), \ + _BF_APPLY##NARGS(_BF_VALUE, n1, v1, n2, v2, n3, v3, n4, v4, \ + n5, v5, n6, v6, n7, v7, n8, v8)) + +#define SET_BITFIELDS(addr, ...) \ + _SET_BITFIELDS_IMPL(addr, __VA_ARGS__, \ + 8, INVALID, 7, INVALID, 6, INVALID, 5, INVALID, \ + 4, INVALID, 3, INVALID, 2, INVALID, 1, INVALID) + #endif /* __DEVICE_MMIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8 Gerrit-Change-Number: 35463 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

7 45

Change in ...coreboot[master]: [RFC and WIP]Add an option to align FMAP regions
by Arthur Heymans (Code Review) 27 Nov '19

27 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33300 Change subject: [RFC and WIP]Add an option to align FMAP regions ...................................................................... [RFC and WIP]Add an option to align FMAP regions This eases writing FMD files when there are alignment requirement on some regions (e.g. MRC_VAR_CACHE). Some questions: - Do we want to error out on options that have a base defined but that does not follow its alignment or do we want to fix the alignment if such configuration presents itself - '~' is used. Is that the 'best' symbol Change-Id: If6e01112f0c98f45876bcc7012f195f5aa693efd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fmd.c M util/cbfstool/fmd.h M util/cbfstool/fmd_parser.y M util/cbfstool/fmd_scanner.l 4 files changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33300/1 diff --git a/util/cbfstool/fmd.c b/util/cbfstool/fmd.c index 7a289d7..d39ec20 100644 --- a/util/cbfstool/fmd.c +++ b/util/cbfstool/fmd.c @@ -248,6 +248,10 @@ } else if (!first_incomplete_it) { watermark = cur_section->offset + cur_section->size; } + if (cur_section->alignment_known) { + cur_section->offset = (cur_section->offset + cur_section->alignment - 1) + & ~(cur_section->alignment); + } } if (first_incomplete_it && diff --git a/util/cbfstool/fmd.h b/util/cbfstool/fmd.h index 90e6d6e..91ae2fd 100644 --- a/util/cbfstool/fmd.h +++ b/util/cbfstool/fmd.h @@ -53,6 +53,8 @@ bool size_known; /** It is an error to read this field unless size_known is set. */ unsigned size; + bool alignment_known; + unsigned alignment; size_t list_len; union flashmap_flags flags; /** It is an error to dereference this array if list_len is 0. */ diff --git a/util/cbfstool/fmd_parser.y b/util/cbfstool/fmd_parser.y index 3ba710c..e7e1caf 100644 --- a/util/cbfstool/fmd_parser.y +++ b/util/cbfstool/fmd_parser.y @@ -52,7 +52,8 @@ struct flashmap_descriptor *parse_descriptor( char *name, union flashmap_flags flags, struct unsigned_option offset, - struct unsigned_option size, struct descriptor_list children); + struct unsigned_option size, struct unsigned_option alignment, + struct descriptor_list children); void yyerror(const char *s); } @@ -71,6 +72,8 @@ %type <maybe_intval> region_offset %type <maybe_intval> region_size_opt %type <maybe_intval> region_size +%type <maybe_intval> region_alignment_opt +%type <maybe_intval> region_alignment %type <region_listhdr> region_list_opt %type <region_listhdr> region_list %type <region_listhdr> region_list_entries @@ -80,13 +83,14 @@ flash_chip: region_name region_offset_opt region_size region_list { union flashmap_flags flags = { .v=0 }; - if (!(res = parse_descriptor($1, flags, $2, $3, $4))) + struct unsigned_option alignment = { .val_known = false }; + if (!(res = parse_descriptor($1, flags, $2, $3, alignment, $4))) YYABORT; }; flash_region: region_name region_flags_opt region_offset_opt region_size_opt - region_list_opt + region_alignment_opt region_list_opt { - struct flashmap_descriptor *node = parse_descriptor($1, $2, $3, $4, $5); + struct flashmap_descriptor *node = parse_descriptor($1, $2, $3, $4, $5, $6); if (!node) YYABORT; @@ -115,6 +119,9 @@ region_size_opt: { $$ = (struct unsigned_option){false, 0}; } | region_size; region_size: INTEGER { $$ = (struct unsigned_option){true, $1}; }; +region_alignment_opt: { $$ = (struct unsigned_option){false, 0}; } + | region_alignment; +region_alignment: '~' INTEGER { $$ = (struct unsigned_option){true, $2}; }; region_list_opt: { $$ = (struct descriptor_list) @@ -152,7 +159,8 @@ struct flashmap_descriptor *parse_descriptor( char *name, union flashmap_flags flags, struct unsigned_option offset, - struct unsigned_option size, struct descriptor_list children) + struct unsigned_option size, struct unsigned_option alignment, + struct descriptor_list children) { struct flashmap_descriptor *region = malloc(sizeof(*region)); if (!region) { @@ -165,6 +173,8 @@ region->offset = offset.val; region->size_known = size.val_known; region->size = size.val; + region->alignment_known = alignment.val_known; + region->alignment = alignment.val; region->list_len = children.len; if (region->list_len) { region->list = malloc(region->list_len * sizeof(*region->list)); diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l index be9a5de..4c7d322 100644 --- a/util/cbfstool/fmd_scanner.l +++ b/util/cbfstool/fmd_scanner.l @@ -39,7 +39,7 @@ [1-9][0-9]*{MULTIPLIER}? return parse_integer(yytext, 10); 0[0-9]+{MULTIPLIER}? return OCTAL; 0[xX][0-9a-fA-F]+{MULTIPLIER}? return parse_integer(yytext + 2, 16); -[^#@{}()[:space:]]* return copy_string(yytext); +[^#@~{}()[:space:]]* return copy_string(yytext); . return *yytext; %% -- To view, visit https://review.coreboot.org/c/coreboot/+/33300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6e01112f0c98f45876bcc7012f195f5aa693efd Gerrit-Change-Number: 33300 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: src/soc/inte/common/block/cse: Add hmrfpo related functions to cse lib
by Sridhar Siricilla (Code Review) 26 Nov '19

26 Nov '19

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35229 to review the following change. Change subject: src/soc/inte/common/block/cse: Add hmrfpo related functions to cse lib ...................................................................... src/soc/inte/common/block/cse: Add hmrfpo related functions to cse lib Below new function are added: * send_hmrfpo_enable_msg() - Sends HMRFPO Enable command to CSE * send_hmrfpo_get_status_msg() - Sends HMRFPO Get Status command to CSE Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 139 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35229/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9585a09..d85209b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -76,6 +76,15 @@ /* RST Origin */ #define GR_ORIGIN_BIOS_POST 2 +#define MKHI_HMRFPO_GROUP_ID 5 + +/* HMRFPO Command Ids */ +#define MKHI_HMRFPO_ENABLE 1 +#define MKHI_HMRFPO_GET_STATUS 3 + +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_MODE_NORMAL 0 + static struct cse_device { uintptr_t sec_bar; } g_cse; @@ -104,6 +113,16 @@ } __packed fields; }; + +struct mkhi_hdr { + uint8_t group_id; + uint8_t command:7; + uint8_t is_resp:1; + uint8_t rsvd; + uint8_t result; +}__packed; + + /* * Initialize the device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been @@ -652,6 +671,109 @@ return 0; } +/* + * Sends HMRFPO Enable command to CSE + */ +int send_hmrfpo_enable_msg(void) +{ + + struct hmrfpo_enable_msg { + struct mkhi_hdr hdr; + uint32_t nonce[2]; + }__packed; + + /* HMRFPO Enable message */ + struct hmrfpo_enable_msg msg = { + .hdr = { + .group_id = MKHI_HMRFPO_GROUP_ID, + .command = MKHI_HMRFPO_ENABLE, + }, + .nonce = {0}, + }; + + /* HMRFPO Enable response */ + struct hmrfpo_enable_resp { + struct mkhi_hdr hdr; + uint32_t fct_base; + uint32_t fct_limit; + uint8_t status; + uint8_t padding[3]; + }__packed; + + struct hmrfpo_enable_resp resp; + size_t resp_size = sizeof(struct hmrfpo_enable_resp); + union me_hfs hfs; + + printk(BIOS_DEBUG, "Send HMRFPO Enable Command\n"); + hfs.data = me_read_config32(PCI_ME_HFSTS1); + /* + * This command can be run only if: + * - Working state is normal and + * - Operation mode is normal. + */ + if ((hfs.fields.working_state != ME_HFS_CWS_NORMAL) || + (hfs.fields.operation_mode != ME_HFS_MODE_NORMAL)) { + printk(BIOS_ERR, "ME not in normal Mode\n"); + goto failed; + } + + if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), + &resp, &resp_size)) + goto failed; + + if (resp.hdr.result) { + printk(BIOS_ERR, "Heci resp Failed:%d\n", resp.hdr.result); + goto failed; + } + return 1; + +failed: + return 0; +} + +/* + * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. + * The status can be DISABLES/LOCKED/ENABLED + */ +int send_hmrfpo_get_status_msg(void) +{ + struct hmrfpo_get_status_msg { + struct mkhi_hdr hdr; + }__packed; + + struct hmrfpo_get_status_resp { + struct mkhi_hdr hdr; + uint8_t status; + uint8_t padding[3]; + }__packed; + + /* HMRFPO STATUS message */ + struct hmrfpo_get_status_msg msg = { + .hdr = { + .group_id = MKHI_HMRFPO_GROUP_ID, + .command = MKHI_HMRFPO_GET_STATUS, + }, + }; + struct hmrfpo_get_status_resp resp; + size_t resp_size = sizeof(struct hmrfpo_get_status_resp); + + printk(BIOS_ERR, "HMRFPO Status Command\n"); + + if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), + &resp, &resp_size)) + goto failed; + + if (resp.hdr.result) { + printk(BIOS_ERR, "Heci resp Failed:%d\n", resp.hdr.result); + goto failed; + } + + return resp.status; + +failed: + return -1; +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index ceeca88e..c0a5fef 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -77,6 +77,19 @@ */ int send_heci_reset_req_message(u8 rst_type); +/* + * Send HMRFPO_ENABLE command. + * returns 0 on failure and 1 on success. + */ +int send_hmrfpo_enable_msg(void); + +/* + * Send HMRFPO_GET_STATUS command. + * returns -1 on failure and 0 (DISABLED) or 1 (LOCKED) or 2 (ENABLED). + */ +int send_hmrfpo_get_status_msg(void); + + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 @@ -96,5 +109,9 @@ #define HOST_RESET_ONLY 2 #define CSE_RESET_ONLY 3 +/*HMRFPO Status types */ +#define MKHI_HMRFPO_DISABLED 0 +#define MKHI_HMRFPO_LOCKED 1 +#define MKHI_HMRFPO_ENABLED 2 #endif // SOC_INTEL_COMMON_MSR_H -- To view, visit https://review.coreboot.org/c/coreboot/+/35229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db Gerrit-Change-Number: 35229 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

6 24

Change in vboot[master]: build error solve KLOCWORK
by Ronak Kanabar (Code Review) 26 Nov '19

26 Nov '19

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/35485 ) Change subject: build error solve KLOCWORK ...................................................................... build error solve KLOCWORK Change-Id: I45bbf1250bff08435b6d7f75b8d84d960a1fe4e4 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/85/35485/1 diff --git a/Makefile b/Makefile index fa63773..407dbd9 100644 --- a/Makefile +++ b/Makefile @@ -142,7 +142,7 @@ -Wundef -Wmissing-prototypes -Wno-trigraphs -Wredundant-decls -Wshadow \ -Wwrite-strings -Wstrict-aliasing -Wdate-time -Wno-unknown-warning \ -Wno-address-of-packed-member -ffunction-sections -fdata-sections \ - -Wimplicit-fallthrough ${DEBUG_FLAGS} + ${DEBUG_FLAGS} # Note: FIRMWARE_ARCH is defined by the Chromium OS ebuild. ifeq (${FIRMWARE_ARCH},arm) -- To view, visit https://review.coreboot.org/c/vboot/+/35485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I45bbf1250bff08435b6d7f75b8d84d960a1fe4e4 Gerrit-Change-Number: 35485 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: [WIP] amd/stoneyridge: Fix CAR stack location
by Kyösti Mälkki (Code Review) 26 Nov '19

26 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34883 ) Change subject: [WIP] amd/stoneyridge: Fix CAR stack location ...................................................................... [WIP] amd/stoneyridge: Fix CAR stack location As far as I can see, for BSP, gcccar.inc exits with %esp at _car_region_end, not _car_stack_end. On exit from ENABLE_AMD_STACK, %esp will have value of DCACHE_RAM_BASE + DCACHE_RAM_SIZE. This was correct for the stack placement with C_ENVIRONMENT_BOOTBLOCK=n. It would be nice if AMD code had guards so we knew how much stack it needs. Setting of DCACHE_BSP_STACK_SIZE works with inverse logic now, the higher you set it, the less space is where the stack is located. This raises the question how its size was determined. 00030000 B _car_region_start 00030000 B _car_stack_start 00034000 B _car_stack_end 00034000 B _preram_cbmem_console 00035600 B _car_relocatable_data_start 00035850 B _car_global_start 00035860 B _car_global_end 00035860 B _car_relocatable_data_end 00040000 B _car_region_end Use the symbol _car_stack_end to have early stage use the location assigned by the linker script car.ld. Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/34883/1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4f0bb3f..c23939c 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -31,6 +31,8 @@ .globl _cache_as_ram_setup, _cache_as_ram_setup_end .globl chipset_teardown_car +#if ENV_ROMSTAGE + _cache_as_ram_setup: /* Preserve BIST. */ @@ -49,6 +51,10 @@ AMD_ENABLE_STACK + /* Let arch/x86/car.ld determine our stack location. + * FIXME: Only do this for BSP. !! */ + movl $_car_stack_end, %esp + /* Align the stack. */ and $0xFFFFFFF0, %esp @@ -107,6 +113,8 @@ pushl %eax call romstage_main +#endif /* ENV_ROMSTAGE */ + #if CONFIG(POSTCAR_STAGE) /* We do not return. Execution continues with run_postcar_phase() diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 402da3a..ad0ea53 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -38,6 +38,10 @@ AMD_ENABLE_STACK + /* Let arch/x86/car.ld determine our stack location. + * FIXME: Only do this for BSP. !! */ + movl $_car_stack_end, %esp + /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp sub $8, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/34883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7 Gerrit-Change-Number: 34883 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
by Krystian Hebel (Code Review) 26 Nov '19

26 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32421 Change subject: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER ...................................................................... nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. AmdGetValue() is required by cpu_bus_scan(), it is adapted from binaryPI wrapper to use new interface for dispatcher. Tested only on 00730F01 (apu2) - no other platforms available. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc A src/northbridge/amd/pi/state_machine.c 5 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32421/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c..c64a7ba 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1006,3 +1009,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df725..08dfd84 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -991,3 +994,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 926208c..f69f226 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -40,6 +40,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1242,3 +1244,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d88..349761b 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -22,6 +22,9 @@ ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += agesawrapper.c ramstage-y += agesawrapper.c +else +romstage-y += state_machine.c +ramstage-y += state_machine.c endif romstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/state_machine.c b/src/northbridge/amd/pi/state_machine.c new file mode 100644 index 0000000..f42e97f --- /dev/null +++ b/src/northbridge/amd/pi/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2019 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Gerrit-Change-Number: 32421 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

6 24

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2019