coreboot-gerrit September 2019

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Change in coreboot[master]: [TEST-ONLY]Set STAPM percentage for Treeya
by Peichao Li (Code Review) 05 Nov '19

05 Nov '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35042 ) Change subject: [TEST-ONLY]Set STAPM percentage for Treeya ...................................................................... [TEST-ONLY]Set STAPM percentage for Treeya Tuning stapm percent from 80 to 68 meet our thermal requirement BUG=None TEST=build and boot treeya Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 --- M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35042/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index beb99e0..7005644 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -20,7 +20,7 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "16 * MiB" - register "stapm_percent" = "80" + register "stapm_percent" = "68" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" -- To view, visit https://review.coreboot.org/c/coreboot/+/35042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 Gerrit-Change-Number: 35042 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: soc/intel: Remove unsued code
by Patrick Rudolph (Code Review) 04 Nov '19

04 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35207 ) Change subject: soc/intel: Remove unsued code ...................................................................... soc/intel: Remove unsued code Delete acpi_create_intel_hpet() which has been replaced by acpi_write_hpet() in the corresponding soc folders some time ago. Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/include/soc/acpi.h M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/include/soc/acpi.h 9 files changed, 0 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35207/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c322cce..db6b271 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -131,37 +131,6 @@ return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 29acda7..2851f92 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <soc/nvs.h> -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc00..c0455b4 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -185,37 +185,6 @@ #endif } -void acpi_create_intel_hpet(acpi_hpet_t *hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 24fe3ae..d075464 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -25,7 +25,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 5de58ea..5ab77e0 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -21,7 +21,6 @@ #include <arch/acpi.h> #include <soc/nvs.h> -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..565c181 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -128,37 +128,6 @@ return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h index 27b7000..917419e 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h +++ b/src/soc/intel/fsp_baytrail/include/soc/acpi.h @@ -21,7 +21,6 @@ #include <soc/nvs.h> #include <device/device.h> -void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 6b1d3f6..e8aebe2 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -114,36 +114,6 @@ return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t *hpet) -{ - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); - - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); - - /* fill out header fields */ - memcpy(header->signature, "HPET", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_hpet_t); - header->revision = get_acpi_table_revision(HPET); - - /* fill out HPET address */ - addr->space_id = 0; /* Memory */ - addr->bit_width = 64; - addr->bit_offset = 0; - addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; - addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; - - hpet->id = 0x8086a201; /* Intel */ - hpet->number = 0x00; - hpet->min_tick = 0x0080; - - header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h index 44e17d0..419f229 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h @@ -20,7 +20,6 @@ #include <arch/acpi.h> -void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); uint16_t get_pmbase(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/35207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Gerrit-Change-Number: 35207 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review) 03 Nov '19

03 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971 Change subject: util/autoport: Make dsdt.asl prettier ...................................................................... util/autoport: Make dsdt.asl prettier Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/main.go 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..5d660d1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -842,13 +842,14 @@ for _, define := range DSDTDefines { if define.Comment != "" { - fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) } dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } dsdt.WriteString( - `#include <arch/acpi.h> + ` +#include <arch/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -858,7 +859,7 @@ 0x20141018 // OEM revision ) { - // Some generic macros + /* Some generic macros */ #include "acpi/platform.asl" `) @@ -870,9 +871,8 @@ } dsdt.WriteString(` - Scope (\_SB) { - Device (PCI0) - { + Device (\_SB.PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { @@ -881,8 +881,7 @@ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } - } + ` } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/30971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Gerrit-Change-Number: 30971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: [WIP] Reduce (void **) pointer usage
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30684 Change subject: [WIP] Reduce (void **) pointer usage ...................................................................... [WIP] Reduce (void **) pointer usage Use uintptr_t * instead. Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/drivers/intel/fsp1_1/include/fsp/memmap.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/include/fsp/memmap.h M src/drivers/intel/fsp2_0/stage_cache.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/baytrail/stage_cache.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/stage_cache.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/include/intelblocks/smm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/smmrelocate.c 35 files changed, 102 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30684/1 diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..fb4a6c3 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -17,10 +17,10 @@ #include <stage_cache.h> #include "haswell.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..a0aaba5 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -17,12 +17,12 @@ #include <stage_cache.h> #include "model_206ax.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7fed2a1..ad9e9dd 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -147,12 +147,12 @@ /* Display SMM area */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - char *smm_base; + uintptr_t smm_base; size_t smm_size; - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base); #endif /* Migrate CAR data */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 864ab45..41d5437 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -33,19 +33,19 @@ /* Display SMM memory map */ static void smm_memory_map(void) { - void *base; + uintptr_t base; size_t size; int i; printk(BIOS_SPEW, "SMM Memory Map\n"); smm_region(&base, &size); - printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + printk(BIOS_SPEW, "SMRAM : 0x%08x 0x%zx\n", (unsigned int)base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); + printk(BIOS_SPEW, " Subregion %d: 0x%08x 0x%zx\n", i, (unsigned int)base, size); } } diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index eb2a637..1b748aa 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -117,9 +117,8 @@ num_mtrrs++; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uint32_t tseg_base; /* * Cache the TSEG region at the top of ram. This region is not @@ -128,11 +127,10 @@ * the SMM handler as well as using the TSEG region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uint32_t)smm_base; slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + slot = stack_push32(slot, (uint32_t)smm_base | MTRR_TYPE_WRBACK); num_mtrrs++; #endif diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6..4895340 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -18,11 +18,11 @@ #include <fsp/memmap.h> #include <stage_cache.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..2ea6656 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -20,11 +20,11 @@ #include <reset.h> #include <program_loading.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 28cb859..2a6c3bc 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -41,7 +41,7 @@ /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..35bcce4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..e5b8bea 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -62,21 +62,21 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* Initialize global tracking state. */ smm_region_info(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.tseg_base = relo_attrs.smbase; relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); relo_attrs.tseg_mask |= SMM_TSEG_WB; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d62c791..82be938 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -114,12 +114,12 @@ * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); /* * Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); void domain_enable_resources(struct device *dev); void domain_read_resources(struct device *dev); void domain_set_resources(struct device *dev); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..ea3bd8b 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -80,18 +80,18 @@ return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } @@ -117,7 +117,7 @@ wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -143,7 +143,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9314488..e89f9e6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -82,7 +82,7 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; uintptr_t tseg_base; msr_t base, mask; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bcec28e..89faa85 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -196,9 +196,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..50ececa 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -48,7 +48,7 @@ return tolum; } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -56,7 +56,6 @@ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region_info(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; assert(sub_size > CONFIG_SMM_RESERVED_SIZE); @@ -74,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c index 4c2a976..8e8c67f 100644 --- a/src/soc/intel/baytrail/stage_cache.c +++ b/src/soc/intel/baytrail/stage_cache.c @@ -17,7 +17,7 @@ #include <stage_cache.h> #include <soc/smm.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { char *smm_base; /* 1MiB cache size */ @@ -27,5 +27,5 @@ * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + *base = smm_base + smm_region_size() - cache_size; } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 12f34fb..b4face2 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -147,7 +147,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..89c3ab0 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -29,9 +29,9 @@ return smm_size; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } @@ -51,15 +51,13 @@ * | (TSEG) | * +-------------------------+ BUNIT_SMRRL */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; - void *sub_ptr; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_ptr, &sub_size); - sub_base = (uintptr_t)sub_ptr; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -75,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; @@ -83,7 +81,7 @@ void *cbmem_top(void) { - char *smm_base; + uintptr_t smm_base; size_t smm_size; /* @@ -114,6 +112,6 @@ * +-------------------------+ */ - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 6e148b9..36b4377 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -87,7 +87,7 @@ unsigned long mmconf; unsigned long bmbound_k; unsigned long bmbound_hi; - void *smm_base; + uintptr_t smm_base; size_t smm_size; unsigned long tseg_base_k; unsigned long tseg_top_k; diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index dc59ab7..b812ced 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -18,7 +18,7 @@ #include <stage_cache.h> #include <stdint.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region. * The top of RAM is defined to be the TSEG base address. */ @@ -26,6 +26,6 @@ offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(cbmem_top() + offset); + *base = cbmem_top() + offset; *size = CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..8aeabac 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -29,9 +29,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -46,16 +46,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -77,7 +75,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index e688592..59ae790 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -173,11 +173,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t *ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -196,9 +196,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -232,24 +232,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46..e2d38fd 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -33,6 +33,6 @@ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); /* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); #endif diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index d929975..d9b5645 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -89,9 +89,9 @@ ); } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7..683af8e 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -91,9 +91,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ @@ -108,7 +108,7 @@ relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 771c3d8..e597e9d 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -33,7 +33,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -48,7 +48,7 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..b4812ab 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -71,13 +71,13 @@ return system_agent_region_base(TOLUD) - smm_region_start(); } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -102,7 +102,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 617b64a..712ec83 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -147,9 +147,8 @@ uintptr_t top_of_ram; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; #endif console_init(); @@ -190,8 +189,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); #endif run_postcar_phase(&pcf); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..20ae6e8 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -28,9 +28,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -45,16 +45,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -76,7 +74,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 57a366a..bb81799 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -172,11 +172,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -195,9 +195,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -231,24 +231,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..c33787a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,9 +40,9 @@ return 8*MiB; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -57,16 +57,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -88,7 +86,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..248f50f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -167,7 +167,7 @@ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - void *smm_base; + uintptr_t *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -179,7 +179,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; + tseg_base = smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index cb4e23f..82aacd4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -241,24 +241,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, -- To view, visit https://review.coreboot.org/c/coreboot/+/30684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Gerrit-Change-Number: 30684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 19

Change in ...coreboot[master]: console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices'
by Arthur Heymans (Code Review) 01 Nov '19

01 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32042 Change subject: console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices' ...................................................................... console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices' This has nothing to do with console options. This also improves the help text to reflect what it actually does. Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/console/Kconfig M src/device/Kconfig 2 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32042/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667..fb87e67 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -176,13 +176,6 @@ # TODO: Deps? # TODO: Improve description. -config ONBOARD_VGA_IS_PRIMARY - bool "Use onboard VGA as primary video device" - default n - depends on PCI - help - If not selected, the last adapter found will be used. - config CONSOLE_NE2K bool "Network console over NE2000 compatible Ethernet adapter" default n diff --git a/src/device/Kconfig b/src/device/Kconfig index 8001b43..2da12bc 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -683,4 +683,14 @@ I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config ONBOARD_VGA_IS_PRIMARY + bool "Use onboard VGA as primary video device" + default n + depends on PCI + help + This option lets you select which VGA device will be used + to decode legacy VGA cycles. Not all chipsets implement this + however. If not selected, the last adapter found will be used, + else the onboard adapter is used. + endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Gerrit-Change-Number: 32042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: sc7180: support bitbang UART w/gpio
by mturney mturney (Code Review) 01 Nov '19

01 Nov '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35498 ) Change subject: sc7180: support bitbang UART w/gpio ...................................................................... sc7180: support bitbang UART w/gpio Change-Id: I21b149500849eceea663d18a0880c6443ae47d9b Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/uart_bitbang.c 1 file changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35498/1 diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index 813be89..fa0eac8 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -17,20 +17,14 @@ #include <console/uart.h> #include <gpio.h> #include <types.h> - -#if 0 -#define UART_TX_PIN GPIO(4) -#else #include <boot/coreboot_tables.h> -gpio_t uart_gpio = { 0 }; -#define UART_TX_PIN uart_gpio + +#define UART_TX_PIN GPIO(44) void uart_fill_lb(void *data) { } -#endif - static void set_tx(int line_state) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b149500849eceea663d18a0880c6443ae47d9b Gerrit-Change-Number: 35498 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sc7180: Add gpio driver
by mturney mturney (Code Review) 01 Nov '19

01 Nov '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35497 ) Change subject: sc7180: Add gpio driver ...................................................................... sc7180: Add gpio driver Add support for gpio driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/30003/25 https://review.coreboot.org/c/coreboot/+/31083/15 Change-Id: I12bdbeb97765b6ae1e015ca35108008bf82801cc Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Signed-off-by: srimuc <srimuc(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/gpio.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7180/include/soc/gpio.h 3 files changed, 280 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35497/1 diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index bb5baf5..860596d 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2018-2019 Qualcomm Inc. + * Copyright 2019 Qualcomm Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,51 +15,91 @@ #include <arch/mmio.h> #include <assert.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> #include <types.h> + #include <gpio.h> void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, uint32_t drive_str, uint32_t enable) { + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ + assert(pull <= GPIO_PULL_UP); + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); } void gpio_set(gpio_t gpio, int value) { + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); } int gpio_get(gpio_t gpio) { - return 0; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); } void gpio_input_pulldown(gpio_t gpio) { - + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); } void gpio_input_pullup(gpio_t gpio) { - + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); } void gpio_input(gpio_t gpio) { - + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); } void gpio_output(gpio_t gpio, int value) { - + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); } void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) { + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_DISABLE); + + clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); + clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT); } int gpio_irq_status(gpio_t gpio) { - return 0; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) + return 0; + + write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); + return 1; } diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 308b2fb..e394189 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -21,5 +21,8 @@ #define AOSS_CC_BASE 0x0C2A0000 #define GCC_BASE 0x00100000 #define QSPI_BASE 0x088DC000 +#define TLMM_NORTH_TILE_BASE 0x03900000 +#define TLMM_SOUTH_TILE_BASE 0x03D00000 +#define TLMM_WEST_TILE_BASE 0x03500000 #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index 170854c..e2f7a65 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,6 +23,53 @@ u32 addr; } gpio_t; +#define TLMM_TILE_SIZE 0x00400000 +#define TLMM_GPIO_OFF_DELTA 0x00001000 +#define TLMM_GPIO_TILE_NUM 3 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +#define GPIO_FUNC_GPIO 0 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + /* GPIO TLMM: Direction */ #define GPIO_INPUT 0 #define GPIO_OUTPUT 1 @@ -33,16 +80,48 @@ #define GPIO_KEEPER 2 #define GPIO_PULL_UP 3 -/* GPIO TLMM: Status */ -#define GPIO_OUTPUT_DISABLE 0 -#define GPIO_OUTPUT_ENABLE 1 +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 -#define GPIO_FUNC_GPIO 0 +/* GPIO TLMM: Status */ +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 118 #define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) -/* TODO: fill this in for Rennell */ -#if 0 #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ GPIO##index##_FUNC_##func1 = 1, \ @@ -54,9 +133,151 @@ GPIO##index##_FUNC_##func7 = 7 enum { - PIN(0, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(0, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, NORTH, QUP1_L0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, NORTH, QUP1_L1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, NORTH, GP_PDM_MIRB, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(9, NORTH, RES1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(10, NORTH, MDP_VSYNC_P_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(11, NORTH, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(12, SOUTH, MDP_VSYNC_E, RES_2, QUP0_L4, RES_4, RES_5, RES_6, RES_7), + PIN(13, SOUTH, CAM_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(14, SOUTH, CAM_MCLK1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(15, SOUTH, CAM_MCLK2, QUP0_L0, QUP0_L2, RES_4, RES_5, RES_6, RES_7), + PIN(16, SOUTH, CAM_MCLK3, QUP0_L1, QUP0_L3, RES_4, RES_5, RES_6, RES_7), + PIN(17, SOUTH, CCI_I2C_SDA0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(18, SOUTH, CCI_I2C_SCL0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(19, SOUTH, CCI_I2C_SDA1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(20, SOUTH, CCI_I2C_SCL1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(21, NORTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(22, NORTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(23, SOUTH, CCI_TIMER2, CAM_MCLK4, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, QUP0_L0, RES_4, RES_5, RES_6, + RES_7), + PIN(26, SOUTH, CCI_ASYNC_IN0, QUP0_L1, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(27, SOUTH, CCI_I2C_SDA2, QUP0_L2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(36, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(37, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(38, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(39, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(40, SOUTH, QUP0_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(41, SOUTH, QUP0_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(42, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(43, NORTH, QUP1_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(45, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(46, NORTH, QUP1_L0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(47, NORTH, QUP1_L1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(48, NORTH, GCC_GP1_CLK_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(49, WEST, MI2S_1_SCK, BTFM_SLIMBUS_CLK, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(50, WEST, MI2S_1_WS, BTFM_SLIMBUS_DATA0, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(51, WEST, MI2S_1_DATA0, BTFM_SLIMBUS_DATA1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(52, WEST, MI2S_1_DATA1, BTFM_SLIMBUS_DATA2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(53, WEST, MI2S_0_SCK, QUP1_L0, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(54, WEST, MI2S_0_WS, QUP1_L1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(55, WEST, MI2S_0_DATA0, QUP1_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(56, WEST, MI2S_0_DATA1, QUP1_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(57, WEST, LPASS_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(58, WEST, LPASS_EXT_MCLK1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(59, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(60, NORTH, QUP1_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(61, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(62, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(63, NORTH, QSPI_CLK, MDP_VSYNC0_OUT, MI2S_2_SCK, MDP_VSYNC1_OUT, + MDP_VSYNC2_OUT, MDP_VSYNC3_OUT, RES_7), + PIN(64, NORTH, QSPI_DATA_0, MI2S_2_WS, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(65, NORTH, QSPI_DATA_1, MI2S_2_DATA0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(66, NORTH, QSPI_DATA_2, MI2S_2_DATA1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(67, NORTH, QSPI_DATA_3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(68, NORTH, QSPI_CS_N_0, QUP1_L4, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(69, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(70, NORTH, RES_1, RES_2, MDP_VSYNC_P_MIRB, LDO_EN, RES_5, RES_6, + RES_7), + PIN(71, NORTH, RES_1, MDP_VSYNC_S_MIRB, LDO_UPDATE, RES_4, RES_5, RES_6, + RES_7), + PIN(72, NORTH, QSPI_CS_N_1, QUP1_L5, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(73, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(74, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(75, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(76, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(77, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(78, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(79, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(80, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(81, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(82, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(83, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(84, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(85, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(86, NORTH, QUP1_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, NORTH, QUP1_L1, ADSP_EXT_VFR_IRQ, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(88, NORTH, QUP1_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(89, NORTH, QUP1_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(90, NORTH, QUP1_L4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(91, NORTH, QUP1_L5, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(92, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(93, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(94, SOUTH, QUP0_L5, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(95, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(96, WEST, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(97, WEST, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(98, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(99, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(103, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(104, WEST, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(105, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(106, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(107, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(108, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(109, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(110, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(111, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(112, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(113, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(114, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(115, WEST, QUP0_L0, QUP0_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(116, WEST, QUP0_L1, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(117, WEST, DP_HOT_PLUG_DETECT_MIRB, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(118, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), }; -#endif enum gpio_irq_type { IRQ_TYPE_LEVEL = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/35497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12bdbeb97765b6ae1e015ca35108008bf82801cc Gerrit-Change-Number: 35497 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: sb/intel/common: Make linking pmbase.c conditional
by Arthur Heymans (Code Review) 30 Oct '19

30 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33200 Change subject: sb/intel/common: Make linking pmbase.c conditional ...................................................................... sb/intel/common: Make linking pmbase.c conditional Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33200/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..42717b0 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -10,6 +10,10 @@ def_bool n depends on SOUTHBRIDGE_INTEL_COMMON +config SOUTHBRIDGE_INTEL_COMMON_PMBASE + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON + config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n @@ -35,6 +39,7 @@ def_bool n select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_PMBASE config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index dbc9c93..ac2fd8e 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -38,8 +38,10 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) -$(eval $(call add_to_all_stages,y,pmbase.c)) +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE),pmbase.c)) +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE),y) smm-y += pmbase.c +endif bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Gerrit-Change-Number: 33200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 15

Change in ...coreboot[master]: sb/intel/common/Makefile: Use the macro to link files in all stages
by Arthur Heymans (Code Review) 30 Oct '19

30 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33199 Change subject: sb/intel/common/Makefile: Use the macro to link files in all stages ...................................................................... sb/intel/common/Makefile: Use the macro to link files in all stages This links the reset function, the common pmbase functions and the spi driver in all stages. Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Makefile.inc 1 file changed, 4 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33199/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index ab5e5d8..dbc9c93 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,11 +27,7 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware -verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET),reset.c)) romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c @@ -42,10 +38,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) -verstage-y += pmbase.c -romstage-y += pmbase.c -ramstage-y += pmbase.c -postcar-y += pmbase.c +$(eval $(call add_to_all_stages,y,pmbase.c)) smm-y += pmbase.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c @@ -56,9 +49,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI),spi.c)) ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c endif @@ -73,10 +64,6 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c -verstage-y += rtc.c -romstage-y += rtc.c -ramstage-y += rtc.c -postcar-y += rtc.c -smm-y += rtc.c +$(eval $(call add_to_all_stages,y,rtc.c)) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Gerrit-Change-Number: 33199 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 14

Change in ...coreboot[master]: sb/intel/common: Add macro to link a file in all stages
by Arthur Heymans (Code Review) 30 Oct '19

30 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33198 Change subject: sb/intel/common: Add macro to link a file in all stages ...................................................................... sb/intel/common: Add macro to link a file in all stages It is easy to forget to link some files which breaks the build when some Kconfig options get enabled. Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Makefile.inc 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33198/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4cf6e6f..ab5e5d8 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -13,6 +13,17 @@ ## GNU General Public License for more details. ## +# add SPI drivers per stage except smm +# $1 condition +# $2 filename +define add_to_all_stages +bootblock-$(1) += $(2) +verstage-$(1) += $(2) +romstage-$(1) += $(2) +postcar-$(1) += $(2) +ramstage-$(1) += $(2) +endef + # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware -- To view, visit https://review.coreboot.org/c/coreboot/+/33198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9 Gerrit-Change-Number: 33198 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 28

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coreboot-gerrit September 2019