coreboot-gerrit September 2019

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Change in ...coreboot[master]: HACK fix upstream bug in util/cbfstool/fit.c
by mturney mturney (Code Review) 21 Jan '20

21 Jan '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33812 Change subject: HACK fix upstream bug in util/cbfstool/fit.c ...................................................................... HACK fix upstream bug in util/cbfstool/fit.c Change-Id: Iac4df05477de0a7a26af46720c4a19156767463f Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M util/cbfstool/fit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33812/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 4cd84f2..500e14f 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -601,7 +601,7 @@ name = "unknown"; } - printf(" %6zd %-20s 0x%08"PRIx64" 0x%08zx\n", i, name, + printf(" %6zd %-20s 0x%08zx 0x%08zx\n", i, name, fit->entries[i].address, fit_entry_size_bytes(&fit->entries[i])); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac4df05477de0a7a26af46720c4a19156767463f Gerrit-Change-Number: 33812 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: hatch: Create puff variant
by Edward O'Callaghan (Code Review) 21 Jan '20

21 Jan '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35554 ) Change subject: hatch: Create puff variant ...................................................................... hatch: Create puff variant BUG=none TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_PUFF Change-Id: I32c9d8bf41e2895bca2184558e8c1059659e6eb9 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 7 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/35554/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index c4c9146..9b128b1 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -77,6 +77,7 @@ default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU + default "PUFF TEST 9896" if BOARD_GOOGLE_PUFF config MAINBOARD_DIR string @@ -94,6 +95,7 @@ default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Puff" if BOARD_GOOGLE_PUFF config MAINBOARD_VENDOR string @@ -119,6 +121,7 @@ default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "puff" if BOARD_GOOGLE_PUFF config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 01b6ead..a652a41 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -36,3 +36,9 @@ select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMETLAKE + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc new file mode 100644 index 0000000..38cf728 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000..1322233 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb new file mode 100644 index 0000000..abbcaaa --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/35554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32c9d8bf41e2895bca2184558e8c1059659e6eb9 Gerrit-Change-Number: 35554 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: WIP lenovo/x230t: Add new mainboard
by Damien Zammit (Code Review) 20 Jan '20

20 Jan '20

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34361 ) Change subject: WIP lenovo/x230t: Add new mainboard ...................................................................... WIP lenovo/x230t: Add new mainboard This is a working port for x230t mostly using autoport. However, it should be made into a variant of x230. I don't have time to do that right now, so I'm pushing as is. gpios seem different between x230 and x230t, please check, but this plus the next commit (gpio33 corrected setting) works on x230t. Change-Id: I3e6b1de3c71bac548af9585f83293817d0576129 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/mainboard/lenovo/x230t/Kconfig A src/mainboard/lenovo/x230t/Kconfig.name A src/mainboard/lenovo/x230t/Makefile.inc A src/mainboard/lenovo/x230t/acpi/ec.asl A src/mainboard/lenovo/x230t/acpi/platform.asl A src/mainboard/lenovo/x230t/acpi/superio.asl A src/mainboard/lenovo/x230t/acpi_tables.c A src/mainboard/lenovo/x230t/board_info.txt A src/mainboard/lenovo/x230t/cmos.default A src/mainboard/lenovo/x230t/cmos.layout A src/mainboard/lenovo/x230t/data.vbt A src/mainboard/lenovo/x230t/devicetree.cb A src/mainboard/lenovo/x230t/dsdt.asl A src/mainboard/lenovo/x230t/gma-mainboard.ads A src/mainboard/lenovo/x230t/gpio.c A src/mainboard/lenovo/x230t/hda_verb.c A src/mainboard/lenovo/x230t/mainboard.c A src/mainboard/lenovo/x230t/romstage.c A src/mainboard/lenovo/x230t/smihandler.c A src/mainboard/lenovo/x230t/thermal.h 20 files changed, 1,137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34361/1 diff --git a/src/mainboard/lenovo/x230t/Kconfig b/src/mainboard/lenovo/x230t/Kconfig new file mode 100644 index 0000000..f3154b5 --- /dev/null +++ b/src/mainboard/lenovo/x230t/Kconfig @@ -0,0 +1,58 @@ +if BOARD_LENOVO_X230T + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_TRESHOLDS_IMPL + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_INT15 + select DRIVERS_RICOH_RCE822 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default lenovo/x230t + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad X230 Tablet" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +endif # BOARD_LENOVO_X230T diff --git a/src/mainboard/lenovo/x230t/Kconfig.name b/src/mainboard/lenovo/x230t/Kconfig.name new file mode 100644 index 0000000..93cb151 --- /dev/null +++ b/src/mainboard/lenovo/x230t/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_X230T + bool "ThinkPad X230 Tablet" diff --git a/src/mainboard/lenovo/x230t/Makefile.inc b/src/mainboard/lenovo/x230t/Makefile.inc new file mode 100644 index 0000000..30cf715 --- /dev/null +++ b/src/mainboard/lenovo/x230t/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +smm-y += smihandler.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x230t/acpi/ec.asl b/src/mainboard/lenovo/x230t/acpi/ec.asl new file mode 100644 index 0000000..4b11e56 --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} + +#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> diff --git a/src/mainboard/lenovo/x230t/acpi/platform.asl b/src/mainboard/lenovo/x230t/acpi/platform.asl new file mode 100644 index 0000000..bf686f4 --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi/platform.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + /* Not implemented. */ + Return(Package(){0,0}) +} diff --git a/src/mainboard/lenovo/x230t/acpi/superio.asl b/src/mainboard/lenovo/x230t/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x230t/acpi_tables.c b/src/mainboard/lenovo/x230t/acpi_tables.c new file mode 100644 index 0000000..279674d --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi_tables.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/x230t/board_info.txt b/src/mainboard/lenovo/x230t/board_info.txt new file mode 100644 index 0000000..09ddde1 --- /dev/null +++ b/src/mainboard/lenovo/x230t/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/lenovo/x230t/cmos.default b/src/mainboard/lenovo/x230t/cmos.default new file mode 100644 index 0000000..979f132 --- /dev/null +++ b/src/mainboard/lenovo/x230t/cmos.default @@ -0,0 +1,16 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +backlight=Both +usb_always_on=Disable diff --git a/src/mainboard/lenovo/x230t/cmos.layout b/src/mainboard/lenovo/x230t/cmos.layout new file mode 100644 index 0000000..27197fb --- /dev/null +++ b/src/mainboard/lenovo/x230t/cmos.layout @@ -0,0 +1,136 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 5 r 0 unused + +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/x230t/data.vbt b/src/mainboard/lenovo/x230t/data.vbt new file mode 100644 index 0000000..9bc06ee --- /dev/null +++ b/src/mainboard/lenovo/x230t/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/x230t/devicetree.cb b/src/mainboard/lenovo/x230t/devicetree.cb new file mode 100644 index 0000000..a3eebce --- /dev/null +++ b/src/mainboard/lenovo/x230t/devicetree.cb @@ -0,0 +1,190 @@ +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" + + device cpu_cluster 0 on + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0x0 on end + device lapic 0xacac off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + register "pci_mmio_size" = "1024" + + device domain 0 on + device pci 00.0 on + subsystemid 0x17aa 0x2203 + end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on + subsystemid 0x17aa 0x2203 + end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) + register "sata_port_map" = "0x7" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "0x0065" + register "p_cnt_throttling_supported" = "1" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 14.0 on + subsystemid 0x17aa 0x2203 + end # USB 3.0 Controller + device pci 16.0 on + subsystemid 0x17aa 0x2203 + end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on + subsystemid 0x17aa 0x21f3 + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x2203 + end # USB2 EHCI #2 + device pci 1b.0 on + subsystemid 0x17aa 0x2203 + end # High Definition Audio + device pci 1c.0 on + subsystemid 0x17aa 0x2203 + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x2203 + end + end + end # PCIe Port #1 + device pci 1c.1 on + subsystemid 0x17aa 0x2203 + end # PCIe Port #2 + device pci 1c.2 on + subsystemid 0x17aa 0x2203 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on + subsystemid 0x17aa 0x2203 + end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on #LPC bridge + subsystemid 0x17aa 0x2203 + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0xfc" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" + register "eventb_enable" = "0xf0" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC bridge + device pci 1f.2 on + subsystemid 0x17aa 0x2203 + end # SATA Controller 1 + device pci 1f.3 on + subsystemid 0x17aa 0x2203 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on + subsystemid 0x17aa 0x2203 + end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/x230t/dsdt.asl b/src/mainboard/lenovo/x230t/dsdt.asl new file mode 100644 index 0000000..1cb4add --- /dev/null +++ b/src/mainboard/lenovo/x230t/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/x230t/gma-mainboard.ads b/src/mainboard/lenovo/x230t/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/lenovo/x230t/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x230t/gpio.c b/src/mainboard/lenovo/x230t/gpio.c new file mode 100644 index 0000000..7e60e76 --- /dev/null +++ b/src/mainboard/lenovo/x230t/gpio.c @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/x230t/hda_verb.c b/src/mainboard/lenovo/x230t/hda_verb.c new file mode 100644 index 0000000..035bae0 --- /dev/null +++ b/src/mainboard/lenovo/x230t/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2203, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa2203), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230t/mainboard.c b/src/mainboard/lenovo/x230t/mainboard.c new file mode 100644 index 0000000..29c15e0 --- /dev/null +++ b/src/mainboard/lenovo/x230t/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock (void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/x230t/romstage.c b/src/mainboard/lenovo/x230t/romstage.c new file mode 100644 index 0000000..10cddeb --- /dev/null +++ b/src/mainboard/lenovo/x230t/romstage.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + { 1, 1, 3 }, /* P2: dock, OC 3 */ + { 1, 1, -1 }, /* P3: wwan, no OC */ + { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 1, -1 }, /* P5: Expresscard, no OC */ + { 0, 0, -1 }, /* P6: Empty */ + { 1, 2, -1 }, /* P7: dock, no OC */ + { 1, 0, -1 }, + { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: webcam, no OC */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd (&spd[0], 0x50, id_only); + read_spd (&spd[2], 0x51, id_only); +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/lenovo/x230t/smihandler.c b/src/mainboard/lenovo/x230t/smihandler.c new file mode 100644 index 0000000..2425927 --- /dev/null +++ b/src/mainboard/lenovo/x230t/smihandler.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/x230t/thermal.h b/src/mainboard/lenovo/x230t/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/x230t/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e6b1de3c71bac548af9585f83293817d0576129 Gerrit-Change-Number: 34361 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: lenovo/x230t: Use INPUT mode for gpio33 as per discussion
by Damien Zammit (Code Review) 20 Jan '20

20 Jan '20

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34362 ) Change subject: lenovo/x230t: Use INPUT mode for gpio33 as per discussion ...................................................................... lenovo/x230t: Use INPUT mode for gpio33 as per discussion Change-Id: Ieb262f38520aa04c65fb8da73e22c96ae510e3eb Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/lenovo/x230t/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34362/1 diff --git a/src/mainboard/lenovo/x230t/gpio.c b/src/mainboard/lenovo/x230t/gpio.c index 7e60e76..c84ba73 100644 --- a/src/mainboard/lenovo/x230t/gpio.c +++ b/src/mainboard/lenovo/x230t/gpio.c @@ -133,7 +133,7 @@ }; static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio33 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, -- To view, visit https://review.coreboot.org/c/coreboot/+/34362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb262f38520aa04c65fb8da73e22c96ae510e3eb Gerrit-Change-Number: 34362 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
by mikeb mikeb (Code Review) 19 Jan '20

19 Jan '20

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31450 to review the following change. Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop ...................................................................... lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S which is currently not used by any of coreboot-supported boards. Also enable the discrete graphics PCI bus leading to HD 8570M (1002,6663) or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround for PCI resource allocation problems to AMD AGESA vendorcode. Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu> Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88 --- M src/device/Kconfig M src/mainboard/lenovo/g505s/devicetree.cb M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 33c1e5b3..5d2087e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -247,8 +247,15 @@ Enable this option for a good compromise between security and speed. config MULTIPLE_VGA_ADAPTERS + prompt "Multiple VGA Adapters" bool + depends on BOARD_LENOVO_G505S default n + help + Some motherboards may have more than one VGA adapter - for example, + there are versions of Lenovo G505S that have a discrete VGA adapter + in addition to its' integrated VGA adapter which is a part of APU. + Enable this option to try to initialize this discrete VGA adapter. menu "Display" depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 99f42d6..1f33c27 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -27,7 +27,7 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end + device pci 2.0 on end # Discrete Graphics PCI bus 0x666X device pci 3.0 off end device pci 4.0 on end # PCIE MINI0 device pci 5.0 on end # PCIE MINI1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c index c566061..ee6d2c2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c @@ -437,8 +437,15 @@ RefPtr = MemPtr->ParameterListPtr; // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; + if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) && + (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) { + // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems + RefPtr->BottomIo = 0xD0; + } + else { + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + } RefPtr->UmaMode = UserOptions.CfgUmaMode; RefPtr->UmaSize = UserOptions.CfgUmaSize; RefPtr->MemHoleRemapping = TRUE; -- To view, visit https://review.coreboot.org/c/coreboot/+/31450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88 Gerrit-Change-Number: 31450 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

7 29

Change in coreboot[master]: src/superio/nuvoton/nct5104d: soft reset GPIO
by Piotr Kleinschmidt (Code Review) 15 Jan '20

15 Jan '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35482 ) Change subject: src/superio/nuvoton/nct5104d: soft reset GPIO ...................................................................... src/superio/nuvoton/nct5104d: soft reset GPIO So far, only hard power off could reset GPIOs state to defaults: IN, Open-drain. Now, defaults are set with every boot to ensure that GPIOS are not in uknown/unwanted state. Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/superio/nuvoton/nct5104d/nct5104d.h M src/superio/nuvoton/nct5104d/superio.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35482/1 diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 707e94a..6826bb6 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -21,15 +21,25 @@ #include <device/pnp_type.h> /* SIO global configuration */ +#define LDN_SELECT_CR07 0x07 #define IRQ_TYPE_SEL_CR10 0x10 /* UARTA,UARTB */ #define IRQ_TYPE_SEL_CR11 0x11 /* SMI,UARTC,UARTD,WDTO */ #define GLOBAL_OPTION_CR26 0x26 #define CR26_LOCK_REG (1 << 4) /* required to access CR10/CR11 */ +/* LDN 0x07 specific registers */ +#define NCT5104D_GPIO0_IO 0xE0 +#define NCT5104D_GPIO1_IO 0xE4 + +/* LDN 0x0F specific registers */ +#define NCT5104D_GPIO0_PP_OD 0xE0 +#define NCT5104D_GPIO1_PP_OD 0xE1 + /* Logical Device Numbers (LDN). */ #define NCT5104D_FDC 0x00 /* FDC - not pinned out */ #define NCT5104D_SP1 0x02 /* UARTA */ #define NCT5104D_SP2 0x03 /* UARTB */ +#define NCT5104D_GPIO 0x07 /* GPIO In-Out configuration */ #define NCT5104D_GPIO_WDT 0x08 /* GPIO WDT Interface */ #define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */ #define NCT5104D_SP3 0x10 /* UARTC */ diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 40d1200..53eb99d 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -106,6 +106,19 @@ pnp_write_config(dev, 0x1c, reg); } +static void reset_gpio(struct device *dev) +{ + /* Soft reset GPIOs to default state: IN, Open-drain */ + + pnp_write_config(dev, LDN_SELECT_CR07, NCT5104D_GPIO); + pnp_write_config(dev, NCT5104D_GPIO0_IO, 0xFF); + pnp_write_config(dev, NCT5104D_GPIO1_IO, 0xFF); + + pnp_write_config(dev, LDN_SELECT_CR07, NCT5104D_GPIO_PP_OD); + pnp_write_config(dev, NCT5104D_GPIO0_PP_OD, 0xFF); + pnp_write_config(dev, NCT5104D_GPIO1_PP_OD, 0xFF); +} + static void nct5104d_init(struct device *dev) { struct superio_nuvoton_nct5104d_config *conf = dev->chip_info; @@ -127,6 +140,7 @@ break; case NCT5104D_GPIO0: case NCT5104D_GPIO1: + reset_gpio(dev); route_pins_to_uart(dev, false); break; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/35482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Gerrit-Change-Number: 35482 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: drivers/aspeed/common: Add support for high resolution framebuffer
by Patrick Rudolph (Code Review) 11 Jan '20

11 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35726 ) Change subject: drivers/aspeed/common: Add support for high resolution framebuffer ...................................................................... drivers/aspeed/common: Add support for high resolution framebuffer Implement reading EDID over software I2C. Copy the linux kernel code and add a bunch of wrapper structs to make it compile. Convert the EDID to a drm_display_mode, which is understood by the driver. Tested on Supermicro X11SSH-TF using FullHD VGA monitor. Initializes the graphics in about 1 second, which is twice as fast as the VGA Option ROM. The framebuffer is advertised and woring in tianocore. Change-Id: I7803566b64158405efc04a39f80a0ec98b44e646 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/ast2050/Kconfig M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/Kconfig M src/drivers/aspeed/common/Makefile.inc M src/drivers/aspeed/common/ast_drv.h A src/drivers/aspeed/common/ast_i2c.c A src/drivers/aspeed/common/ast_mode.c M src/drivers/aspeed/common/ast_tables.h 8 files changed, 1,159 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35726/1 diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 337b181..7d2c728 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -1,5 +1,4 @@ config DRIVERS_ASPEED_AST2050 bool select DRIVERS_ASPEED_AST_COMMON - select HAVE_VGA_TEXT_FRAMEBUFFER select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 59659b8..01d58f9 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -34,6 +34,7 @@ pci_dev_set_resources(dev); } + static void aspeed_ast2050_init(struct device *dev) { struct drm_device drm_dev; @@ -50,13 +51,19 @@ outb(0xa6, 0x3d4); outb(0x2f, 0x3d5); outb(0xa7, 0x3d4); outb(0x3f, 0x3d5); - /* Initialize standard VGA text mode */ - vga_io_init(); - vga_textmode_init(); - printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + if (CONFIG(VGA_TEXT_FRAMEBUFFER)) { + /* Initialize standard VGA text mode */ + vga_io_init(); - /* if we don't have console, at least print something... */ - vga_line_write(0, "ASpeed VGA text mode initialized"); + vga_textmode_init(); + printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "ASpeed VGA text mode initialized"); + } else if (CONFIG(GENERIC_LINEAR_FRAMEBUFFER)) { + ast_driver_framebuffer_init(&drm_dev, 0); + printk(BIOS_INFO, "ASpeed high resolution framebuffer initialized\n"); + } } static struct device_operations aspeed_ast2050_ops = { diff --git a/src/drivers/aspeed/common/Kconfig b/src/drivers/aspeed/common/Kconfig index 653782f..c292bcf 100644 --- a/src/drivers/aspeed/common/Kconfig +++ b/src/drivers/aspeed/common/Kconfig @@ -1,3 +1,12 @@ config DRIVERS_ASPEED_AST_COMMON bool - select VGA + select HAVE_LINEAR_FRAMEBUFFER + select HAVE_VGA_TEXT_FRAMEBUFFER + select VGA if VGA_TEXT_FRAMEBUFFER + select SOFTWARE_I2C if GENERIC_LINEAR_FRAMEBUFFER + +config DRIVERS_ASPEED_I2C_BUS + int + depends on DRIVERS_ASPEED_AST_COMMON + depends on SOFTWARE_I2C + default 0 diff --git a/src/drivers/aspeed/common/Makefile.inc b/src/drivers/aspeed/common/Makefile.inc index 75f8b48..01e09a1 100644 --- a/src/drivers/aspeed/common/Makefile.inc +++ b/src/drivers/aspeed/common/Makefile.inc @@ -1 +1,4 @@ -ramstage-$(CONFIG_DRIVERS_ASPEED_AST_COMMON) += ast_dp501.c ast_main.c ast_post.c +ifeq ($(CONFIG_DRIVERS_ASPEED_AST_COMMON),y) +ramstage-y += ast_dp501.c ast_main.c ast_post.c +ramstage-$(CONFIG_GENERIC_LINEAR_FRAMEBUFFER) += ast_mode.c ast_i2c.c +endif diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index 53640f1..b46e98a 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -44,6 +44,7 @@ AST2150, AST2300, AST2400, + AST2500, AST1180, }; @@ -190,6 +191,8 @@ #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2) #define AST_HWC_SIGNATURE_SIZE 32 +#define EINVAL 22 /* Invalid argument */ + #define AST_DEFAULT_HWC_NUM 2 /* define for signature structure */ #define AST_HWC_SIGNATURE_CHECKSUM 0x00 @@ -200,6 +203,98 @@ #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 +/* ast_mode.c stuff */ +struct ast_vbios_stdtable { + u8 misc; + u8 seq[4]; + u8 crtc[25]; + u8 ar[20]; + u8 gr[9]; +}; + +struct ast_vbios_enhtable { + u32 ht; + u32 hde; + u32 hfp; + u32 hsync; + u32 vt; + u32 vde; + u32 vfp; + u32 vsync; + u32 dclk_index; + u32 flags; + u32 refresh_rate; + u32 refresh_rate_index; + u32 mode_id; +}; + +struct ast_vbios_dclk_info { + u8 param1; + u8 param2; + u8 param3; +}; + +struct ast_vbios_mode_info { + const struct ast_vbios_stdtable *std_table; + const struct ast_vbios_enhtable *enh_table; +}; + +#define DRM_MODE_FLAG_NVSYNC NVSync +#define DRM_MODE_FLAG_PVSYNC PVSync +#define DRM_MODE_FLAG_NHSYNC NHSync +#define DRM_MODE_FLAG_PHSYNC PHSync + +struct drm_display_mode { + /* Proposed mode values */ + u16 vrefresh; /* in Hz */ + u32 clock; + u16 hdisplay; + u16 vdisplay; + u32 flags; + + /* Actual mode we give to hw */ + u16 crtc_hdisplay; + u16 crtc_htotal; + u16 crtc_hblank_start; + u16 crtc_hblank_end; + u16 crtc_hsync_start; + u16 crtc_hsync_end; + u16 crtc_vtotal; + u16 crtc_vsync_start; + u16 crtc_vsync_end; + u16 crtc_vdisplay; + u16 crtc_vblank_start; + u16 crtc_vblank_end; +}; + +struct drm_format { + u32 cpp[1]; /* Colors per pixel */ +}; + +struct drm_framebuffer { + u32 pitches[1]; + struct drm_format *format; +}; + +struct drm_primary { + struct drm_framebuffer *fb; +}; + +struct drm_crtc { + struct drm_device *dev; + struct drm_primary *primary; + struct drm_display_mode mode; +}; + +struct drm_connector { + struct drm_device *dev; +}; + +enum drm_mode_status { + MODE_NOMODE, + MODE_OK +}; + #define AST_MM_ALIGN_SHIFT 4 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) @@ -220,4 +315,12 @@ bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); + +/* ast mode */ +int ast_driver_framebuffer_init(struct drm_device *dev, int flags); + +/* ast i2c */ +void ast_software_i2c_init(unsigned bus); +int ast_software_i2c_read(unsigned bus, struct ast_private *ast_priv, uint8_t edid[256]); + #endif diff --git a/src/drivers/aspeed/common/ast_i2c.c b/src/drivers/aspeed/common/ast_i2c.c new file mode 100644 index 0000000..92cce3d --- /dev/null +++ b/src/drivers/aspeed/common/ast_i2c.c @@ -0,0 +1,137 @@ + +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: Dave Airlie <airlied(a)redhat.com> + * Authors: 9Elements Agency GmbH <patrick.rudolph(a)9elements.com> + */ +#include <delay.h> +#include <device/i2c_simple.h> + +#include "ast_drv.h" + +#if CONFIG_DRIVER_TPM_I2C_BUS == CONFIG_DRIVERS_ASPEED_I2C_BUS +#error Software I2C bus collision! +#endif + +#if CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS == CONFIG_DRIVERS_ASPEED_I2C_BUS +#error Software I2C bus collision! +#endif + +static struct ast_private *ast; + +static int get_clock(unsigned int bus) +{ + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + do { + val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); + + return val & 1 ? 1 : 0; +} + +static int get_data(unsigned int bus) +{ + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + do { + val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); + + return val & 1 ? 1 : 0; +} + +static void set_clock(unsigned int bus, int clock) +{ + int i; + u8 ujcrb7, jtemp; + + for (i = 0; i < 0x10000; i++) { + ujcrb7 = ((clock & 0x01) ? 0 : 1); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); + if (ujcrb7 == jtemp) + break; + } +} + +static void set_data(unsigned int bus, int data) +{ + int i; + u8 ujcrb7, jtemp; + + for (i = 0; i < 0x10000; i++) { + ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); + if (ujcrb7 == jtemp) + break; + } +} + +static struct software_i2c_ops ast_ops = { + .set_sda = set_data, + .set_scl = set_clock, + .get_sda = get_data, + .get_scl = get_clock, +}; + +void ast_software_i2c_init(unsigned bus) +{ + software_i2c[bus] = &ast_ops; + + i2c_recover_bus(bus); +} + +int ast_software_i2c_read(unsigned bus, struct ast_private *ast_priv, uint8_t edid[256]) +{ + ast = ast_priv; + + /* Need to reset internal EEPROM counter to 0 */ + return i2c_read_bytes(bus, 0x50, 0, edid, 256); +} diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c new file mode 100644 index 0000000..b321f5d --- /dev/null +++ b/src/drivers/aspeed/common/ast_mode.c @@ -0,0 +1,777 @@ + +/* + * Copied from Linux drivers/gpu/drm/ast/ast_mode.c + * + * Copyright 2012 Red Hat Inc. + * Parts based on xf86-video-ast + * Copyright (c) 2005 ASPEED Technology Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: Dave Airlie <airlied(a)redhat.com> + * Authors: 9Elements Agency GmbH <patrick.rudolph(a)9elements.com> + */ +#include <edid.h> +#include <device/i2c_simple.h> + +#include "ast_drv.h" +#include "ast_tables.h" + + +static inline void ast_load_palette_index(struct ast_private *ast, + u8 index, u8 red, u8 green, + u8 blue) +{ + ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, red); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, green); + ast_io_read8(ast, AST_IO_SEQ_PORT); + ast_io_write8(ast, AST_IO_DAC_DATA, blue); + ast_io_read8(ast, AST_IO_SEQ_PORT); +} + +static void ast_crtc_load_lut(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + /* FIXME: Gamma cor 2.6 ? */ + for (int i = 0; i < 256; i++) + ast_load_palette_index(ast, i, i, i, i); + +} + +static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate; + const struct ast_vbios_enhtable *best = NULL; + u32 hborder, vborder; + bool check_sync; + dev_err(crtc->dev->pdev, "fb->format->cpp[0] * 8 = %d\n", fb->format->cpp[0] * 8); + + switch (fb->format->cpp[0] * 8) { + case 8: + vbios_mode->std_table = &vbios_stdtable[VGAModeIndex]; + color_index = VGAModeIndex - 1; + break; + case 16: + vbios_mode->std_table = &vbios_stdtable[HiCModeIndex]; + color_index = HiCModeIndex; + break; + case 24: + case 32: + vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex]; + color_index = TrueCModeIndex; + break; + default: + return false; + } + dev_err(crtc->dev->pdev, "crtc->mode.crtc_hdisplay = %d\n", crtc->mode.crtc_hdisplay); + + switch (crtc->mode.crtc_hdisplay) { + case 640: + vbios_mode->enh_table = &res_640x480[refresh_rate_index]; + break; + case 800: + vbios_mode->enh_table = &res_800x600[refresh_rate_index]; + break; + case 1024: + vbios_mode->enh_table = &res_1024x768[refresh_rate_index]; + break; + case 1280: + if (crtc->mode.crtc_vdisplay == 800) + vbios_mode->enh_table = &res_1280x800[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; + break; + case 1360: + vbios_mode->enh_table = &res_1360x768[refresh_rate_index]; + break; + case 1440: + vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; + break; + case 1600: + if (crtc->mode.crtc_vdisplay == 900) + vbios_mode->enh_table = &res_1600x900[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; + break; + case 1680: + vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; + break; + case 1920: + if (crtc->mode.crtc_vdisplay == 1080) + vbios_mode->enh_table = &res_1920x1080[refresh_rate_index]; + else + vbios_mode->enh_table = &res_1920x1200[refresh_rate_index]; + break; + default: + return false; + } + + refresh_rate = mode->vrefresh; + check_sync = vbios_mode->enh_table->flags & WideScreenMode; + do { + const struct ast_vbios_enhtable *loop = vbios_mode->enh_table; + + while (loop->refresh_rate != 0xff) { + if ((check_sync) && + (((mode->flags & DRM_MODE_FLAG_NVSYNC) && + (loop->flags & PVSync)) || + ((mode->flags & DRM_MODE_FLAG_PVSYNC) && + (loop->flags & NVSync)) || + ((mode->flags & DRM_MODE_FLAG_NHSYNC) && + (loop->flags & PHSync)) || + ((mode->flags & DRM_MODE_FLAG_PHSYNC) && + (loop->flags & NHSync)))) { + loop++; + continue; + } + if (loop->refresh_rate <= refresh_rate + && (!best || loop->refresh_rate > best->refresh_rate)) + best = loop; + loop++; + } + if (best || !check_sync) + break; + check_sync = 0; + } while (1); + if (best) + vbios_mode->enh_table = best; + + hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0; + vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0; + + adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht; + adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder; + adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder; + adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder + + vbios_mode->enh_table->hfp; + adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder + + vbios_mode->enh_table->hfp + + vbios_mode->enh_table->hsync); + + adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt; + adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder; + adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder; + adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder + + vbios_mode->enh_table->vfp; + adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder + + vbios_mode->enh_table->vfp + + vbios_mode->enh_table->vsync); + + refresh_rate_index = vbios_mode->enh_table->refresh_rate_index; + mode_id = vbios_mode->enh_table->mode_id; + + if (ast->chip == AST1180) { + /* TODO 1180 */ + } else { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); + if (vbios_mode->enh_table->flags & NewModeInfo) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, + fb->format->cpp[0] * 8); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); + + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); + } + } + + return true; +} + +static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct ast_vbios_stdtable *stdtable; + u32 i; + u8 jreg; + + /* Only 32 BPP support */ + stdtable = &vbios_stdtable[TrueCModeIndex]; + + jreg = stdtable->misc; + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); + + /* Set SEQ */ + ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03); + for (i = 0; i < 4; i++) { + jreg = stdtable->seq[i]; + if (!i) + jreg |= 0x20; + ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); + } + + /* Set CRTC */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); + for (i = 0; i < 25; i++) + ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); + + /* set AR */ + jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); + for (i = 0; i < 20; i++) { + jreg = stdtable->ar[i]; + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg); + } + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00); + + jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ); + ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20); + + /* Set GR */ + for (i = 0; i < 9; i++) + ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); +} + +static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0; + u16 temp, precache = 0; + + if ((ast->chip == AST2500) && + (vbios_mode->enh_table->flags & AST2500PreCatchCRT)) + precache = 40; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); + + temp = (mode->crtc_htotal >> 3) - 5; + if (temp & 0x100) + jregAC |= 0x01; /* HT D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); + + temp = (mode->crtc_hdisplay >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x04; /* HDE D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); + + temp = (mode->crtc_hblank_start >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x10; /* HBS D[8] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); + + temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f; + if (temp & 0x20) + jreg05 |= 0x80; /* HBE D[5] */ + if (temp & 0x40) + jregAD |= 0x01; /* HBE D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); + + temp = ((mode->crtc_hsync_start-precache) >> 3) - 1; + if (temp & 0x100) + jregAC |= 0x40; /* HRS D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); + + temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f; + if (temp & 0x20) + jregAD |= 0x04; /* HRE D[5] */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); + + /* vert timings */ + temp = (mode->crtc_vtotal) - 2; + if (temp & 0x100) + jreg07 |= 0x01; + if (temp & 0x200) + jreg07 |= 0x20; + if (temp & 0x400) + jregAE |= 0x01; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); + + temp = (mode->crtc_vsync_start) - 1; + if (temp & 0x100) + jreg07 |= 0x04; + if (temp & 0x200) + jreg07 |= 0x80; + if (temp & 0x400) + jregAE |= 0x08; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); + + temp = (mode->crtc_vsync_end - 1) & 0x3f; + if (temp & 0x10) + jregAE |= 0x20; + if (temp & 0x20) + jregAE |= 0x40; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); + + temp = mode->crtc_vdisplay - 1; + if (temp & 0x100) + jreg07 |= 0x02; + if (temp & 0x200) + jreg07 |= 0x40; + if (temp & 0x400) + jregAE |= 0x02; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); + + temp = mode->crtc_vblank_start - 1; + if (temp & 0x100) + jreg07 |= 0x08; + if (temp & 0x200) + jreg09 |= 0x20; + if (temp & 0x400) + jregAE |= 0x04; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); + + temp = mode->crtc_vblank_end - 1; + if (temp & 0x100) + jregAE |= 0x10; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); + + if (precache) + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); + else + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); +} + +static void ast_set_offset_reg(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + const struct drm_framebuffer *fb = crtc->primary->fb; + + u16 offset; + + offset = fb->pitches[0] >> 3; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); +} + +static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = dev->dev_private; + const struct ast_vbios_dclk_info *clk_info; + + if (ast->chip == AST2500) + clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index]; + else + clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, + (clk_info->param3 & 0xc0) | + ((clk_info->param3 & 0x3) << 4)); +} + +static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = crtc->dev->dev_private; + u8 jregA0 = 0, jregA3 = 0, jregA8 = 0; + + /* 32 BPP */ + jregA0 = 0x70; + jregA3 = 0x08; + jregA8 = 0x02; + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); + + /* Set Threshold */ + if (ast->chip == AST2300 || ast->chip == AST2400 || + ast->chip == AST2500) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); + } else if (ast->chip == AST2100 || + ast->chip == AST1100 || + ast->chip == AST2200 || + ast->chip == AST2150) { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); + } else { + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); + } +} + +static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode, + struct ast_vbios_mode_info *vbios_mode) +{ + struct ast_private *ast = dev->dev_private; + u8 jreg; + + jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ); + jreg &= ~0xC0; + if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80; + if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40; + ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg); +} + +static void ast_set_start_address_crt1(struct ast_private *ast, u32 offset) +{ + u32 addr; + + addr = offset >> 2; + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); + ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); +} + +static int ast_crtc_do_set_base(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + u64 gpu_addr; + + /* PCI BAR 0 */ + struct resource *res = find_resource(crtc->dev->pdev, 0x10); + if (!res) { + dev_err(dev->pdev, "BAR0 resource not found.\n"); + return -EIO; + } + + gpu_addr = (uintptr_t)res2mmio(res, 0, 0); + + ast_set_offset_reg(crtc); + ast_set_start_address_crt1(ast, (u32)gpu_addr); + + return 0; +} + +static int ast_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = crtc->dev; + struct ast_private *ast = crtc->dev->dev_private; + struct ast_vbios_mode_info vbios_mode; + bool ret; + if (ast->chip == AST1180) { + dev_err(dev->pdev, "AST 1180 modesetting not supported\n"); + return -EINVAL; + } + + /* DPMS, set on */ + ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); + if (ast->tx_chip_type == AST_TX_DP501) + ast_set_dp501_video_output(crtc->dev, 1); + ast_crtc_load_lut(crtc); + + /* Get mode */ + ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode); + if (ret == false) { + dev_err(dev->pdev, "Failed to find compatible vbios mode\n"); + return -EINVAL; + } + ast_open_key(ast); + + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); + + ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_offset_reg(crtc); + ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); + ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode); + ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); + + ast_crtc_do_set_base(crtc); + + /* Commit changes */ + + ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); + ast_crtc_load_lut(crtc); + + return 0; +} + +static int ast_get_modes(struct drm_connector *connector, struct edid *out) +{ + struct ast_private *ast = connector->dev->dev_private; + u8 edid[128]; + + bool flags = false; + if (ast->tx_chip_type == AST_TX_DP501) { + ast->dp501_maxclk = 0xff; + flags = ast_dp501_read_edid(connector->dev, (u8 *)edid); + if (flags) + ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev); + else + dev_err(dev->pdev, "I2C transmission error\n"); + } + + if (!flags) { + ast_software_i2c_read(CONFIG_DRIVERS_ASPEED_I2C_BUS, ast, edid); + } + if (decode_edid(edid, sizeof(edid), out) != EDID_CONFORMANT) { + dev_err(dev->pdev, "Failed to decode EDID\n"); + return -EIO; + } + + return 0; +} + +static enum drm_mode_status ast_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct ast_private *ast = connector->dev->dev_private; + int flags = MODE_NOMODE; + uint32_t jtemp; + + if (ast->support_wide_screen) { + if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050)) + return MODE_OK; + if ((mode->hdisplay == 1280) && (mode->vdisplay == 800)) + return MODE_OK; + if ((mode->hdisplay == 1440) && (mode->vdisplay == 900)) + return MODE_OK; + if ((mode->hdisplay == 1360) && (mode->vdisplay == 768)) + return MODE_OK; + if ((mode->hdisplay == 1600) && (mode->vdisplay == 900)) + return MODE_OK; + + if ((ast->chip == AST2100) || (ast->chip == AST2200) || + (ast->chip == AST2300) || (ast->chip == AST2400) || + (ast->chip == AST2500) || (ast->chip == AST1180)) { + if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080)) + return MODE_OK; + + if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) { + jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); + if (jtemp & 0x01) + return MODE_NOMODE; + else + return MODE_OK; + } + } + } + switch (mode->hdisplay) { + case 640: + if (mode->vdisplay == 480) flags = MODE_OK; + break; + case 800: + if (mode->vdisplay == 600) flags = MODE_OK; + break; + case 1024: + if (mode->vdisplay == 768) flags = MODE_OK; + break; + case 1280: + if (mode->vdisplay == 1024) flags = MODE_OK; + break; + case 1600: + if (mode->vdisplay == 1200) flags = MODE_OK; + break; + default: + return flags; + } + + return flags; +} + +static void ast_edid_to_drmmode(struct edid *edid, struct drm_display_mode *mode) +{ + memset(mode, 0, sizeof(*mode)); + + mode->hdisplay = edid->mode.ha; + mode->vdisplay = edid->mode.va; + mode->crtc_hdisplay = edid->mode.ha; + mode->crtc_vdisplay = edid->mode.va; + + mode->clock = edid->mode.pixel_clock; + mode->vrefresh = edid->mode.refresh; + + mode->crtc_hblank_start = edid->mode.ha + edid->mode.hso; + mode->crtc_hblank_end = edid->mode.ha + edid->mode.hso + edid->mode.hbl; + mode->crtc_hsync_start = edid->mode.ha + edid->mode.hso; + mode->crtc_hsync_end = edid->mode.ha + edid->mode.hso + edid->mode.hspw; + mode->crtc_htotal = MAX(mode->crtc_hblank_end, mode->crtc_hsync_end); + + mode->crtc_vblank_start = edid->mode.va + edid->mode.vso; + mode->crtc_vblank_end = edid->mode.va + edid->mode.vso + edid->mode.vbl; + mode->crtc_vsync_start = edid->mode.va + edid->mode.vso; + mode->crtc_vsync_end = edid->mode.va + edid->mode.vso + edid->mode.vspw; + mode->crtc_vtotal = MAX(mode->crtc_vblank_end, mode->crtc_vsync_end); + + mode->flags = 0; + if (edid->mode.phsync == '+') + mode->flags |= DRM_MODE_FLAG_PHSYNC; + else + mode->flags |= DRM_MODE_FLAG_NHSYNC; + + if (edid->mode.pvsync == '+') + mode->flags |= DRM_MODE_FLAG_PVSYNC; + else + mode->flags |= DRM_MODE_FLAG_NVSYNC; +} + +static int ast_select_mode(struct drm_connector *connector, + struct edid *edid, struct drm_display_mode *mode) +{ + bool widescreen; + int ret; + + ret = ast_get_modes(connector, edid); + if (ret) { + dev_err(dev->pdev, "Failed to get mode from EDID\n"); + return ret; + } + printk(BIOS_DEBUG, "Display has %dpx x %dpx\n", edid->mode.ha, edid->mode.va); + + widescreen = !!(((edid->mode.ha * 4) % (edid->mode.va * 3))); + + do { + /* Select a compatible smaller mode */ + if (edid->mode.ha > 1920 && widescreen) { + edid->mode.ha = 1920; + edid->mode.va = 1080; + } else if (edid->mode.ha >= 1920 && widescreen) { + edid->mode.ha = 1680; + edid->mode.va = 1050; + } else if (edid->mode.ha >= 1680 && widescreen) { + edid->mode.ha = 1600; + edid->mode.va = 900; + } else if (edid->mode.ha >= 1680 && !widescreen) { + edid->mode.ha = 1600; + edid->mode.va = 1200; + } else if (edid->mode.ha >= 1600 && widescreen) { + edid->mode.ha = 1440; + edid->mode.va = 900; + } else if (edid->mode.ha >= 1440 && widescreen) { + edid->mode.ha = 1360; + edid->mode.va = 768; + } else if (edid->mode.ha >= 1360 && widescreen) { + edid->mode.ha = 1280; + edid->mode.va = 800; + } else if (edid->mode.ha >= 1360 && !widescreen) { + edid->mode.ha = 1280; + edid->mode.va = 1024; + } else if (edid->mode.ha >= 1280) { + edid->mode.ha = 1024; + edid->mode.va = 768; + } else if (edid->mode.ha >= 1024) { + edid->mode.ha = 800; + edid->mode.va = 600; + } else if (edid->mode.ha >= 800) { + edid->mode.ha = 640; + edid->mode.va = 480; + } else { + dev_err(dev->pdev, "No compatible mode found.\n"); + + return -EIO; + } + + ast_edid_to_drmmode(edid, mode); + + } while (ast_mode_valid(connector, mode) != MODE_OK); + + /* Update EDID info */ + edid->x_resolution = edid->mode.ha; + edid->y_resolution = edid->mode.va; + edid->bytes_per_line = ALIGN_UP(edid->x_resolution * 4, 8); + + printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d\n", + edid->x_resolution, edid->y_resolution, edid->bytes_per_line); + + return 0; +} + +static void ast_hide_cursor(struct drm_crtc *crtc) +{ + struct ast_private *ast = crtc->dev->dev_private; + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00); +} + +int ast_driver_framebuffer_init(struct drm_device *dev, int flags) +{ + struct drm_display_mode adjusted_mode; + struct drm_crtc crtc; + struct drm_format format; + struct drm_primary primary; + struct drm_framebuffer fb; + struct drm_connector connector; + struct edid edid; + int ret; + + /* Init structs */ + connector.dev = dev; + + format.cpp[0] = 4; /* 32 BPP */ + fb.format = &format; + + primary.fb = &fb; + + crtc.dev = dev; + crtc.primary = &primary; + + /* Init I2C */ + ast_software_i2c_init(CONFIG_DRIVERS_ASPEED_I2C_BUS); + + /* Read EDID and find mode */ + ret = ast_select_mode(&connector, &edid, &crtc.mode); + if (ret) { + dev_err(dev->pdev, "Failed to select mode.\n"); + return ret; + } + + fb.pitches[0] = edid.bytes_per_line; + + memcpy(&adjusted_mode, &crtc.mode, sizeof(crtc.mode)); + + ret = ast_crtc_mode_set(&crtc, &crtc.mode, &adjusted_mode); + if (ret) { + dev_err(dev->pdev, "Failed to set mode.\n"); + return ret; + } + + ast_hide_cursor(&crtc); + + /* Advertise new mode */ + + /* PCI BAR 0 */ + struct resource *res = find_resource(dev->pdev, 0x10); + if (!res) { + dev_err(dev->pdev, "BAR0 resource not found.\n"); + return -EIO; + } + uintptr_t gpu_addr = (uintptr_t)res2mmio(res, 0, 0); + + edid.framebuffer_bits_per_pixel = 32; /* 32 BPP */ + set_vbe_mode_info_valid(&edid, gpu_addr); + + /* Clear display */ + memset((void *)gpu_addr, 0, edid.bytes_per_line * edid.y_resolution); + + return 0; +} diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..aa54fcf 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -47,6 +47,7 @@ #define SyncPN (PVSync | NHSync) #define SyncNP (NVSync | PHSync) #define SyncNN (NVSync | NHSync) +#define AST2500PreCatchCRT 0x00004000 /* DCLK Index */ #define VCLK25_175 0x00 @@ -108,80 +109,110 @@ {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ }; +static const struct ast_vbios_dclk_info dclk_table_ast2500[] = { + {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ + {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ + {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ + {0x76, 0x63, 0x01}, /* 03: VCLK36 */ + {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ + {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ + {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ + {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ + {0x80, 0x64, 0x00}, /* 08: VCLK65 */ + {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ + {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ + {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ + {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ + {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ + {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ + {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ + {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ + {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ + {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ + {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ + {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ + {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ + {0x58, 0x01, 0x42}, /* 17: VCLK119 */ + {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ + {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ + {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ +}; + static struct ast_vbios_stdtable vbios_stdtable[] = { /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, - 0xff} + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, + 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, + 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, + 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, - 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, - 0xff} + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, + 0xff}, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, + 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; -static struct ast_vbios_enhtable res_640x480[] = { +static const struct ast_vbios_enhtable res_640x480[] = { { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ @@ -194,7 +225,7 @@ (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, }; -static struct ast_vbios_enhtable res_800x600[] = { +static const struct ast_vbios_enhtable res_800x600[] = { {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ (SyncPP | Charx8Dot), 56, 1, 0x30 }, {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ @@ -210,7 +241,7 @@ }; -static struct ast_vbios_enhtable res_1024x768[] = { +static const struct ast_vbios_enhtable res_1024x768[] = { {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ (SyncNN | Charx8Dot), 60, 1, 0x31 }, {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ @@ -223,7 +254,7 @@ (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, }; -static struct ast_vbios_enhtable res_1280x1024[] = { +static const struct ast_vbios_enhtable res_1280x1024[] = { {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x32 }, {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ @@ -234,7 +265,7 @@ (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, }; -static struct ast_vbios_enhtable res_1600x1200[] = { +static const struct ast_vbios_enhtable res_1600x1200[] = { {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ (SyncPP | Charx8Dot), 60, 1, 0x33 }, {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ @@ -242,34 +273,39 @@ }; /* 16:9 */ -static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ +static const struct ast_vbios_enhtable res_1360x768[] = { + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ - (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x39 }, }; -static struct ast_vbios_enhtable res_1600x900[] = { - {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ +static const struct ast_vbios_enhtable res_1600x900[] = { + {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x3A }, + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; -static struct ast_vbios_enhtable res_1920x1080[] = { +static const struct ast_vbios_enhtable res_1920x1080[] = { {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x38 }, {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; /* 16:10 */ -static struct ast_vbios_enhtable res_1280x800[] = { +static const struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ @@ -277,29 +313,32 @@ }; -static struct ast_vbios_enhtable res_1440x900[] = { +static const struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; -static struct ast_vbios_enhtable res_1680x1050[] = { +static const struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -static struct ast_vbios_enhtable res_1920x1200[] = { +static const struct ast_vbios_enhtable res_1920x1200[] = { {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, - {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 60, 1, 0x34 }, + {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | + AST2500PreCatchCRT), 0xFF, 1, 0x34 }, }; - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7803566b64158405efc04a39f80a0ec98b44e646 Gerrit-Change-Number: 35726 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 42

Change in ...coreboot[master]: nb/i945: Consolidate sdram_setup_processor_side()
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33781 Change subject: nb/i945: Consolidate sdram_setup_processor_side() ...................................................................... nb/i945: Consolidate sdram_setup_processor_side() Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33781/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 281e7b2..c994786 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2695,13 +2695,11 @@ static void sdram_setup_processor_side(void) { - if (i945_silicon_revision() == 0) + if (i945_silicon_revision() == 0) { MCHBAR32(FSBPMC3) |= (1 << 2); - - MCHBAR8(0xb00) |= 1; - - if (i945_silicon_revision() == 0) MCHBAR32(SLPCTL) |= (1 << 8); + } + MCHBAR8(0xb00) |= 1; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/33781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Gerrit-Change-Number: 33781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/intel/i440bx: Remove never used 'dra' value
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34558 ) Change subject: nb/intel/i440bx: Remove never used 'dra' value ...................................................................... nb/intel/i440bx: Remove never used 'dra' value Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34558/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7..3a1b66a 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -799,7 +799,6 @@ } /* "DRA" is our RPS for the two rows on this DIMM. */ - dra = 0; /* Columns */ col = spd_read_byte(device, SPD_NUM_COLUMNS); -- To view, visit https://review.coreboot.org/c/coreboot/+/34558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Gerrit-Change-Number: 34558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34434 ) Change subject: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT ...................................................................... nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT Found-by: scan-build 7.0.1-8 Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/gma.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34434/1 diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 61731fe..6577153 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -68,9 +68,8 @@ /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); - int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/34434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Gerrit-Change-Number: 34434 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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