Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33129
Change subject: soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor
......................................................................
soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFA.
Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/include/soc/iomap.h
A src/soc/intel/cannonlake/include/soc/thermal.h
A src/soc/intel/cannonlake/thermal.c
6 files changed, 147 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33129/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 1328944..03faa3c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -53,6 +53,7 @@
ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c
+ramstage-y += thermal.c
ramstage-y += uart.c
ramstage-y += vr_config.c
ramstage-y += sd.c
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 0d51c1c..39f808b 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -421,6 +421,9 @@
* Bit 0: MISCCFG_GPDLCGEN
*/
uint8_t gpio_pm[TOTAL_GPIO_COMM];
+
+ /* PCH Trip Temperature */
+ uint8_t pch_trip_temp;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 4dfd15b..d277658 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -32,6 +32,7 @@
#include <soc/pm.h>
#include <soc/smbus.h>
#include <soc/systemagent.h>
+#include <soc/thermal.h>
#include <stdlib.h>
#include "chip.h"
@@ -63,6 +64,16 @@
uint8_t reg8;
tco_lockdown();
+
+ /*
+ * Set low maximum temp value used for dynamic thermal sensor
+ * shutdown consideration.
+ *
+ * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+ * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
+ */
+ pch_thermal_configuration();
+
/*
* Disable ACPI PM timer based on dt policy
*
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 100bd11..488d938 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -76,6 +76,8 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
+#define THERMAL_BASE_ADDRESS 0xfe600000
+
#define VTD_BASE_ADDRESS 0xFED90000
#define VTD_BASE_SIZE 0x00004000
/*
diff --git a/src/soc/intel/cannonlake/include/soc/thermal.h b/src/soc/intel/cannonlake/include/soc/thermal.h
new file mode 100644
index 0000000..1f4085c
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/thermal.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_THERMAL_H_
+#define _SOC_THERMAL_H_
+
+#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c
+
+/* Enable thermal sensor power management */
+void pch_thermal_configuration(void);
+
+#endif
diff --git a/src/soc/intel/cannonlake/thermal.c b/src/soc/intel/cannonlake/thermal.c
new file mode 100644
index 0000000..9d62843
--- /dev/null
+++ b/src/soc/intel/cannonlake/thermal.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/thermal.h>
+
+#include "chip.h"
+
+#define MAX_TRIP_TEMP 205
+#define DEFAULT_TRIP_TEMP 50
+
+static void *pch_thermal_get_bar(struct device *dev)
+{
+ uintptr_t bar;
+
+ bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ /*
+ * Bits [31:12] are the base address as per EDS for Thermal Device,
+ * Don't care about [11:0] bits
+ */
+ return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
+}
+
+static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar)
+{
+ uint8_t pcireg;
+
+ /* Assign Resources to Thermal Device */
+ /* Clear BIT 1-2 of Command Register */
+ pcireg = pci_read_config8(dev, PCI_COMMAND);
+ pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config8(dev, PCI_COMMAND, pcireg);
+
+ /* Program Temporary BAR for Thermal Device */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
+
+ /* Enable Bus Master and MMIO Space */
+ pcireg = pci_read_config8(dev, PCI_COMMAND);
+ pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config8(dev, PCI_COMMAND, pcireg);
+}
+
+/* PCH Low Temp Threshold (LTT) */
+static uint16_t pch_get_ltt_value(struct device *dev)
+{
+ static struct soc_intel_skylake_config *config;
+ uint16_t ltt_value;
+ uint16_t trip_temp = DEFAULT_TRIP_TEMP;
+
+ config = dev->chip_info;
+
+ if (config->pch_trip_temp)
+ trip_temp = config->pch_trip_temp;
+
+ if (trip_temp > MAX_TRIP_TEMP)
+ die("Input PCH temp trip is higher than allowed range!");
+
+ /* Trip Point Temp = (LTT / 2 - 50 degree C) */
+ ltt_value = (trip_temp + 50) * 2;
+
+ return ltt_value;
+}
+
+/* Enable thermal sensor power management */
+void pch_thermal_configuration(void)
+{
+ uint16_t reg16;
+ struct device *dev = PCH_DEV_THERMAL;
+ if (!dev) {
+ printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n");
+ return;
+ }
+ void *thermalbar = pch_thermal_get_bar(dev);
+
+ /* Use default pre-ram bar */
+ if (!thermalbar) {
+ pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS);
+ thermalbar = (void *)THERMAL_BASE_ADDRESS;
+ }
+
+ /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
+ reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT);
+ reg16 &= ~0x1ff;
+ /* Low Temp Threshold (LTT) */
+ reg16 |= pch_get_ltt_value(dev);
+ write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Gerrit-Change-Number: 33129
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-MessageType: newchange
Prasun Gera has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35431 )
Change subject: src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU
......................................................................
src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU
Both T530 and W530 share the same PCI device id of 0166 for the iGPU.
Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a
Signed-off-by: Prasun Gera <prasun.gera(a)gmail.com>
---
M src/mainboard/lenovo/t530/Kconfig
1 file changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35431/1
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index f63a120..4fcbcb5 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -60,7 +60,10 @@
config VGA_BIOS_FILE
string
- default "pci8086,0106.rom" if BOARD_LENOVO_T530
- default "pci8086,0166.rom" if BOARD_LENOVO_W530
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a
Gerrit-Change-Number: 35431
Gerrit-PatchSet: 1
Gerrit-Owner: Prasun Gera
Gerrit-MessageType: newchange
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931
Change subject: soc/intel/denverton_ns: Allow using FSP repo
......................................................................
soc/intel/denverton_ns: Allow using FSP repo
Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/soc/intel/denverton_ns/Kconfig
2 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 8156d18..6f5ed2a 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -85,7 +85,8 @@
bool "Use the IntelFSP based binaries"
depends on ADD_FSP_BINARIES
depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
- SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE
+ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
+ SOC_INTEL_DENVERTON_NS
help
When selecting this option, the SoC must set FSP_HEADER_PATH
and FSP_FD_PATH correctly so FSP splitting works.
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 1096549..dfb5c37 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -78,6 +78,16 @@
help
The memory location of the Intel FSP-S binary for this platform.
+config FSP_HEADER_PATH
+ string "Location of FSP headers"
+ depends on MAINBOARD_USES_FSP2_0
+ default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/"
+
+config FSP_FD_PATH
+ string
+ depends on FSP_USE_REPO
+ default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd"
+
# CAR memory layout on DENVERTON_NS hardware:
## CAR base address - 0xfef00000
## CAR size 1MB - 0x100 (0xfff00)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Gerrit-Change-Number: 30931
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384
Change subject: README: Spell Web site with one space
......................................................................
README: Spell Web site with one space
Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M payloads/libpayload/README
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1
diff --git a/payloads/libpayload/README b/payloads/libpayload/README
index fdf9b18..7348934 100644
--- a/payloads/libpayload/README
+++ b/payloads/libpayload/README
@@ -49,10 +49,10 @@
Please see the sample/ directory for details.
-Website and Mailing List
+Web site and Mailing List
------------------------
-The main website is https://www.coreboot.org/Libpayload.
+The main web site is https://www.coreboot.org/Libpayload.
For additional information, patches, and discussions, please join the
coreboot mailing list at https://www.coreboot.org/Mailinglist, where most
--
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Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
Gerrit-Change-Number: 31384
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange