Change in coreboot[master]: [WIP] soc/intel: Refactor device ACPI names
by Kyösti Mälkki (Code Review) 08 Feb '20
by Kyösti Mälkki (Code Review) 08 Feb '20
08 Feb '20
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35736 )
Change subject: [WIP] soc/intel: Refactor device ACPI names
......................................................................
[WIP] soc/intel: Refactor device ACPI names
Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/fsp_broadwell_de/southcluster.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/skylake/acpi.c
5 files changed, 21 insertions(+), 237 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35736/1
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 8e516f8..e53bb0c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -147,65 +147,10 @@
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
- switch (dev->path.pci.devfn) {
- /* DSDT: acpi/northbridge.asl */
- case SA_DEVFN_ROOT:
- return "MCHC";
- /* DSDT: acpi/lpc.asl */
- case PCH_DEVFN_LPC:
- return "LPCB";
- /* DSDT: acpi/xhci.asl */
- case PCH_DEVFN_XHCI:
- return "XHCI";
- /* DSDT: acpi/pch_hda.asl */
- case PCH_DEVFN_HDA:
- return "HDAS";
- /* DSDT: acpi/lpss.asl */
- case PCH_DEVFN_UART0:
- return "URT1";
- case PCH_DEVFN_UART1:
- return "URT2";
- case PCH_DEVFN_UART2:
- return "URT3";
- case PCH_DEVFN_UART3:
- return "URT4";
- case PCH_DEVFN_SPI0:
- return "SPI1";
- case PCH_DEVFN_SPI1:
- return "SPI2";
- case PCH_DEVFN_SPI2:
- return "SPI3";
- case PCH_DEVFN_PWM:
- return "PWM";
- case PCH_DEVFN_I2C0:
- return "I2C0";
- case PCH_DEVFN_I2C1:
- return "I2C1";
- case PCH_DEVFN_I2C2:
- return "I2C2";
- case PCH_DEVFN_I2C3:
- return "I2C3";
- case PCH_DEVFN_I2C4:
- return "I2C4";
- case PCH_DEVFN_I2C5:
- return "I2C5";
- case PCH_DEVFN_I2C6:
- return "I2C6";
- case PCH_DEVFN_I2C7:
- return "I2C7";
- /* Storage */
- case PCH_DEVFN_SDCARD:
- return "SDCD";
- case PCH_DEVFN_EMMC:
- return "EMMC";
- case PCH_DEVFN_SDIO:
- return "SDIO";
- /* PCIe */
- case PCH_DEVFN_PCIE1:
- return "RP03";
- case PCH_DEVFN_PCIE5:
- return "RP01";
- }
+#if 0
+ /* FIXME dev->acpi_name */
+ return dev->acpi_name;
+#endif
return NULL;
}
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0ce2f1a..1754964 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -74,66 +74,10 @@
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
- switch (dev->path.pci.devfn) {
- case SA_DEVFN_ROOT: return "MCHC";
- case SA_DEVFN_IGD: return "GFX0";
- case PCH_DEVFN_ISH: return "ISHB";
- case PCH_DEVFN_XHCI: return "XHCI";
- case PCH_DEVFN_USBOTG: return "XDCI";
- case PCH_DEVFN_THERMAL: return "THRM";
- case PCH_DEVFN_I2C0: return "I2C0";
- case PCH_DEVFN_I2C1: return "I2C1";
- case PCH_DEVFN_I2C2: return "I2C2";
- case PCH_DEVFN_I2C3: return "I2C3";
- case PCH_DEVFN_CSE: return "CSE1";
- case PCH_DEVFN_CSE_2: return "CSE2";
- case PCH_DEVFN_CSE_IDER: return "CSED";
- case PCH_DEVFN_CSE_KT: return "CSKT";
- case PCH_DEVFN_CSE_3: return "CSE3";
- case PCH_DEVFN_SATA: return "SATA";
- case PCH_DEVFN_UART2: return "UAR2";
- case PCH_DEVFN_I2C4: return "I2C4";
- case PCH_DEVFN_I2C5: return "I2C5";
- case PCH_DEVFN_PCIE1: return "RP01";
- case PCH_DEVFN_PCIE2: return "RP02";
- case PCH_DEVFN_PCIE3: return "RP03";
- case PCH_DEVFN_PCIE4: return "RP04";
- case PCH_DEVFN_PCIE5: return "RP05";
- case PCH_DEVFN_PCIE6: return "RP06";
- case PCH_DEVFN_PCIE7: return "RP07";
- case PCH_DEVFN_PCIE8: return "RP08";
- case PCH_DEVFN_PCIE9: return "RP09";
- case PCH_DEVFN_PCIE10: return "RP10";
- case PCH_DEVFN_PCIE11: return "RP11";
- case PCH_DEVFN_PCIE12: return "RP12";
- case PCH_DEVFN_PCIE13: return "RP13";
- case PCH_DEVFN_PCIE14: return "RP14";
- case PCH_DEVFN_PCIE15: return "RP15";
- case PCH_DEVFN_PCIE16: return "RP16";
- case PCH_DEVFN_PCIE17: return "RP17";
- case PCH_DEVFN_PCIE18: return "RP18";
- case PCH_DEVFN_PCIE19: return "RP19";
- case PCH_DEVFN_PCIE20: return "RP20";
- case PCH_DEVFN_PCIE21: return "RP21";
- case PCH_DEVFN_PCIE22: return "RP22";
- case PCH_DEVFN_PCIE23: return "RP23";
- case PCH_DEVFN_PCIE24: return "RP24";
- case PCH_DEVFN_UART0: return "UAR0";
- case PCH_DEVFN_UART1: return "UAR1";
- case PCH_DEVFN_GSPI0: return "SPI0";
- case PCH_DEVFN_GSPI1: return "SPI1";
- case PCH_DEVFN_GSPI2: return "SPI2";
- case PCH_DEVFN_EMMC: return "EMMC";
- case PCH_DEVFN_SDCARD: return "SDXC";
- case PCH_DEVFN_LPC: return "LPCB";
- case PCH_DEVFN_P2SB: return "P2SB";
- case PCH_DEVFN_PMC: return "PMC_";
- case PCH_DEVFN_HDA: return "HDAS";
- case PCH_DEVFN_SMBUS: return "SBUS";
- case PCH_DEVFN_SPI: return "FSPI";
- case PCH_DEVFN_GBE: return "IGBE";
- case PCH_DEVFN_TRACEHUB:return "THUB";
- }
+#if 0
+ /* FIXME dev->acpi_name */
+ return dev->acpi_name;
+#endif
return NULL;
}
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c
index 31dcc25..2ad5f52 100644
--- a/src/soc/intel/fsp_broadwell_de/southcluster.c
+++ b/src/soc/intel/fsp_broadwell_de/southcluster.c
@@ -280,10 +280,11 @@
#if CONFIG(HAVE_ACPI_TABLES)
static const char *lpc_acpi_name(const struct device *dev)
{
- if (dev->path.pci.devfn == PCH_DEVFN_LPC)
- return "LPC0";
- else
- return NULL;
+#if 0
+ /* FIXME dev->acpi_name */
+ return dev->acpi_name;
+#endif
+ return NULL;
}
#endif
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index 2bb908c..956f35f 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -37,67 +37,10 @@
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
- switch (dev->path.pci.devfn) {
- case SA_DEVFN_ROOT: return "MCHC";
- case SA_DEVFN_IGD: return "GFX0";
- case PCH_DEVFN_ISH: return "ISHB";
- case PCH_DEVFN_XHCI: return "XHCI";
- case PCH_DEVFN_USBOTG: return "XDCI";
- case PCH_DEVFN_THERMAL: return "THRM";
- case PCH_DEVFN_I2C0: return "I2C0";
- case PCH_DEVFN_I2C1: return "I2C1";
- case PCH_DEVFN_I2C2: return "I2C2";
- case PCH_DEVFN_I2C3: return "I2C3";
- case PCH_DEVFN_CSE: return "CSE1";
- case PCH_DEVFN_CSE_2: return "CSE2";
- case PCH_DEVFN_CSE_IDER: return "CSED";
- case PCH_DEVFN_CSE_KT: return "CSKT";
- case PCH_DEVFN_CSE_3: return "CSE3";
- case PCH_DEVFN_SATA: return "SATA";
- case PCH_DEVFN_UART2: return "UAR2";
- case PCH_DEVFN_I2C4: return "I2C4";
- case PCH_DEVFN_I2C5: return "I2C5";
- case PCH_DEVFN_PCIE1: return "RP01";
- case PCH_DEVFN_PCIE2: return "RP02";
- case PCH_DEVFN_PCIE3: return "RP03";
- case PCH_DEVFN_PCIE4: return "RP04";
- case PCH_DEVFN_PCIE5: return "RP05";
- case PCH_DEVFN_PCIE6: return "RP06";
- case PCH_DEVFN_PCIE7: return "RP07";
- case PCH_DEVFN_PCIE8: return "RP08";
- case PCH_DEVFN_PCIE9: return "RP09";
- case PCH_DEVFN_PCIE10: return "RP10";
- case PCH_DEVFN_PCIE11: return "RP11";
- case PCH_DEVFN_PCIE12: return "RP12";
- case PCH_DEVFN_PCIE13: return "RP13";
- case PCH_DEVFN_PCIE14: return "RP14";
- case PCH_DEVFN_PCIE15: return "RP15";
- case PCH_DEVFN_PCIE16: return "RP16";
- case PCH_DEVFN_PCIE17: return "RP17";
- case PCH_DEVFN_PCIE18: return "RP18";
- case PCH_DEVFN_PCIE19: return "RP19";
- case PCH_DEVFN_PCIE20: return "RP20";
- case PCH_DEVFN_PCIE21: return "RP21";
- case PCH_DEVFN_PCIE22: return "RP22";
- case PCH_DEVFN_PCIE23: return "RP23";
- case PCH_DEVFN_PCIE24: return "RP24";
- case PCH_DEVFN_UART0: return "UAR0";
- case PCH_DEVFN_UART1: return "UAR1";
- case PCH_DEVFN_GSPI0: return "SPI0";
- case PCH_DEVFN_GSPI1: return "SPI1";
- case PCH_DEVFN_GSPI2: return "SPI2";
- case PCH_DEVFN_EMMC: return "EMMC";
- case PCH_DEVFN_SDCARD: return "SDXC";
- /* Keeping ACPI device name coherent with ec.asl */
- case PCH_DEVFN_ESPI: return "LPCB";
- case PCH_DEVFN_P2SB: return "P2SB";
- case PCH_DEVFN_PMC: return "PMC_";
- case PCH_DEVFN_HDA: return "HDAS";
- case PCH_DEVFN_SMBUS: return "SBUS";
- case PCH_DEVFN_SPI: return "FSPI";
- case PCH_DEVFN_GBE: return "IGBE";
- case PCH_DEVFN_TRACEHUB:return "THUB";
- }
+#if 0
+ /* FIXME dev->acpi_name */
+ return dev->acpi_name;
+#endif
return NULL;
}
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 43f9c39..45756b3 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -760,59 +760,10 @@
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
- switch (dev->path.pci.devfn) {
- case SA_DEVFN_ROOT: return "MCHC";
- case SA_DEVFN_IGD: return "GFX0";
- case PCH_DEVFN_ISH: return "ISHB";
- case PCH_DEVFN_XHCI: return "XHCI";
- case PCH_DEVFN_USBOTG: return "XDCI";
- case PCH_DEVFN_THERMAL: return "THRM";
- case PCH_DEVFN_CIO: return "ICIO";
- case PCH_DEVFN_I2C0: return "I2C0";
- case PCH_DEVFN_I2C1: return "I2C1";
- case PCH_DEVFN_I2C2: return "I2C2";
- case PCH_DEVFN_I2C3: return "I2C3";
- case PCH_DEVFN_CSE: return "CSE1";
- case PCH_DEVFN_CSE_2: return "CSE2";
- case PCH_DEVFN_CSE_IDER: return "CSED";
- case PCH_DEVFN_CSE_KT: return "CSKT";
- case PCH_DEVFN_CSE_3: return "CSE3";
- case PCH_DEVFN_SATA: return "SATA";
- case PCH_DEVFN_UART2: return "UAR2";
- case PCH_DEVFN_I2C4: return "I2C4";
- case PCH_DEVFN_I2C5: return "I2C5";
- case PCH_DEVFN_PCIE1: return "RP01";
- case PCH_DEVFN_PCIE2: return "RP02";
- case PCH_DEVFN_PCIE3: return "RP03";
- case PCH_DEVFN_PCIE4: return "RP04";
- case PCH_DEVFN_PCIE5: return "RP05";
- case PCH_DEVFN_PCIE6: return "RP06";
- case PCH_DEVFN_PCIE7: return "RP07";
- case PCH_DEVFN_PCIE8: return "RP08";
- case PCH_DEVFN_PCIE9: return "RP09";
- case PCH_DEVFN_PCIE10: return "RP10";
- case PCH_DEVFN_PCIE11: return "RP11";
- case PCH_DEVFN_PCIE12: return "RP12";
- case PCH_DEVFN_PCIE13: return "RP13";
- case PCH_DEVFN_PCIE14: return "RP14";
- case PCH_DEVFN_PCIE15: return "RP15";
- case PCH_DEVFN_PCIE16: return "RP16";
- case PCH_DEVFN_UART0: return "UAR0";
- case PCH_DEVFN_UART1: return "UAR1";
- case PCH_DEVFN_GSPI0: return "SPI0";
- case PCH_DEVFN_GSPI1: return "SPI1";
- case PCH_DEVFN_EMMC: return "EMMC";
- case PCH_DEVFN_SDIO: return "SDIO";
- case PCH_DEVFN_SDCARD: return "SDXC";
- case PCH_DEVFN_LPC: return "LPCB";
- case PCH_DEVFN_P2SB: return "P2SB";
- case PCH_DEVFN_PMC: return "PMC_";
- case PCH_DEVFN_HDA: return "HDAS";
- case PCH_DEVFN_SMBUS: return "SBUS";
- case PCH_DEVFN_SPI: return "FSPI";
- case PCH_DEVFN_GBE: return "IGBE";
- case PCH_DEVFN_TRACEHUB:return "THUB";
- }
+#if 0
+ /* FIXME dev->acpi_name */
+ return dev->acpi_name;
+#endif
return NULL;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0f2ee991efbd0911dfce5fdf5c5d92de9b7cc652
Gerrit-Change-Number: 35736
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
4
7
Change in coreboot[master]: trogdor: support mbn_version 6 with python build scripts
by mturney mturney (Code Review) 07 Feb '20
by mturney mturney (Code Review) 07 Feb '20
07 Feb '20
mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35506 )
Change subject: trogdor: support mbn_version 6 with python build scripts
......................................................................
trogdor: support mbn_version 6 with python build scripts
Developer/Reviewer, be aware of this patch from Mistral:
https://review.coreboot.org/c/coreboot/+/33425/18
Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Signed-off-by: T Michael Turney <mturney(a)codeaurora.org>
---
M util/qualcomm/createxbl.py
M util/qualcomm/mbn_tools.py
2 files changed, 90 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35506/1
diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py
index 4a21854..769e9f1e 100755
--- a/util/qualcomm/createxbl.py
+++ b/util/qualcomm/createxbl.py
@@ -44,6 +44,7 @@
#
# when who what, where, why
# -------- --- ------------------------------------------------------
+# 05/21/19 rissha Added --mbn_version to add MBN header accordingly
# 03/26/18 tv Added -e to enable extended MBNV5 support
# 09/04/15 et Added -x and -d to embed xbl_sec ELF
# 02/11/15 ck Fixed missing elf type check in ZI OOB feature
@@ -119,6 +120,10 @@
help="Removes ZI segments that have addresses greater" + \
" than 32 bits when converting from a 64 to 32 bit ELF")
+ parser.add_option("--mbn_version",
+ action="store", type="int", dest="mbn_version",
+ help="Add mbn header in elf image. '3', '5' or '6'")
+
(options, args) = parser.parse_args()
if not options.elf_inp_file1:
@@ -206,11 +211,16 @@
else:
zi_oob_enabled = True
+ header_version = 3
+
if options.elf_inp_xbl_sec:
is_ext_mbn_v5 = True
+ header_version = 5
else:
is_ext_mbn_v5 = False
+ if options.mbn_version:
+ header_version = options.mbn_version
mbn_type = 'elf'
header_format = 'reg'
@@ -259,7 +269,7 @@
source_elf,
target_hash,
elf_out_file_name = target_phdr_elf,
- secure_type = image_header_secflag)
+ secure_type = image_header_secflag, header_version = header_version )
if rv:
raise RuntimeError, "Failed to run pboot_gen_elf"
@@ -270,7 +280,8 @@
target_hash_hd,
image_header_secflag,
is_ext_mbn_v5,
- elf_file_name = source_elf)
+ elf_file_name = source_elf,
+ header_version = header_version)
if rv:
raise RuntimeError, "Failed to create image header for hash segment"
diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py
index 12dc210..079e02e 100755
--- a/util/qualcomm/mbn_tools.py
+++ b/util/qualcomm/mbn_tools.py
@@ -41,6 +41,7 @@
#
# when who what, where, why
# -------- --- ---------------------------------------------------------
+# 05/21/18 rissha Added support for extended MBNV6 and Add support for hashing elf segments with SHA384
# 03/22/18 thiru Added support for extended MBNV5.
# 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features.
# 03/18/13 dhaval Add support for hashing elf segments with SHA256 and
@@ -64,23 +65,24 @@
#----------------------------------------------------------------------------
# GLOBAL VARIABLES BEGIN
#----------------------------------------------------------------------------
-PAD_BYTE_1 = 255 # Padding byte 1s
-PAD_BYTE_0 = 0 # Padding byte 0s
-SHA256_SIGNATURE_SIZE = 256 # Support SHA256
-MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates
-MI_BOOT_IMG_HDR_SIZE = 40 # sizeof(mi_boot_image_header_type)
-MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header)
-BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements
-SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements
-FLASH_PARTI_VERSION = 3 # Flash Partition Version Number
-MAX_PHDR_COUNT = 100 # Maximum allowable program headers
-CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root
-VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON
-MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE
-MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature
+PAD_BYTE_1 = 255 # Padding byte 1s
+PAD_BYTE_0 = 0 # Padding byte 0s
+SHA256_SIGNATURE_SIZE = 256 # Support SHA256
+MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates
+MBN_HEADER_VERSION_3 = 3 # Mbn header_version 3
+MBN_HEADER_VERSION_5 = 5 # Mbn header_version 5
+MBN_HEADER_VERSION_6 = 6 # Mbn header_version 6
+MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header)
+BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements
+SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements
+MAX_PHDR_COUNT = 100 # Maximum allowable program headers
+CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root
+VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON
+MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE
+MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature
-SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image
-SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image
+SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image
+SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image
# Magic numbers filled in for boot headers
FLASH_CODE_WORD = 0x844BDCD1
@@ -528,7 +530,7 @@
class Boot_Hdr:
def __init__(self, init_val):
self.image_id = ImageType.NONE_IMG
- self.flash_parti_ver = FLASH_PARTI_VERSION
+ self.flash_parti_ver = MBN_HEADER_VERSION_3
self.image_src = init_val
self.image_dest_ptr = init_val
self.image_size = init_val
@@ -573,6 +575,10 @@
self.reserved_2,
self.reserved_3 ]
+ if self.flash_parti_ver == MBN_HEADER_VERSION_6:
+ values.insert(10, self.metadata_size_qti)
+ values.insert(11, self.metadata_size)
+
if self.image_dest_ptr >= 0x100000000:
values[3] = 0xFFFFFFFF
@@ -584,8 +590,12 @@
# Write 10 entries(40B) or 20 entries(80B) of boot header
if write_full_hdr is False:
- s = struct.Struct('I'* 10)
- values = values[:10]
+ if self.flash_parti_ver == MBN_HEADER_VERSION_6:
+ s = struct.Struct('I'* 12)
+ values = values[:12]
+ else:
+ s = struct.Struct('I'* 10)
+ values = values[:10]
else:
s = struct.Struct('I' * self.getLength())
@@ -912,7 +922,8 @@
write_full_hdr = False,
in_code_size = None,
cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE,
- num_of_pages = None):
+ num_of_pages = None,
+ header_version = None):
# Preliminary checks
if (requires_preamble is True) and (preamble_file_name is None):
@@ -945,9 +956,12 @@
cert_chain_size = 0
image_size = code_size
+ if header_version:
+ assert header_version in [MBN_HEADER_VERSION_3, MBN_HEADER_VERSION_5, MBN_HEADER_VERSION_6], 'Not a valid MBN header version'
+
# For ELF or hashed images, image destination will be determined from an ELF input file
if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf':
- image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE
+ image_dest = get_hash_address(elf_file_name) + (header_size(header_version))
elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin':
image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST']
image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE']
@@ -993,10 +1007,17 @@
boot_header.cert_chain_size = cert_chain_size
if is_ext_mbn_v5 == True:
- # If platform image integrity check is enabled
- boot_header.flash_parti_ver = 5 # version
- boot_header.image_src = 0 # sig_size_qc
- boot_header.image_dest_ptr = 0 # cert_chain_size_qc
+ # If platform image integrity check is enabled
+ boot_header.flash_parti_ver = MBN_HEADER_VERSION_5 # version
+ boot_header.image_src = 0 # sig_size_qc
+ boot_header.image_dest_ptr = 0 # cert_chain_size_qc
+
+ if header_version == MBN_HEADER_VERSION_6:
+ boot_header.flash_parti_ver = MBN_HEADER_VERSION_6 # version
+ boot_header.image_src = 0 # sig_size_qc
+ boot_header.image_dest_ptr = 0 # cert_chain_size_qc
+ boot_header.metadata_size_qti = 0 # qti_metadata size
+ boot_header.metadata_size = 0 # oem_metadata size
# If preamble is required, output the preamble file and update the boot_header
if requires_preamble is True:
@@ -1021,9 +1042,20 @@
last_phys_addr = None,
append_xml_hdr = False,
is_sha256_algo = True,
- cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE):
+ cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE,
+ header_version = None):
+ sha_algo = 'SHA1'
+ if is_sha256_algo:
+ sha_algo = 'SHA256'
+
+ if header_version == MBN_HEADER_VERSION_6:
+ sha_algo = 'SHA384'
global MI_PROG_BOOT_DIGEST_SIZE
- if (is_sha256_algo is True):
+ image_header_size = header_size(header_version)
+
+ if (sha_algo == 'SHA384'):
+ MI_PROG_BOOT_DIGEST_SIZE = 48
+ elif sha_algo == 'SHA256':
MI_PROG_BOOT_DIGEST_SIZE = 32
else:
MI_PROG_BOOT_DIGEST_SIZE = 20
@@ -1110,7 +1142,7 @@
fbuf = elf_in_fp.read(hash_size)
if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True:
- hash = generate_hash(fbuf, is_sha256_algo)
+ hash = generate_hash(fbuf, sha_algo)
else:
hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE
@@ -1129,7 +1161,7 @@
file_buff = elf_in_fp.read(data_len)
if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0):
- hash = generate_hash(file_buff, is_sha256_algo)
+ hash = generate_hash(file_buff, sha_algo)
else:
hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE
@@ -1151,7 +1183,7 @@
# Initialize the hash table program header
[hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \
- initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64)
+ initialize_hash_phdr(elf_in_file_name, hashtable_size, image_header_size, ELF_BLOCK_ALIGN, is_elf64)
# Check if hash segment max size parameter was passed
if (hash_seg_max_size is not None):
@@ -1252,7 +1284,7 @@
# Read the program header and compute hash
proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size)
- hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo)
+ hash = generate_hash(elfhdr_buff + proghdr_buff, sha_algo)
# Write hash to file as first hash table entry
hash_out_fp.seek(0)
@@ -1592,7 +1624,7 @@
page = page + elf_in_fp.read(bytes_in_page - len(page))
if (len(page) < DP_PAGE_SIZE):
page = page + (struct.pack('b', 0) * (DP_PAGE_SIZE - len(page)))
- hashes = hashes + [generate_hash(page, True)]
+ hashes = hashes + [generate_hash(page, 'SHA256')]
bytes_left -= bytes_in_page
# And write them to the hash segment
@@ -2101,9 +2133,20 @@
#----------------------------------------------------------------------------
# sha1/sha256 hash routine wrapper
#----------------------------------------------------------------------------
-def generate_hash(in_buf, is_sha256_algo):
+def header_size(header_version):
+ if header_version == MBN_HEADER_VERSION_6:
+ return 48
+ else:
+ return 40
+
+#----------------------------------------------------------------------------
+# sha1/sha256 hash routine wrapper
+#----------------------------------------------------------------------------
+def generate_hash(in_buf, sha_algo):
# Initialize a SHA1 object from the Python hash library
- if (is_sha256_algo is True):
+ if sha_algo == 'SHA384':
+ m = hashlib.sha384()
+ elif sha_algo == 'SHA256':
m = hashlib.sha256()
else:
m = hashlib.sha1()
--
To view, visit https://review.coreboot.org/c/coreboot/+/35506
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Gerrit-Change-Number: 35506
Gerrit-PatchSet: 1
Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org>
Gerrit-MessageType: newchange
6
19
Change in coreboot[master]: trogdor: Add T32 scripts for full boot chain
by mturney mturney (Code Review) 06 Feb '20
by mturney mturney (Code Review) 06 Feb '20
06 Feb '20
Hello ashk(a)codeaurora.org,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35505
to review the following change.
Change subject: trogdor: Add T32 scripts for full boot chain
......................................................................
trogdor: Add T32 scripts for full boot chain
Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489
Signed-off-by: ashk <ashk(a)codeaurora.org>
---
M util/qualcomm/scripts/cmm/debug_cb_common.cmm
A util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm
A util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm
3 files changed, 229 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35505/1
diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm
index 5959ee1..cc3dd38 100644
--- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm
+++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm
@@ -163,22 +163,28 @@
enter
)
+
+;;;; START OF COMMENTED OUT CODE TO SKIP QCLIB DEBUG
+
; go &QCLEntryAddr
; wait !run()
-;
+
; if &QCLStage
; (
-; &imgpath="3rdparty\blobs\soc\qualcomm\sdm845\QcLib.elf"
+
; if (&RAMLoad)
-; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /noclear
-; else
-; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode /noclear
-;
+; d.load \\snowcone\builds792\PROD\BOOT.XF.3.1-00315-SC7180LCB-1\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll
+; else
+; d.load \\snowcone\builds792\PROD\BOOT.XF.3.1-00315-SC7180LCB-1\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll
+
+
; print %String "Now the control is in QCLStage, press enter after debugging to go to next stage"
; print %String "Press enter to go to next stage"
; enter
; )
+;;;; END OF QCLIB COMMENTED OUT CODE
+
go &RAMEntryAddr
wait !run()
@@ -193,26 +199,6 @@
print %String "Press enter to go to next stage"
enter
)
-
-; BL31 disabled for now
-; Next block of code commented out
-; go &BL31EntryAddr
-; wait !run()
-;
-; if &BL31Stage
-; (
-; &imgpath="build\bl31.elf"
-; if (&RAMLoad)
-; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath
-; else
-; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode
-; y.spath.srd 3rdparty/arm-trusted-firmware
-; print %String "Now the control is in BL31, press enter after debugging to go to next stage"
-; print %String "Press enter to go to next stage"
-; enter
-; )
-; End of commented out code block: bl31
-
go &DCEntryAddr
wait !run()
@@ -220,36 +206,17 @@
(
&imgpath="payloads\external\depthcharge\depthcharge\build\depthcharge.elf"
symbol.sourcepath.setbasedir &srcpath\payloads
+ y.spath.srd payloads\external\depthcharge\depthcharge\src
if (&RAMLoad)
d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath
else
d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath /nocode
- b.d /all
- b.set main
- b.set halt
- b.set &KernelEntryAddr ; kernel entry point
- y.spath.srd + payloads/external/depthcharge/depthcharge
- y.spath.srd + 3rdparty\vboot_reference
- d.dump &RamConsoleAddr /spotlight
- &CBTablePtr=Register(X0)
- Data.SAVE.Binary CBTablePtr.bin &CBTablePtr++0x400
- print %String "Now the control is in Depthcharge, press enter after debugging to run free"
- ;print %String "Use this command to load kernel symbols: d.load.elf vmlinux /nocode /strippart kernel"
- print %String "Press enter when done debugging Depthcharge"
- enter
+ print %String "Now the control is in depthcharge, end of script"
+ d.l
+ b.s main
+ ;Execute this command in T32 if you start debugging vboot code, e.g. vboot_select_and_load_kernel()
+ ;y.spath.srd 3rdparty\vboot\firmware
)
-; go &KernelEntryAddr
-; wait !run()
-;
-; if &KernelSyms
-; (
-; print %String "Kernel Symbols are being loaded, this requires two files in coreboot root tree:"
-; print %String "vmlinux needs to be copied from ChromiumOS build tree"
-; print %String "msm-4.4 needs to be symbolic link to kernel source tree"
-; d.load.elf vmlinux /strippart "msm-4.4" /nocode
-; y.spath.srd msm-4.4
-; print %String "This script now concludes at kernel entry point"
-; )
enddo
diff --git a/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm
new file mode 100644
index 0000000..276bf45
--- /dev/null
+++ b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm
@@ -0,0 +1,158 @@
+;============================================================================
+;##
+;## This file is part of the coreboot project.
+;##
+;## Copyright (C) 2019, The Linux Foundation. All rights reserved.
+;##
+;## This program is free software; you can redistribute it and/or modify
+;## it under the terms of the GNU General Public License version 2 and
+;## only version 2 as published by the Free Software Foundation.
+;##
+;## This program is distributed in the hope that it will be useful,
+;## but WITHOUT ANY WARRANTY; without even the implied warranty of
+;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;## GNU General Public License for more details.
+;##
+;============================================================================
+; Name:
+; debug_cb_trogdor.cmm
+;
+; Description:
+; Debug coreboot trogdor front-end
+;============================================================================
+
+;============================================================================
+; CMM script variables
+;============================================================================
+
+LOCAL &TargetPkg
+
+GLOBAL &BBEntryAddr // Bootblock Entry
+GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec
+GLOBAL &VEREntryAddr // Verstage Entry
+GLOBAL &ROMEntryAddr // Romstage Entry
+GLOBAL &QCLEntryAddr // QCLstage Entry
+GLOBAL &RAMEntryAddr // Ramstage Entry
+GLOBAL &BL31EntryAddr // BL31 Entry
+GLOBAL &DCEntryAddr // Depthcharge Entry
+GLOBAL &KernelEntryAddr // Kernel Entry
+
+GLOBAL &PreRamConsoleAddr
+GLOBAL &RamConsoleAddr
+GLOBAL &PreRamCbfsCache
+GLOBAL &VBoot2Work
+GLOBAL &Stack
+GLOBAL &Ttb
+GLOBAL &Timestamp
+GLOBAL &CbmemTop
+GLOBAL &PostRamCbfsCache
+
+GLOBAL &CBTablePtr
+GLOBAL &debug
+;============================================================================
+
+;---------------------------------------------------
+; Entry point
+;---------------------------------------------------
+ENTRY &ImageName
+
+ // Later these can be parameterized
+ &TargetPkg="trogdorPkg"
+
+ // These settings come from .../src/soc/qualcomm/sc7180/include/soc/memlayout.ld
+ &BBEntryAddr=0x14815000
+ &VEREntryAddr=0x14680000
+ &ROMEntryAddr=0x14680000
+ &QCLEntryAddr=0x14881950
+ &RAMEntryAddr=0x9F860000
+ &BL31EntryAddr=0x06820000
+ &DCEntryAddr=0xF1000000
+ &KernelEntryAddr=0xD0000000
+
+ &PreRamConsoleAddr=0x14830800
+ &VBoot2Work=0x1482E000
+ &Stack=0x14847000
+ &Ttb=0x14839000
+ &Timestamp=0x14838800
+ &PreRamCbfsCache=0x1481F000
+ &CbmemTop=0x280000000
+ &PostRamCbfsCache=0x9F800000
+ // End of memlayout.ld settings
+
+ // Common commands irrespective of &Mode
+ PATH
+ &CwDir=os.pwd()
+ PATH + &CwDir
+
+ // position at top of coreboot tree
+ // find depth count for source loading
+ cd ..\..\..\..
+ &srcpath=os.pwd()
+
+
+;---------------------------------------------------
+; Setup area and log
+;---------------------------------------------------
+ area.clear
+ area.reset
+ area.create CB_Logs 1000. 8192.
+ area.select CB_Logs
+
+ area.view CB_Logs
+
+ PRINT %String "Source Path: &srcpath"
+
+ symbol.sourcepath.setbasedir &srcpath\src
+
+ // Make parsing simple, upper-case parameters
+ &ImageName=STRING.UPR("&ImageName")
+ IF (STR.CP("&ImageName","DEBUG,*"))
+ (
+ &debug="DEBUG"
+ )
+ ELSE
+ (
+ &debug=""
+ )
+ &ImageName=STR.CUT("&ImageName",6)
+ IF "&debug"==""
+ (
+ PRINT "SPI_RAM LOAD"
+ &ImageName=STRING.UPR("&ImageName")
+ IF "&ImageName"==""
+ (
+ &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC
+ )
+ PRINT "&ImageName"
+ )
+ ELSE
+ (
+ if (STR.CP("&debug","DEBUG"))
+ (
+ PRINT "DEBUG"
+ &ImageName=STRING.UPR("&ImageName")
+ IF "&ImageName"==""
+ (
+ &ImageName="RAM,ALL" //for RAM loading all the images
+ )
+ PRINT "&ImageName"
+ )
+ )
+
+ sys.d
+ sys.up
+ b.d
+ y.reset
+ D.S EZAXI:0xC260208 %LE %Long 0x80000000
+
+ b.s 0x148e7000 /o
+ go
+ WAIT !STATE.RUN()
+
+ b.s 0x14815000 /o
+ go
+ WAIT !STATE.RUN()
+
+ DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName
+
+ enddo
diff --git a/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm b/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm
new file mode 100644
index 0000000..9205d67
--- /dev/null
+++ b/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm
@@ -0,0 +1,53 @@
+sys.d
+sys.up
+b.d
+y.reset
+
+d.load.elf \\ashk-linux\workspace\ashk\pbl_script\FBC_validation\APPS_PBL.elf
+
+b.s sec_ctrl_drv_ioctl\273+0xC /P /CMD "r.s x6 0x12345678" /resume
+b.s pbl_recoverable_error_handler /o
+b.s pbl_non_recoverable_error_handler /o
+
+snoop.PC on
+
+b.s 0x148e7000 /o
+go
+WAIT !STATE.RUN()
+
+b.s 0x14815000 /o
+go
+WAIT !STATE.RUN()
+
+b.d
+b.s 0x14680000 /o
+go
+WAIT !STATE.RUN()
+
+b.d
+b.s 0x14680000 /o
+go
+WAIT !STATE.RUN()
+
+b.d
+b.s 0x14881950 /o
+go
+WAIT !STATE.RUN()
+
+d.load \\ashk-linux\workspace\ashk\test_qclib_8_7\boot.xf.3.1.test_qclib_8_7\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll
+do \\ashk-linux\workspace\ashk\test_qclib_8_7\boot.xf.3.1.test_qclib_8_7\boot_images\QcomPkg\Tools\qclib\qclib_rennell_only_stub_coreboot.cmm
+
+b.d
+b.s 0x9f860000 /o
+go
+WAIT !STATE.RUN()
+
+b.d
+b.s 0x80c00000 /o
+go
+WAIT !STATE.RUN()
+
+b.d
+b.s 0xF1000000 /o
+go
+WAIT !STATE.RUN()
--
To view, visit https://review.coreboot.org/c/coreboot/+/35505
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489
Gerrit-Change-Number: 35505
Gerrit-PatchSet: 1
Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org>
Gerrit-Reviewer: ashk(a)codeaurora.org
Gerrit-MessageType: newchange
6
12
Change in coreboot[master]: toolchain: build the bootstrap part on recent FreeBSD setups
by Idwer Vollering (Code Review) 30 Jan '20
by Idwer Vollering (Code Review) 30 Jan '20
30 Jan '20
Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34999 )
Change subject: toolchain: build the bootstrap part on recent FreeBSD setups
......................................................................
toolchain: build the bootstrap part on recent FreeBSD setups
"Add support for -fuse-ld=lld, backported from GCC mainline which is
going to become GCC 9 (in form of files/patch-fuse-ld=lld borrowed
from devel/riscv64-gcc)."
Obtained through: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227302
Change-Id: I3fa04283a2d306a9a11a1a0d929c6b7df2ac62fb
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
A util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch
1 file changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/34999/1
diff --git a/util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch b/util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch
new file mode 100644
index 0000000..dcf6b5a
--- /dev/null
+++ b/util/crossgcc/patches/gcc-8.3.0_fbsd-ld-lld.patch
@@ -0,0 +1,88 @@
+diff -urN gcc-8.3.0-vanilla/gcc/collect2.c gcc-8.3.0/gcc/collect2.c
+--- gcc-8.3.0-vanilla/gcc/collect2.c 2018-06-22 16:52:11.000000000 +0200
++++ gcc-8.3.0/gcc/collect2.c 2019-08-19 21:57:22.771579000 +0200
+@@ -831,6 +831,7 @@
+ USE_PLUGIN_LD,
+ USE_GOLD_LD,
+ USE_BFD_LD,
++ USE_LLD_LD,
+ USE_LD_MAX
+ } selected_linker = USE_DEFAULT_LD;
+ static const char *const ld_suffixes[USE_LD_MAX] =
+@@ -838,7 +839,8 @@
+ "ld",
+ PLUGIN_LD_SUFFIX,
+ "ld.gold",
+- "ld.bfd"
++ "ld.bfd",
++ "ld.lld"
+ };
+ static const char *const real_ld_suffix = "real-ld";
+ static const char *const collect_ld_suffix = "collect-ld";
+@@ -1007,6 +1009,8 @@
+ selected_linker = USE_BFD_LD;
+ else if (strcmp (argv[i], "-fuse-ld=gold") == 0)
+ selected_linker = USE_GOLD_LD;
++ else if (strcmp (argv[i], "-fuse-ld=lld") == 0)
++ selected_linker = USE_LLD_LD;
+
+ #ifdef COLLECT_EXPORT_LIST
+ /* These flags are position independent, although their order
+@@ -1096,7 +1100,8 @@
+ /* Maybe we know the right file to use (if not cross). */
+ ld_file_name = 0;
+ #ifdef DEFAULT_LINKER
+- if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD)
++ if (selected_linker == USE_BFD_LD || selected_linker == USE_GOLD_LD ||
++ selected_linker == USE_LLD_LD)
+ {
+ char *linker_name;
+ # ifdef HOST_EXECUTABLE_SUFFIX
+@@ -1315,7 +1320,7 @@
+ else if (!use_collect_ld
+ && strncmp (arg, "-fuse-ld=", 9) == 0)
+ {
+- /* Do not pass -fuse-ld={bfd|gold} to the linker. */
++ /* Do not pass -fuse-ld={bfd|gold|lld} to the linker. */
+ ld1--;
+ ld2--;
+ }
+diff -urN gcc-8.3.0-vanilla/gcc/common.opt gcc-8.3.0/gcc/common.opt
+--- gcc-8.3.0-vanilla/gcc/common.opt 2018-06-16 08:52:17.000000000 +0200
++++ gcc-8.3.0/gcc/common.opt 2019-08-19 21:58:53.386201000 +0200
+@@ -2715,6 +2715,10 @@
+ Common Driver Negative(fuse-ld=bfd)
+ Use the gold linker instead of the default linker.
+
++fuse-ld=lld
++Common Driver Negative(fuse-ld=lld)
++Use the lld LLVM linker instead of the default linker.
++
+ fuse-linker-plugin
+ Common Undocumented Var(flag_use_linker_plugin)
+
+diff -urN gcc-8.3.0-vanilla/gcc/doc/invoke.texi gcc-8.3.0/gcc/doc/invoke.texi
+--- gcc-8.3.0-vanilla/gcc/doc/invoke.texi 2019-02-15 00:08:18.000000000 +0100
++++ gcc-8.3.0/gcc/doc/invoke.texi 2019-08-19 22:05:27.979804000 +0200
+@@ -12259,6 +12259,10 @@
+ @opindex fuse-ld=gold
+ Use the @command{gold} linker instead of the default linker.
+
++@item -fuse-ld=lld
++@opindex fuse-ld=lld
++Use the LLVM @command{lld} linker instead of the default linker.
++
+ @cindex Libraries
+ @item -l@var{library}
+ @itemx -l @var{library}
+diff -urN gcc-8.3.0-vanilla/gcc/opts.c gcc-8.3.0/gcc/opts.c
+--- gcc-8.3.0-vanilla/gcc/opts.c 2019-01-31 11:00:26.000000000 +0100
++++ gcc-8.3.0/gcc/opts.c 2019-08-19 22:00:46.309476000 +0200
+@@ -2481,6 +2481,7 @@
+
+ case OPT_fuse_ld_bfd:
+ case OPT_fuse_ld_gold:
++ case OPT_fuse_ld_lld:
+ case OPT_fuse_linker_plugin:
+ /* No-op. Used by the driver and passed to us because it starts with f.*/
+ break;
--
To view, visit https://review.coreboot.org/c/coreboot/+/34999
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3fa04283a2d306a9a11a1a0d929c6b7df2ac62fb
Gerrit-Change-Number: 34999
Gerrit-PatchSet: 1
Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-MessageType: newchange
1
2
Change in ...coreboot[master]: Kconfig: Display a warning if the board is updated incorrectly
by Martin Roth (Code Review) 26 Jan '20
by Martin Roth (Code Review) 26 Jan '20
26 Jan '20
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33641
Change subject: Kconfig: Display a warning if the board is updated incorrectly
......................................................................
Kconfig: Display a warning if the board is updated incorrectly
Even though we have a comment to run make distclean before switching
mainboards, people still ignore this and end up with confusing results.
To try to fix this, save the mainboard directory in a Kconfig symbol
that will not get updated when the mainboard gets changed. This allows
us to compare it to the actual mainboard directory which will be updated
when the platform changes and put up an obnoxious warning in the
mainboard directory. Add another warning in the main menu, because
the initial warning is probably going to be ignored. The main menu
points to some documentation on how to fix the problem.
Note that this will only catch issues going forward, and won't catch
any already saved config that has a problem.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a
---
A Documentation/getting_started/fix_dot_config.md
M src/Kconfig
M src/mainboard/Kconfig
3 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33641/1
diff --git a/Documentation/getting_started/fix_dot_config.md b/Documentation/getting_started/fix_dot_config.md
new file mode 100644
index 0000000..17d89d0
--- /dev/null
+++ b/Documentation/getting_started/fix_dot_config.md
@@ -0,0 +1,50 @@
+# How to repair your .config file
+
+## Overview
+Many people rely on a saved .config file for building their
+platform. This is reasonable, but can create unanticipated
+problems.
+
+## TLDR
+* Backup your .config: "cp .config .config_bak"
+* Create the defconfig file: "make savedefconfig"
+* Edit defconfig & delete unknown config lines: "vi defconfig"
+* To just get rid of the warning about a bad .config, remove
+* the CONFIG_MAINBOARD_CHECK line.
+* The SMBIOS lines are probably incorrect as well. The ROM size
+* is very suspect. Check the correct default for your platform.
+* Save the defconfig
+* Generate a new full config:
+* "make -B defconfig KBUILD_DEFCONFIG=defconfig"
+
+## defconfig or "Mini config"
+Instead of saving a "full" config, people should use a defconfig.
+This is just the changes from a default coreboot configuration
+file. It's significantly smaller, and when a new configuration option
+gets added, it just takes the default value for that option when
+expanded into a full .config.
+
+### Generating the defconfig file
+To create the defconfig file, run "make savedefconfig". By default
+this will generate the file in the root coreboot directory and call
+it "defconfig". If there was already a file named "defconfig", this
+will overwrite that file.
+
+### Contents of the defconfig file
+As the defconfig file contains just the differences between the
+platform and the default choices for the platform. For the current
+default platform, the defconfig can actually be an empty file.
+
+Typically the defconfig will contain at least 2 lines - a
+CONFIG_VENDOR_ line and a CONFIG_BOARD_ line. Again though, if you
+are building the default board for any particular vendor, that line
+may not be present.
+
+All additional lines in a defconfig file are options that the user
+has specifically chosen to update in their config.
+
+### Generating a .config from a defconfig
+To expand the defconfig so that can be used, run:
+ DFILE=defconfig; make -B defconfig KBUILD_DEFCONFIG=$DFILE
+
+You can point DFILE to any saved defconfig.
diff --git a/src/Kconfig b/src/Kconfig
index 72d826f..8eae329 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -16,6 +16,15 @@
mainmenu "coreboot configuration"
+if MAINBOARD_CHECK != MAINBOARD_DIR
+comment "***********************************************************************"
+comment "WARNING: Your config is using defaults from a different mainboard "
+comment "than you currently have set. We'd recommend that you delete your "
+comment ".config file and start over, but if you want to try to repair the "
+comment "file, see Documentation/getting_started/fix_dot_config.md "
+comment "***********************************************************************"
+endif
+
menu "General setup"
config COREBOOT_BUILD
@@ -1062,6 +1071,14 @@
mainboard code supports this. On supported Intel platforms this works
by changing the settings in the descriptor.bin file.
+config MAINBOARD_CHECK
+ string "Mainboard dir - Do not change manually"
+ default MAINBOARD_DIR
+ help
+ Check the platform. If this symbol doesn't match the currently
+ selected mainboard directory, give the user warnings that they're
+ probably doing something wrong.
+
endmenu
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index c88d317..d9216a9 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -1,5 +1,16 @@
comment "Important: Run 'make distclean' before switching boards"
+if MAINBOARD_CHECK != MAINBOARD_DIR
+comment "***********************************************************************"
+comment "WARNING: Your config is using defaults from a different mainboard "
+comment "than you currently have set. We'd recommend that you delete your "
+comment ".config file and start over. "
+comment "* *"
+comment "If you ignore this warning and build anyway, you will almost certainly "
+comment "get a bad rom with undefined results. "
+comment "***********************************************************************"
+endif
+
choice
prompt "Mainboard vendor"
default VENDOR_EMULATION
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a
Gerrit-Change-Number: 33641
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
4
7
Change in ...coreboot[master]: Console: Allow console UART to be enabled without serial console
by Martin Roth (Code Review) 26 Jan '20
by Martin Roth (Code Review) 26 Jan '20
26 Jan '20
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33380
Change subject: Console: Allow console UART to be enabled without serial console
......................................................................
Console: Allow console UART to be enabled without serial console
Currently, when we disable serial console, the serial console uart
remains uninitialized. This patch allows coreboot to still set up
the UART, even if we're not sending the console to it.
BUG=b:74392237
TEST=Verify UART still works, even with coreboot console disabled
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a
---
M src/console/Kconfig
M src/drivers/uart/Kconfig
M src/include/console/uart.h
3 files changed, 28 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33380/1
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 61ba667..da769d3 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -33,6 +33,7 @@
bool "Serial port console output"
default y
depends on DRIVERS_UART
+ select ENABLE_UART
help
Send coreboot debug output to a serial port.
@@ -47,7 +48,7 @@
specific UART has to be used (e.g. when the platform code
performs dangerous configurations).
-if CONSOLE_SERIAL
+if ENABLE_UART
comment "I/O mapped, 8250-compatible"
depends on DRIVERS_UART_8250IO
@@ -79,13 +80,13 @@
Map the COM port number to the respective I/O port.
comment "Serial port base address = 0x3f8"
-depends on UART_FOR_CONSOLE = 0
+depends on UART_FOR_CONSOLE = 0 && DRIVERS_UART_8250IO
comment "Serial port base address = 0x2f8"
-depends on UART_FOR_CONSOLE = 1
+depends on UART_FOR_CONSOLE = 1 && DRIVERS_UART_8250IO
comment "Serial port base address = 0x3e8"
-depends on UART_FOR_CONSOLE = 2
+depends on UART_FOR_CONSOLE = 2 && DRIVERS_UART_8250IO
comment "Serial port base address = 0x2e8"
-depends on UART_FOR_CONSOLE = 3
+depends on UART_FOR_CONSOLE = 3 && DRIVERS_UART_8250IO
config UART_OVERRIDE_BAUDRATE
boolean
@@ -156,7 +157,7 @@
default 3
depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
-endif # CONSOLE_SERIAL
+endif # ENABLE_UART
config SPKMODEM
bool "spkmodem (console on speaker) console output"
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index 1f23a19..9b242fd 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -1,6 +1,21 @@
config DRIVERS_UART
bool
+config ENABLE_UART
+ def_bool n
+
+config ENABLE_UART_WITHOUT_CONSOLE
+ bool "Always configure primary UART"
+ depends on DRIVERS_UART
+ select ENABLE_UART
+ help
+ The primary UART has previously only been set up when the serial console
+ is enabled.
+ Selecting this choice will configure the console UART even if the serial
+ console is disabled.
+
+ Select the UART in the console menu
+
config DRIVERS_UART_8250IO
# FIXME: Shouldn't have a prompt, should default to n, and
# should be selected by boards that have it instead.
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index aed67c2..6bd88ae 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -67,11 +67,16 @@
(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \
ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI))))
-#if __CONSOLE_SERIAL_ENABLE__
+#if CONFIG(ENABLE_UART)
static inline void __uart_init(void)
{
uart_init(CONFIG_UART_FOR_CONSOLE);
}
+#else
+static inline void __uart_init(void) {}
+#endif
+
+#if __CONSOLE_SERIAL_ENABLE__
static inline void __uart_tx_byte(u8 data)
{
uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data);
@@ -81,7 +86,6 @@
uart_tx_flush(CONFIG_UART_FOR_CONSOLE);
}
#else
-static inline void __uart_init(void) {}
static inline void __uart_tx_byte(u8 data) {}
static inline void __uart_tx_flush(void) {}
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a
Gerrit-Change-Number: 33380
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
4
14
Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips
by Peter Lemenkov (Code Review) 24 Jan '20
by Peter Lemenkov (Code Review) 24 Jan '20
24 Jan '20
Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427
Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips
......................................................................
superio/nsc: Use common defines for NSC PC8xxxx chips
* Some common NSC defines moved to superio/nsc/common
* All NSC's pc8xxxx chips uses these common definitions
* Lenovo T60/X60/Z61t/T400 docking updated to use these common defines
* HP ProLiant DL165 G6 Fam10 updated to use this common code
Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10
builds fine.
Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/lenovo/t400/dock.c
M src/mainboard/lenovo/t60/dock.c
M src/mainboard/lenovo/x60/dock.c
M src/mainboard/lenovo/z61t/dock.c
A src/superio/nsc/common/superio_defs.h
D src/superio/nsc/pc87309/pc87309.h
M src/superio/nsc/pc87309/superio.c
D src/superio/nsc/pc87360/pc87360.h
M src/superio/nsc/pc87360/superio.c
D src/superio/nsc/pc87366/pc87366.h
M src/superio/nsc/pc87366/superio.c
D src/superio/nsc/pc87382/pc87382.h
M src/superio/nsc/pc87382/superio.c
D src/superio/nsc/pc87384/pc87384.h
M src/superio/nsc/pc87384/superio.c
D src/superio/nsc/pc87392/pc87392.h
M src/superio/nsc/pc87392/superio.c
M src/superio/nsc/pc87417/pc87417.h
M src/superio/nsc/pc87417/superio.c
20 files changed, 219 insertions(+), 369 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 6d2eed4..7f5411e 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -34,6 +34,7 @@
#include <spd.h>
#include <delay.h>
#include <superio/serverengines/pilot/pilot.h>
+#include <superio/nsc/common/superio_defs.h>
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
@@ -50,7 +51,7 @@
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
-#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
+#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c
index 6d1a80c..58788e7 100644
--- a/src/mainboard/lenovo/t400/dock.c
+++ b/src/mainboard/lenovo/t400/dock.c
@@ -23,7 +23,7 @@
#include <device/pnp.h>
#include <delay.h>
#include "dock.h"
-#include <superio/nsc/pc87382/pc87382.h>
+#include <superio/nsc/common/superio_defs.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <ec/lenovo/h8/h8.h>
@@ -64,8 +64,8 @@
return 0;
}
-static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK);
-static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO);
+static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK);
+static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO);
static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base)
{
@@ -170,20 +170,18 @@
/* Docking station side. */
-#include <superio/nsc/pc87384/pc87384.h>
-
-static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO);
-static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1);
+static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO);
+static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1);
static const struct pin_config remote_gpio[] = {
- {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE},
- {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE},
- {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
+ {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE},
+ {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE},
+ {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
};
static int pc87384_init(void)
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index 05dd65e..57a5a00 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -18,7 +18,7 @@
#include <arch/io.h>
#include <delay.h>
#include "dock.h"
-#include <superio/nsc/pc87384/pc87384.h>
+#include <superio/nsc/common/superio_defs.h>
#include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h"
#include <southbridge/intel/i82801gx/i82801gx.h>
@@ -128,38 +128,38 @@
dock_write_register(0x22, 0xa9);
/* enable serial port */
- dock_write_register(0x07, PC87384_SP1);
+ dock_write_register(0x07, PC8XXXX_SP1);
dock_write_register(0x30, 0x01);
- dock_write_register(0x07, PC87384_GPIO);
+ dock_write_register(0x07, PC8XXXX_GPIO);
dock_write_register(0x60, 0x16);
dock_write_register(0x61, 0x20);
/* enable GPIO */
dock_write_register(0x30, 0x01);
- dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
/* no GPIO events enabled for PORT0 */
diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c
index b94d818..cf5e71d 100644
--- a/src/mainboard/lenovo/x60/dock.c
+++ b/src/mainboard/lenovo/x60/dock.c
@@ -20,7 +20,7 @@
#include <delay.h>
#include "dock.h"
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <superio/nsc/pc87392/pc87392.h>
+#include <superio/nsc/common/superio_defs.h>
static void dlpc_write_register(int reg, int value)
{
@@ -165,58 +165,58 @@
dock_write_register(0x61, 0x20);
/* init GPIO pins */
- dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE |
- PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE |
- PC87392_GPIO_PIN_PULLUP,
- PC87392_GPIO_PIN_TRIGGERS_SMI);
+ dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP,
+ PC8XXXX_GPIO_PIN_TRIGGERS_SMI);
- dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02);
+ dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02);
- dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE |
- PC87392_GPIO_PIN_PULLUP,
- PC87392_GPIO_PIN_TRIGGERS_SMI);
+ dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP,
+ PC8XXXX_GPIO_PIN_TRIGGERS_SMI);
- dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
/* enable GPIO */
dock_write_register(0x30, 0x01);
diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c
index 05dd65e..57a5a00 100644
--- a/src/mainboard/lenovo/z61t/dock.c
+++ b/src/mainboard/lenovo/z61t/dock.c
@@ -18,7 +18,7 @@
#include <arch/io.h>
#include <delay.h>
#include "dock.h"
-#include <superio/nsc/pc87384/pc87384.h>
+#include <superio/nsc/common/superio_defs.h>
#include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h"
#include <southbridge/intel/i82801gx/i82801gx.h>
@@ -128,38 +128,38 @@
dock_write_register(0x22, 0xa9);
/* enable serial port */
- dock_write_register(0x07, PC87384_SP1);
+ dock_write_register(0x07, PC8XXXX_SP1);
dock_write_register(0x30, 0x01);
- dock_write_register(0x07, PC87384_GPIO);
+ dock_write_register(0x07, PC8XXXX_GPIO);
dock_write_register(0x60, 0x16);
dock_write_register(0x61, 0x20);
/* enable GPIO */
dock_write_register(0x30, 0x01);
- dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
/* no GPIO events enabled for PORT0 */
diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h
new file mode 100644
index 0000000..cc35508
--- /dev/null
+++ b/src/superio/nsc/common/superio_defs.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H
+#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H
+
+#define PC8XXXX_FDC 0x00 /* Floppy */
+#define PC8XXXX_PP 0x01 /* Parallel port */
+#define PC8XXXX_SP2 0x02 /* COM 2 / IR */
+#define PC8XXXX_SP1 0x03 /* COM 1 */
+#define PC8XXXX_SWC 0x04 /* System wakeup control */
+//#define PC8XXXX_PM 0x04 /* Power management */
+#define PC8XXXX_KBCM 0x05 /* Mouse */
+#define PC8XXXX_KBCK 0x06 /* Keyboard */
+#define PC8XXXX_GPIO 0x07 /* General purpose IO */
+//#define PC8XXXX_HM 0x08
+#define PC8XXXX_FSD 0x08 /* Fan speed device */
+#define PC8XXXX_ACB 0x08
+#define PC8XXXX_FSCM 0x09
+#define PC8XXXX_FMC 0x09
+#define PC8XXXX_WDT 0x0A
+#define PC8XXXX_GMP 0x0B
+#define PC8XXXX_MIDI 0x0C
+#define PC8XXXX_VLM 0x0D
+#define PC8XXXX_TMS 0x0E
+#define PC8XXXX_XBUS 0x0F
+#define PC8XXXX_RTC 0x10
+#define PC8XXXX_MHC 0x14
+#define PC8XXXX_DOCK 0x19
+
+#define PC8XXXX_GPIO_PIN_OE 0x01
+#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02
+#define PC8XXXX_GPIO_PIN_PULLUP 0x04
+#define PC8XXXX_GPIO_PIN_LOCK 0x08
+#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10
+#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20
+#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40
+
+#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01
+#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02
+
+#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */
diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h
deleted file mode 100644
index 3b912ea..0000000
--- a/src/superio/nsc/pc87309/pc87309.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87309_H
-#define SUPERIO_NSC_PC87309_H
-
-/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */
-
-#define PC87309_FDC 0x00 /* Floppy */
-#define PC87309_PP 0x01 /* Parallel port */
-#define PC87309_SP2 0x02 /* Com2 / IR */
-#define PC87309_SP1 0x03 /* Com1 */
-#define PC87309_PM 0x04 /* Power management */
-#define PC87309_KBCM 0x05 /* Mouse */
-#define PC87309_KBCK 0x06 /* Keyboard */
-
-#endif /* SUPERIO_NSC_PC87309_H */
diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c
index 458c501..f63bea9 100644
--- a/src/superio/nsc/pc87309/superio.c
+++ b/src/superio/nsc/pc87309/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87309.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -28,7 +28,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87309_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -43,14 +43,14 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
/* TODO: PM. */
- { NULL, PC87309_KBCM, PNP_IRQ0, },
- { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h
deleted file mode 100644
index c969746..0000000
--- a/src/superio/nsc/pc87360/pc87360.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87360_H
-#define SUPERIO_NSC_PC87360_H
-
-#define PC87360_FDC 0x00 /* Floppy */
-#define PC87360_PP 0x01 /* Parallel port */
-#define PC87360_SP2 0x02 /* Com2 */
-#define PC87360_SP1 0x03 /* Com1 */
-#define PC87360_SWC 0x04
-#define PC87360_KBCM 0x05 /* Mouse */
-#define PC87360_KBCK 0x06 /* Keyboard */
-#define PC87360_GPIO 0x07
-#define PC87360_ACB 0x08
-#define PC87360_FSCM 0x09
-#define PC87360_WDT 0x0A
-
-#endif /* SUPERIO_NSC_PC87360_H */
diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c
index cf5c7ca..85f21a2 100644
--- a/src/superio/nsc/pc87360/superio.c
+++ b/src/superio/nsc/pc87360/superio.c
@@ -21,7 +21,7 @@
#include <string.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87360.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -29,7 +29,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87360_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -44,18 +44,18 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87360_KBCM, PNP_IRQ0, },
- { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h
deleted file mode 100644
index b1df69f..0000000
--- a/src/superio/nsc/pc87366/pc87366.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87366_H
-#define SUPERIO_NSC_PC87366_H
-
-#define PC87366_FDC 0x00 /* Floppy */
-#define PC87366_PP 0x01 /* Parallel port */
-#define PC87366_SP2 0x02 /* Com2 */
-#define PC87366_SP1 0x03 /* Com1 */
-#define PC87366_SWC 0x04
-#define PC87366_KBCM 0x05 /* Mouse */
-#define PC87366_KBCK 0x06 /* Keyboard */
-#define PC87366_GPIO 0x07
-#define PC87366_ACB 0x08
-#define PC87366_FSCM 0x09
-#define PC87366_WDT 0x0A
-#define PC87366_GMP 0x0b
-#define PC87366_MIDI 0x0C
-#define PC87366_VLM 0x0D
-#define PC87366_TMS 0x0E
-
-#endif /* SUPERIO_NSC_PC87366_H */
diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c
index e1cba17..60e5e23 100644
--- a/src/superio/nsc/pc87366/superio.c
+++ b/src/superio/nsc/pc87366/superio.c
@@ -21,7 +21,7 @@
#include <string.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87366.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -29,7 +29,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87366_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -44,18 +44,18 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87366_KBCM, PNP_IRQ0, },
- { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h
deleted file mode 100644
index 6826f45..0000000
--- a/src/superio/nsc/pc87382/pc87382.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87382_H
-#define SUPERIO_NSC_PC87382_H
-
-#define PC87382_IR 0x02
-#define PC87382_SP1 0x03
-#define PC87382_GPIO 0x07
-#define PC87382_DOCK 0x19
-#endif
diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c
index 688f08c..6a21f51 100644
--- a/src/superio/nsc/pc87382/superio.c
+++ b/src/superio/nsc/pc87382/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <string.h>
#include <stdlib.h>
-#include "pc87382.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -27,10 +27,10 @@
return;
switch (dev->path.pnp.device) {
- case PC87382_DOCK:
+ case PC8XXXX_DOCK:
break;
- case PC87382_GPIO:
+ case PC8XXXX_GPIO:
break;
}
}
@@ -44,11 +44,11 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8 },
- { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
- { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
+ { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h
deleted file mode 100644
index 2184584..0000000
--- a/src/superio/nsc/pc87384/pc87384.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87384_H
-#define SUPERIO_NSC_PC87384_H
-
-#define PC87384_PP 0x01
-#define PC87384_SP2 0x02
-#define PC87384_SP1 0x03
-#define PC87384_GPIO 0x07
-
-#define PC87384_GPIO_PIN_OE 0x01
-#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02
-#define PC87384_GPIO_PIN_PULLUP 0x04
-#define PC87384_GPIO_PIN_LOCK 0x08
-#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10
-#define PC87384_GPIO_PIN_TRIG_LOW 0x20
-#define PC87384_GPIO_PIN_DEBOUNCE 0x40
-
-#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01
-
-#endif
diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c
index f34acd5..9548d2c 100644
--- a/src/superio/nsc/pc87384/superio.c
+++ b/src/superio/nsc/pc87384/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <string.h>
#include <stdlib.h>
-#include "pc87384.h"
+#include <superio/nsc/common/superio_defs.h>
static struct device_operations ops = {
.read_resources = pnp_read_resources,
@@ -29,10 +29,10 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
- { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h
deleted file mode 100644
index 5832435..0000000
--- a/src/superio/nsc/pc87392/pc87392.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87392_H
-#define SUPERIO_NSC_PC87392_H
-
-#define PC87392_FDC 0x00
-#define PC87392_PP 0x01
-#define PC87392_SP2 0x02
-#define PC87392_SP1 0x03
-#define PC87392_GPIO 0x07
-#define PC87392_WDT 0x0A
-
-#define PC87392_GPIO_PIN_OE 0x01
-#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02
-#define PC87392_GPIO_PIN_PULLUP 0x04
-#define PC87392_GPIO_PIN_LOCK 0x08
-#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10
-#define PC87392_GPIO_PIN_TRIG_LOW 0x20
-#define PC87392_GPIO_PIN_DEBOUNCE 0x40
-
-#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01
-#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02
-
-#endif
diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c
index edd4619..9971b5c 100644
--- a/src/superio/nsc/pc87392/superio.c
+++ b/src/superio/nsc/pc87392/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <string.h>
#include <stdlib.h>
-#include "pc87392.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -36,13 +36,13 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
- { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
- { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8 },
- { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 },
- { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h
index b50a920..e6c7f79 100644
--- a/src/superio/nsc/pc87417/pc87417.h
+++ b/src/superio/nsc/pc87417/pc87417.h
@@ -19,17 +19,6 @@
#ifndef SUPERIO_NSC_PC87417_H
#define SUPERIO_NSC_PC87417_H
-#define PC87417_FDC 0x00 /* Floppy */
-#define PC87417_PP 0x01 /* Parallel Port */
-#define PC87417_SP2 0x02 /* Com2 */
-#define PC87417_SP1 0x03 /* Com1 */
-#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */
-#define PC87417_KBCM 0x05 /* Mouse */
-#define PC87417_KBCK 0x06 /* Keyboard */
-#define PC87417_GPIO 0x07
-#define PC87417_XBUS 0x0F
-#define PC87417_RTC 0x10
-
#define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO)
/* This is to get around a romcc bug */
/* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */
diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c
index f0e0bb1..a4e8022 100644
--- a/src/superio/nsc/pc87417/superio.c
+++ b/src/superio/nsc/pc87417/superio.c
@@ -22,7 +22,7 @@
#include <string.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87417.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -30,7 +30,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87417_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -45,17 +45,17 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87417_KBCM, PNP_IRQ0, },
- { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, },
- { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, },
+ { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, },
};
static void enable_dev(struct device *dev)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485
Gerrit-Change-Number: 31427
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
Gerrit-MessageType: newchange
2
2
Change in coreboot[master]: src/superio: Remove unused superio chips
by Martin Roth (Code Review) 24 Jan '20
by Martin Roth (Code Review) 24 Jan '20
24 Jan '20
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35428 )
Change subject: src/superio: Remove unused superio chips
......................................................................
src/superio: Remove unused superio chips
These SIOs are not being used or tested by abuild, so remove them from
the tree.
src/superio/fintek/f71805f
src/superio/fintek/f71872
src/superio/intel/i8900
src/superio/ite/it8613e
src/superio/ite/it8671f
src/superio/ite/it8716f
src/superio/ite/it8786e
src/superio/nsc/pc87309
src/superio/nsc/pc87360
src/superio/nsc/pc87366
src/superio/nsc/pc97317
src/superio/nuvoton/nct5539d
src/superio/smsc/dme1737
src/superio/smsc/lpc47b272
src/superio/smsc/lpc47b397
src/superio/smsc/sch4037
src/superio/smsc/sio1036
src/superio/via/vt1211
src/superio/winbond/w83697hf
src/superio/winbond/wpcd376i
Signed-off-by: Martin Roth <martin(a)coreboot.org>
Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4
---
D src/superio/fintek/f71805f/Kconfig
D src/superio/fintek/f71805f/Makefile.inc
D src/superio/fintek/f71805f/f71805f.h
D src/superio/fintek/f71805f/superio.c
D src/superio/fintek/f71872/Kconfig
D src/superio/fintek/f71872/Makefile.inc
D src/superio/fintek/f71872/f71872.h
D src/superio/fintek/f71872/superio.c
D src/superio/intel/i8900/Kconfig
D src/superio/intel/i8900/Makefile.inc
D src/superio/intel/i8900/early_serial.c
D src/superio/intel/i8900/i8900.h
D src/superio/intel/i8900/superio.c
D src/superio/ite/it8613e/Kconfig
D src/superio/ite/it8613e/Makefile.inc
D src/superio/ite/it8613e/chip.h
D src/superio/ite/it8613e/it8613e.h
D src/superio/ite/it8613e/superio.c
D src/superio/ite/it8671f/Kconfig
D src/superio/ite/it8671f/Makefile.inc
D src/superio/ite/it8671f/early_serial.c
D src/superio/ite/it8671f/it8671f.h
D src/superio/ite/it8671f/superio.c
D src/superio/ite/it8716f/Kconfig
D src/superio/ite/it8716f/Makefile.inc
D src/superio/ite/it8716f/it8716f.h
D src/superio/ite/it8716f/superio.c
D src/superio/ite/it8786e/Kconfig
D src/superio/ite/it8786e/Makefile.inc
D src/superio/ite/it8786e/acpi/superio.asl
D src/superio/ite/it8786e/chip.h
D src/superio/ite/it8786e/it8786e.h
D src/superio/ite/it8786e/superio.c
D src/superio/nsc/pc87309/Kconfig
D src/superio/nsc/pc87309/Makefile.inc
D src/superio/nsc/pc87309/pc87309.h
D src/superio/nsc/pc87309/superio.c
D src/superio/nsc/pc87360/Kconfig
D src/superio/nsc/pc87360/Makefile.inc
D src/superio/nsc/pc87360/pc87360.h
D src/superio/nsc/pc87360/superio.c
D src/superio/nsc/pc87366/Kconfig
D src/superio/nsc/pc87366/Makefile.inc
D src/superio/nsc/pc87366/pc87366.h
D src/superio/nsc/pc87366/superio.c
D src/superio/nsc/pc97317/Kconfig
D src/superio/nsc/pc97317/Makefile.inc
D src/superio/nsc/pc97317/early_serial.c
D src/superio/nsc/pc97317/pc97317.h
D src/superio/nsc/pc97317/superio.c
M src/superio/nuvoton/common/early_serial.c
D src/superio/nuvoton/nct5539d/Kconfig
D src/superio/nuvoton/nct5539d/Makefile.inc
D src/superio/nuvoton/nct5539d/nct5539d.h
D src/superio/nuvoton/nct5539d/superio.c
D src/superio/smsc/dme1737/Kconfig
D src/superio/smsc/dme1737/Makefile.inc
D src/superio/smsc/dme1737/dme1737.h
D src/superio/smsc/dme1737/early_serial.c
D src/superio/smsc/dme1737/superio.c
D src/superio/smsc/lpc47b272/Kconfig
D src/superio/smsc/lpc47b272/Makefile.inc
D src/superio/smsc/lpc47b272/early_serial.c
D src/superio/smsc/lpc47b272/lpc47b272.h
D src/superio/smsc/lpc47b272/superio.c
D src/superio/smsc/lpc47b397/Kconfig
D src/superio/smsc/lpc47b397/Makefile.inc
D src/superio/smsc/lpc47b397/early_serial.c
D src/superio/smsc/lpc47b397/lpc47b397.h
D src/superio/smsc/lpc47b397/superio.c
D src/superio/smsc/sch4037/Kconfig
D src/superio/smsc/sch4037/Makefile.inc
D src/superio/smsc/sch4037/sch4037.h
D src/superio/smsc/sch4037/sch4037_early_init.c
D src/superio/smsc/sch4037/superio.c
D src/superio/smsc/sio1036/Kconfig
D src/superio/smsc/sio1036/Makefile.inc
D src/superio/smsc/sio1036/sio1036.h
D src/superio/smsc/sio1036/sio1036_early_init.c
D src/superio/smsc/sio1036/superio.c
D src/superio/via/vt1211/Kconfig
D src/superio/via/vt1211/Makefile.inc
D src/superio/via/vt1211/superio.c
D src/superio/via/vt1211/vt1211.h
D src/superio/winbond/w83697hf/Kconfig
D src/superio/winbond/w83697hf/Makefile.inc
D src/superio/winbond/w83697hf/chip.h
D src/superio/winbond/w83697hf/superio.c
D src/superio/winbond/w83697hf/w83697hf.h
D src/superio/winbond/wpcd376i/Kconfig
D src/superio/winbond/wpcd376i/Makefile.inc
D src/superio/winbond/wpcd376i/chip.h
D src/superio/winbond/wpcd376i/early_serial.c
D src/superio/winbond/wpcd376i/superio.c
D src/superio/winbond/wpcd376i/wpcd376i.h
95 files changed, 0 insertions(+), 4,058 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35428/1
diff --git a/src/superio/fintek/f71805f/Kconfig b/src/superio/fintek/f71805f/Kconfig
deleted file mode 100644
index 7f06f55..0000000
--- a/src/superio/fintek/f71805f/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_FINTEK_F71805F
- bool
- select SUPERIO_FINTEK_COMMON_PRE_RAM
diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc
deleted file mode 100644
index 26b23f6..0000000
--- a/src/superio/fintek/f71805f/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c
diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h
deleted file mode 100644
index b4ca60a..0000000
--- a/src/superio/fintek/f71805f/f71805f.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_FINTEK_F71805F_H
-#define SUPERIO_FINTEK_F71805F_H
-
-/*
- * Datasheet:
- * - Name: F71805F/FG Super H/W Monitor + LPC IO
- * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17
- * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf
- * - Revision: V0.25P
- */
-
-/* Logical Device Numbers (LDN). */
-#define F71805F_FDC 0x00 /* Floppy */
-#define F71805F_SP1 0x01 /* UART1 */
-#define F71805F_SP2 0x02 /* UART2 */
-#define F71805F_PP 0x03 /* Parallel port */
-#define F71805F_HWM 0x04 /* Hardware monitor */
-#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */
-#define F71805F_PME 0x0a /* Power Management Events (PME) */
-
-#endif /* SUPERIO_FINTEK_F71805F_H */
diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c
deleted file mode 100644
index 4719923..0000000
--- a/src/superio/fintek/f71805f/superio.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <stdlib.h>
-#include "f71805f.h"
-
-static void f71805f_init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-
- /* TODO: Might potentially need code for HWM or FDC etc. */
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = f71805f_init,
- .ops_pnp_mode = &pnp_conf_mode_8787_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- /* TODO: Some of the 0x07f8 etc. values may not be correct. */
- { NULL, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, F71805F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, F71805F_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, F71805F_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
- { NULL, F71805F_GPIO, PNP_IRQ0, },
- { NULL, F71805F_PME, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_fintek_f71805f_ops = {
- CHIP_NAME("Fintek F71805F/FG Super I/O")
- .enable_dev = enable_dev
-};
diff --git a/src/superio/fintek/f71872/Kconfig b/src/superio/fintek/f71872/Kconfig
deleted file mode 100644
index 516ff094..0000000
--- a/src/superio/fintek/f71872/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_FINTEK_F71872
- bool
- select SUPERIO_FINTEK_COMMON_PRE_RAM
diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc
deleted file mode 100644
index 7237d0b..0000000
--- a/src/superio/fintek/f71872/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c
diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h
deleted file mode 100644
index afd238c..0000000
--- a/src/superio/fintek/f71872/f71872.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_FINTEK_F71872_H
-#define SUPERIO_FINTEK_F71872_H
-
-/* Logical Device Numbers (LDN). */
-#define F71872_FDC 0x00 /* Floppy */
-#define F71872_SP1 0x01 /* UART1 */
-#define F71872_SP2 0x02 /* UART2 */
-#define F71872_PP 0x03 /* Parallel Port */
-#define F71872_HWM 0x04 /* Hardware Monitor */
-#define F71872_KBC 0x05 /* Keyboard/Mouse */
-#define F71872_GPIO 0x06 /* GPIO */
-#define F71872_VID 0x07 /* VID */
-#define F71872_PM 0x0a /* ACPI/PME */
-
-#endif /* SUPERIO_FINTEK_F71872_H */
diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c
deleted file mode 100644
index 3316ee2..0000000
--- a/src/superio/fintek/f71872/superio.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <stdlib.h>
-#include <pc80/keyboard.h>
-#include "f71872.h"
-
-static void f71872_init(struct device *dev)
-{
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- /* TODO: Might potentially need code for HWM or FDC etc. */
- case F71872_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = f71872_init,
- .ops_pnp_mode = &pnp_conf_mode_8787_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- /* TODO: Some of the 0x07f8 etc. values may not be correct. */
- { NULL, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, F71872_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, F71872_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, F71872_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
- { NULL, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
- { NULL, F71872_GPIO, PNP_IRQ0, },
- { NULL, F71872_VID, PNP_IO0, 0x0ff8, },
- { NULL, F71872_PM, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_fintek_f71872_ops = {
- CHIP_NAME("Fintek F71872 Super I/O")
- .enable_dev = enable_dev
-};
diff --git a/src/superio/intel/i8900/Kconfig b/src/superio/intel/i8900/Kconfig
deleted file mode 100644
index ed37f7f..0000000
--- a/src/superio/intel/i8900/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_INTEL_I8900
- bool
diff --git a/src/superio/intel/i8900/Makefile.inc b/src/superio/intel/i8900/Makefile.inc
deleted file mode 100644
index 562d5d1..0000000
--- a/src/superio/intel/i8900/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c
-romstage-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_INTEL_I8900) += superio.c
diff --git a/src/superio/intel/i8900/early_serial.c b/src/superio/intel/i8900/early_serial.c
deleted file mode 100644
index 681b225..0000000
--- a/src/superio/intel/i8900/early_serial.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp.h>
-#include "i8900.h"
-
-static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
-
- outb(0x80, port);
- outb(0x86, port);
-}
-
-static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
-
- outb(0x68, port);
- outb(0x08, port);
-}
-
-/* Enable device interrupts, set UART_CLK predivide. */
-void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_write_config(dev, I8900_SIW_CONFIGURATION,
- (predivide << 2) | I8900_ENABLE_SIRQ);
- pnp_exit_ext_func_mode(dev);
-}
-
-void i8900_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
-
-void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase)
-{
- /* Enable WDT */
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/intel/i8900/i8900.h b/src/superio/intel/i8900/i8900.h
deleted file mode 100644
index 348d3c4..0000000
--- a/src/superio/intel/i8900/i8900.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_INTEL_I8900_I8900_H
-#define SUPERIO_INTEL_I8900_I8900_H
-
-#include <device/pnp_type.h>
-
-/*
- * The SIW ("Serial I/O and Watchdog Timer") integrated into the i8900 is
- * very similar to a Super I/O, both in functionality and config mechanism.
- *
- * The SIW contains:
- * - UART(s)
- * - Serial interrupt controller
- * - Watchdog timer (WDT)
- * - LPC interface
- */
-
-/* Logical device numbers (LDNs). */
-#define I8900_SP1 0x04 /* Com1 */
-#define I8900_SP2 0x05 /* Com2 */
-#define I8900_WDT 0x06 /* Watchdog timer */
-
-/* Registers and bit definitions: */
-
-#define I8900_SIW_CONFIGURATION 0x29
-
-/*
- * SIW_CONFIGURATION[3:2] = UART_CLK predivide
- * 00: divide by 1
- * 01: divide by 8
- * 10: divide by 26
- * 11: reserved
- */
-#define I8900_UART_CLK_PREDIVIDE_1 0x00
-#define I8900_UART_CLK_PREDIVIDE_8 0x01
-#define I8900_UART_CLK_PREDIVIDE_26 0x02
-#define I8900_ENABLE_SIRQ 0x01
-
-void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide);
-void i8900_enable_serial(pnp_devfn_t dev, u16 iobase);
-void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase);
-
-#endif
diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c
deleted file mode 100644
index 24805bc..0000000
--- a/src/superio/intel/i8900/superio.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include <drivers/uart/uart8250reg.h>
-#include "i8900.h"
-#include <arch/io.h>
-
-static void pnp_enter_ext_func_mode(struct device *dev)
-{
- outb(0x80, dev->path.pnp.port);
- outb(0x86, dev->path.pnp.port);
-}
-
-static void pnp_exit_ext_func_mode(struct device *dev)
-{
- outb(0x68, dev->path.pnp.port);
- outb(0x08, dev->path.pnp.port);
-}
-
-static void i8900_init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-}
-
-static void i8900_pnp_set_resources(struct device *dev)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_resources(dev);
- pnp_exit_ext_func_mode(dev);
-}
-
-static void i8900_pnp_enable_resources(struct device *dev)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_enable_resources(dev);
- pnp_exit_ext_func_mode(dev);
-}
-
-static void i8900_pnp_enable(struct device *dev)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, !!dev->enabled);
- pnp_exit_ext_func_mode(dev);
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = i8900_pnp_set_resources,
- .enable_resources = i8900_pnp_enable_resources,
- .enable = i8900_pnp_enable,
- .init = i8900_init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, I8900_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, I8900_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, I8900_WDT, PNP_IO0 | PNP_IRQ0, 0x07f8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_intel_i8900_ops = {
- CHIP_NAME("Intel 8900 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig
deleted file mode 100644
index f09cac2..0000000
--- a/src/superio/ite/it8613e/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
-## Copyright (C) 2018 Kevin Cody-Little <kcodyjr(a)gmail.com>
-## Copyright (C) 2019 Protectli
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_ITE_IT8613E
- bool
- select SUPERIO_ITE_COMMON_PRE_RAM
- select SUPERIO_ITE_ENV_CTRL
- select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
- select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
- select SUPERIO_ITE_ENV_CTRL_5FANS
- select SUPERIO_ITE_ENV_CTRL_NO_ONOFF
diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc
deleted file mode 100644
index 75ab26b..0000000
--- a/src/superio/ite/it8613e/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
-## Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
-## Copyright (C) 2019 Protectli
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c
diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h
deleted file mode 100644
index 65875c8..0000000
--- a/src/superio/ite/it8613e/chip.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
- * Copyright (C) 2019 Protectli
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_ITE_IT8613E_CHIP_H
-#define SUPERIO_ITE_IT8613E_CHIP_H
-
-#include <superio/ite/common/env_ctrl_chip.h>
-
-struct superio_ite_it8613e_config {
- struct ite_ec_config ec;
-};
-
-#endif /* SUPERIO_ITE_IT8613E_CHIP_H */
diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h
deleted file mode 100644
index 890c249..0000000
--- a/src/superio/ite/it8613e/it8613e.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
- * Copyright (C) 2019 Protectli
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_ITE_IT8613E_H
-#define SUPERIO_ITE_IT8613E_H
-
-/*
- * IT8613 supports 2 clock inputs: PCICLK and CLKIN. Multiple registers need
- * to be set to choose proper source. PCICLK is required for LPC.
- *
- * In the table below PD means pull-down, X - don't care.
- *
- * |-------------------------------------------------------------------|
- * | CLKIN | PCICLK | LDN7\ | GBL\ | LDN7\ | LDN7\ | GBL\ |
- * | | | 71h[3] | 23h[3] | 2Dh[2] | 2Dh[1] | 23h[0] |
- * |--------+--------+---------+---------+---------+---------+---------|
- * | PD | 33 MHz | X | 0 | 0 | 0 | 0 |
- * | PD | 24 MHz | 1 | 1 | X | 0 | 1 |
- * | PD | 25 MHz | X | 0 | 1 | 0 | 0 |
- * | 24 MHz | X | 0 | 1 | X | 0 | 1 |
- * | 48 MHz | X | 0 | 1 | X | 0 | 0 |
- * |-------------------------------------------------------------------|
- *
- */
-
-#define IT8613E_SP1 0x01 /* Com1 */
-#define IT8613E_EC 0x04 /* Environment controller */
-#define IT8613E_KBCK 0x05 /* PS/2 keyboard */
-#define IT8613E_KBCM 0x06 /* PS/2 mouse */
-#define IT8613E_GPIO 0x07 /* GPIO */
-#define IT8613E_CIR 0x0a /* Consumer Infrared */
-
-#endif /* SUPERIO_ITE_IT8613E_H */
diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c
deleted file mode 100644
index 7a4e336..0000000
--- a/src/superio/ite/it8613e/superio.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de>
- * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
- * Copyright (C) 2019 Protectli
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <superio/conf_mode.h>
-#include <superio/ite/common/env_ctrl.h>
-
-#include "chip.h"
-#include "it8613e.h"
-
-static void it8613e_init(struct device *dev)
-{
- const struct superio_ite_it8613e_config *conf = dev->chip_info;
- const struct resource *res;
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case IT8613E_EC:
- res = find_resource(dev, PNP_IDX_IO0);
- if (!conf || !res)
- break;
- ite_ec_init(res->base, &conf->ec);
- break;
- case IT8613E_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- case IT8613E_KBCM:
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = it8613e_init,
- .ops_pnp_mode = &pnp_conf_mode_870155_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- /* Serial Port 1 */
- { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
- /* Environmental Controller */
- { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, },
- /* KBC Keyboard */
- { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
- 0x0fff, 0x0fff, },
- /* KBC Mouse */
- { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, },
- /* GPIO */
- { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0ff8, },
- /* Consumer Infrared */
- { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_ite_it8613e_ops = {
- CHIP_NAME("ITE IT8613E Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/ite/it8671f/Kconfig b/src/superio/ite/it8671f/Kconfig
deleted file mode 100644
index ba63224..0000000
--- a/src/superio/ite/it8671f/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_ITE_IT8671F
- bool
- select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc
deleted file mode 100644
index f625bc1..0000000
--- a/src/superio/ite/it8671f/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c
-romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c
diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c
deleted file mode 100644
index b5b94df..0000000
--- a/src/superio/ite/it8671f/early_serial.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pnp_type.h>
-#include <device/pnp.h>
-#include <stdint.h>
-#include "it8671f.h"
-
-/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE 0x3f0
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
-#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
-
-#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
-
-/*
- * Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data.
- */
-static const u8 init_values[] = {
- 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
- 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
- 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
- 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
-};
-
-static void it8671f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-/* Enter the configuration state (MB PnP mode). */
-static void it8671f_enter_conf(void)
-{
- int i;
-
- /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
- /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
- /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
- /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
- outb(0x86, IT8671F_CONFIGURATION_PORT);
- outb(0x80, IT8671F_CONFIGURATION_PORT);
- outb(0x55, IT8671F_CONFIGURATION_PORT);
- outb(0x55, IT8671F_CONFIGURATION_PORT);
-
- /* Sequentially write the 32 special values. */
- for (i = 0; i < 32; i++)
- outb(init_values[i], SIO_BASE);
-}
-
-/* Exit the configuration state (MB PnP mode). */
-static void it8671f_exit_conf(void)
-{
- it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 48MHz CLKIN (24MHz is the default). */
-void it8671f_48mhz_clkin(void)
-{
- it8671f_enter_conf();
- it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
- it8671f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- it8671f_enter_conf();
-
- /*
- * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
- * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7).
- */
- it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
-
- /* Enable serial port(s). */
- it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
- it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
-
- it8671f_exit_conf();
-}
diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h
deleted file mode 100644
index 5fe74bc..0000000
--- a/src/superio/ite/it8671f/it8671f.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_ITE_IT8671F_H
-#define SUPERIO_ITE_IT8671F_H
-
-#include <device/pnp_type.h>
-#include <stdint.h>
-
-/* Datasheet: Not available online, got it from ITE per request. */
-
-#define IT8671F_FDC 0x00 /* Floppy */
-#define IT8671F_SP1 0x01 /* Com1 */
-#define IT8671F_SP2 0x02 /* Com2 */
-#define IT8671F_PP 0x03 /* Parallel port */
-#define IT8671F_KBCK 0x05 /* PS/2 keyboard */
-#define IT8671F_KBCM 0x06 /* PS/2 mouse */
-
-void it8671f_48mhz_clkin(void);
-void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif /* SUPERIO_ITE_IT8671F_H */
diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c
deleted file mode 100644
index 70da2ab..0000000
--- a/src/superio/ite/it8671f/superio.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include <superio/conf_mode.h>
-#include "it8671f.h"
-
-static void init(struct device *dev)
-{
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case IT8671F_FDC: /* TODO. */
- break;
- case IT8671F_PP: /* TODO. */
- break;
- case IT8671F_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- case IT8671F_KBCM: /* TODO. */
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_enable,
- .init = init,
- .ops_pnp_mode = &pnp_conf_mode_870155_aa,
-};
-
-/* TODO: FDC, PP, KBCM. */
-static struct pnp_info pnp_dev_info[] = {
- { NULL, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
- 0x07f8, },
- { NULL, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_ite_it8671f_ops = {
- CHIP_NAME("ITE IT8671F Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/ite/it8716f/Kconfig b/src/superio/ite/it8716f/Kconfig
deleted file mode 100644
index 969e788..0000000
--- a/src/superio/ite/it8716f/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_ITE_IT8716F
- bool
- select SUPERIO_ITE_COMMON_PRE_RAM
-
-config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
- bool
- depends on SUPERIO_ITE_IT8716F
- default n
- select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc
deleted file mode 100644
index 6125068..0000000
--- a/src/superio/ite/it8716f/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c
diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h
deleted file mode 100644
index 726c4cc..0000000
--- a/src/superio/ite/it8716f/it8716f.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_ITE_IT8716F_H
-#define SUPERIO_ITE_IT8716F_H
-
-#include <stdint.h>
-
-/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
-
-/* Logical device numbers (LDNs). */
-#define IT8716F_FDC 0x00 /* Floppy */
-#define IT8716F_SP1 0x01 /* Com1 */
-#define IT8716F_SP2 0x02 /* Com2 */
-#define IT8716F_PP 0x03 /* Parallel port */
-#define IT8716F_EC 0x04 /* Environment controller */
-#define IT8716F_KBCK 0x05 /* PS/2 keyboard */
-#define IT8716F_KBCM 0x06 /* PS/2 mouse */
-#define IT8716F_GPIO 0x07 /* GPIO */
-#define IT8716F_MIDI 0x08 /* MIDI port */
-#define IT8716F_GAME 0x09 /* GAME port */
-#define IT8716F_IR 0x0a /* Consumer IR */
-
-/* Provided by mainboard, called by IT8716F superio.c. */
-void init_ec(u16 base);
-
-#endif /* SUPERIO_ITE_IT8716F_H */
diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c
deleted file mode 100644
index de1ef0d..0000000
--- a/src/superio/ite/it8716f/superio.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD)
- * Copyright (C) 2007 Ward Vandewege <ward(a)gnu.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <console/console.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include <superio/conf_mode.h>
-
-#include "it8716f.h"
-
-#if !CONFIG(SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL)
-
-void init_ec(u16 base)
-{
- u8 value;
-
- /* Read out current value of FAN_CTL (0x14). */
- value = pnp_read_index(base, 0x14);
- printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n",
- base + 0x14, value);
-
- /* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */
- pnp_write_index(base, 0x14, value | 0x87);
- printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n",
- base + 0x14, value | 0x87);
-}
-#endif
-
-static void it8716f_init(struct device *dev)
-{
- struct resource *res0;
-
- if (!dev->enabled)
- return;
-
- /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */
- switch (dev->path.pnp.device) {
- case IT8716F_EC:
- res0 = find_resource(dev, PNP_IDX_IO0);
-#define EC_INDEX_PORT 5
- init_ec(res0->base + EC_INDEX_PORT);
- break;
- case IT8716F_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = it8716f_init,
- .ops_pnp_mode = &pnp_conf_mode_870155_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
- { NULL, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
- { NULL, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
- { NULL, IT8716F_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0,
- 0x0ff8, 0x0ffc, },
- { NULL, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, },
- { NULL, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, },
- { NULL, IT8716F_KBCM, PNP_IRQ0, },
- { NULL, IT8716F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2,
- 0x0ff8, 0x0ff8, 0x0ff8, },
- { NULL, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
- { NULL, IT8716F_GAME, PNP_IO0, 0x0ff8, },
- { NULL, IT8716F_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_ite_it8716f_ops = {
- CHIP_NAME("ITE IT8716F Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig
deleted file mode 100644
index 9d3f258..0000000
--- a/src/superio/ite/it8786e/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2016 secunet Security Networks AG
-## Copyright (C) 2018 Libretrend LDA
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_ITE_IT8786E
- bool
- select SUPERIO_ITE_COMMON_PRE_RAM
- select SUPERIO_ITE_ENV_CTRL
- select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
- select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
- select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG
diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc
deleted file mode 100644
index 560957f..0000000
--- a/src/superio/ite/it8786e/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2016 secunet Security Networks AG
-## Copyright (C) 2018 Libretrend LDA
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c
diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl
deleted file mode 100644
index f860da6..0000000
--- a/src/superio/ite/it8786e/acpi/superio.asl
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de>
- * Copyright (C) 2013, 2016 secunet Security Networks AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Include this file into a mainboard's DSDT _SB device tree and it will
- * expose the IT8786E SuperIO and some of its functionality.
- *
- * It allows the change of IO ports, IRQs and DMA settings on logical
- * devices, disabling and reenabling logical devices.
- *
- * LDN State
- * 0x1 UARTA Implemented, untested
- * 0x2 UARTB Implemented, untested
- * 0x3 PP Not implemented
- * 0x4 EC Not implemented
- * 0x5 KBC Implemented, untested
- * 0x6 MOUSE Implemented, untested
- * 0x7 GPIO Not implemented
- * 0x8 UARTC Implemented, untested
- * 0x9 UARTD Implemented, untested
- * 0xa UARTE Not implemented
- * 0xb UARTF Not implemented
- * 0xc CIR Not implemented
- *
- * Controllable through preprocessor defines:
- * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
- * SUPERIO_PNP_BASE I/O address of the first PnP configuration register
- * IT8786E_SHOW_UARTA If defined, UARTA will be exposed.
- * IT8786E_SHOW_UARTB If defined, UARTB will be exposed.
- * IT8786E_SHOW_UARTC If defined, UARTC will be exposed.
- * IT8786E_SHOW_UARTD If defined, UARTD will be exposed.
- * IT8786E_SHOW_KBC If defined, the KBC will be exposed.
- * IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
- */
-
-#undef SUPERIO_CHIP_NAME
-#define SUPERIO_CHIP_NAME IT8786E
-#include <superio/acpi/pnp.asl>
-
-#undef PNP_DEFAULT_PSC
-#define PNP_DEFAULT_PSC Return (0) /* no power management */
-
-#define CONFIGURE_CONTROL CCTL
-
-Device (SUPERIO_DEV) {
- Name (_HID, EisaId("PNP0A05"))
- Name (_STR, Unicode("ITE IT8786E Super I/O"))
- Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
-
- /* Mutex for accesses to the configuration ports */
- Mutex (CRMX, 1)
-
- /* SuperIO configuration ports */
- OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
- Field (CREG, ByteAcc, NoLock, Preserve)
- {
- PNP_ADDR_REG, 8,
- PNP_DATA_REG, 8
- }
- IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
- {
- Offset (0x02),
- CONFIGURE_CONTROL, 8, /* Global configure control */
-
- Offset (0x07),
- PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
-
- Offset (0x30),
- PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
-
- Offset (0x60),
- PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
- PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
- Offset (0x62),
- PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
- PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
-
- Offset (0x70),
- PNP_IRQ0, 8, /* First IRQ */
- }
-
- Method (_CRS)
- {
- /* Announce the used i/o ports to the OS */
- Return (ResourceTemplate () {
- IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE,
- 0x01, 0x02)
- })
- }
-
- #undef PNP_ENTER_MAGIC_1ST
- #undef PNP_ENTER_MAGIC_2ND
- #undef PNP_ENTER_MAGIC_3RD
- #undef PNP_ENTER_MAGIC_4TH
- #undef PNP_EXIT_MAGIC_1ST
- #define PNP_ENTER_MAGIC_1ST 0x87
- #define PNP_ENTER_MAGIC_2ND 0x01
- #define PNP_ENTER_MAGIC_3RD 0x55
-#if SUPERIO_PNP_BASE == 0x2e
- #define PNP_ENTER_MAGIC_4TH 0x55
-#else
- #define PNP_ENTER_MAGIC_4TH 0xaa
-#endif
- #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
- #define PNP_EXIT_SPECIAL_VAL 0x02
- #include <superio/acpi/pnp_config.asl>
-
-#ifdef IT8786E_SHOW_UARTA
- #undef SUPERIO_UART_LDN
- #undef SUPERIO_UART_DDN
- #undef SUPERIO_UART_PM_REG
- #undef SUPERIO_UART_PM_VAL
- #undef SUPERIO_UART_PM_LDN
- #define SUPERIO_UART_LDN 1
- #include <superio/acpi/pnp_uart.asl>
-#endif
-
-#ifdef IT8786E_SHOW_UARTB
- #undef SUPERIO_UART_LDN
- #undef SUPERIO_UART_DDN
- #undef SUPERIO_UART_PM_REG
- #undef SUPERIO_UART_PM_VAL
- #undef SUPERIO_UART_PM_LDN
- #define SUPERIO_UART_LDN 2
- #include <superio/acpi/pnp_uart.asl>
-#endif
-
-#ifdef IT8786E_SHOW_KBC
- #undef SUPERIO_KBC_LDN
- #undef SUPERIO_KBC_PS2M
- #undef SUPERIO_KBC_PS2LDN
- #define SUPERIO_KBC_LDN 5
-#ifdef IT8786E_SHOW_PS2M
- #define SUPERIO_KBC_PS2LDN 6
-#endif
- #include <superio/acpi/pnp_kbc.asl>
-#endif
-
-#ifdef IT8786E_SHOW_UARTC
- #undef SUPERIO_UART_LDN
- #undef SUPERIO_UART_DDN
- #undef SUPERIO_UART_PM_REG
- #undef SUPERIO_UART_PM_VAL
- #undef SUPERIO_UART_PM_LDN
- #define SUPERIO_UART_LDN 8
- #include <superio/acpi/pnp_uart.asl>
-#endif
-
-#ifdef IT8786E_SHOW_UARTD
- #undef SUPERIO_UART_LDN
- #undef SUPERIO_UART_DDN
- #undef SUPERIO_UART_PM_REG
- #undef SUPERIO_UART_PM_VAL
- #undef SUPERIO_UART_PM_LDN
- #define SUPERIO_UART_LDN 9
- #include <superio/acpi/pnp_uart.asl>
-#endif
-}
diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h
deleted file mode 100644
index 4b2e811..0000000
--- a/src/superio/ite/it8786e/chip.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 secunet Security Networks AG
- * Copyright (C) 2019 Libretrend LDA
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_ITE_IT8786E_CHIP_H
-#define SUPERIO_ITE_IT8786E_CHIP_H
-
-#include <superio/ite/common/env_ctrl_chip.h>
-
-struct superio_ite_it8786e_config {
- struct ite_ec_config ec;
-};
-
-#endif /* SUPERIO_ITE_IT8786E_CHIP_H */
diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h
deleted file mode 100644
index 5f11b63..0000000
--- a/src/superio/ite/it8786e/it8786e.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 secunet Security Networks AG
- * Copyright (C) 2019 Libretrend LDA
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_ITE_IT8786E_H
-#define SUPERIO_ITE_IT8786E_H
-
-#define IT8786E_SP1 0x01 /* COM1 */
-#define IT8786E_SP2 0x02 /* COM2 */
-#define IT8786E_PP 0x03 /* Printer port */
-#define IT8786E_EC 0x04 /* Environment controller */
-#define IT8786E_KBCK 0x05 /* Keyboard */
-#define IT8786E_KBCM 0x06 /* Mouse */
-#define IT8786E_GPIO 0x07 /* GPIO */
-#define IT8786E_SP3 0x08 /* COM3 */
-#define IT8786E_SP4 0x09 /* COM4 */
-#define IT8786E_CIR 0x0a /* Consumer IR */
-#define IT8786E_SP5 0x0b /* COM5 */
-#define IT8786E_SP6 0x0c /* COM6 */
-
-#include <stdint.h>
-
-#endif /* SUPERIO_ITE_IT8786E_H */
diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c
deleted file mode 100644
index ac9dc4b..0000000
--- a/src/superio/ite/it8786e/superio.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 secunet Security Networks AG
- * Copyright (C) 2019 Libretrend LDA
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <superio/conf_mode.h>
-#include <superio/ite/common/env_ctrl.h>
-
-#include "it8786e.h"
-#include "chip.h"
-
-static void it8786e_init(struct device *const dev)
-{
- const struct superio_ite_it8786e_config *conf;
- const struct resource *res;
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case IT8786E_EC:
- conf = dev->chip_info;
- res = find_resource(dev, PNP_IDX_IO0);
- if (!conf || !res)
- break;
- ite_ec_init(res->base, &conf->ec);
- break;
- case IT8786E_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- default:
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = it8786e_init,
- .ops_pnp_mode = &pnp_conf_mode_870155_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- /* Serial Port 1 */
- { NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
- PNP_MSC2,
- 0x0ff8, },
- /* Serial Port 2 */
- { NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
- PNP_MSC2,
- 0x0ff8, },
- /* Printer Port */
- { NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 |
- PNP_MSC0,
- 0x0ff8, 0x0ffc, },
- /* Environmental Controller */
- { NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 |
- PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 |
- PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB |
- PNP_MSCC,
- 0x0ff8, 0x0ffc, },
- /* KBC Keyboard */
- { NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
- 0x0fff, 0x0fff, },
- /* KBC Mouse */
- { NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, },
- /* GPIO */
- { NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 |
- PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 |
- PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
- PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB,
- 0x0ffc, 0x0fff, },
- /* Serial Port 3 */
- { NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
- PNP_MSC2,
- 0x0ff8, },
- /* Serial Port 4 */
- { NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
- PNP_MSC2,
- 0x0ff8, },
- /* Consumer Infrared */
- { NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
- /* Serial Port 5 */
- { NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
- PNP_MSC2,
- 0x0ff8, },
- /* Serial Port 6 */
- { NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
- PNP_MSC2,
- 0x0ff8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_ite_it8786e_ops = {
- CHIP_NAME("ITE IT8786E Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/nsc/pc87309/Kconfig b/src/superio/nsc/pc87309/Kconfig
deleted file mode 100644
index ff72706..0000000
--- a/src/superio/nsc/pc87309/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_NSC_PC87309
- bool
- select SUPERIO_NSC_COMMON_PRE_RAM
diff --git a/src/superio/nsc/pc87309/Makefile.inc b/src/superio/nsc/pc87309/Makefile.inc
deleted file mode 100644
index 6c7a8ab..0000000
--- a/src/superio/nsc/pc87309/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_NSC_PC87309) += superio.c
diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h
deleted file mode 100644
index 3b912ea..0000000
--- a/src/superio/nsc/pc87309/pc87309.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87309_H
-#define SUPERIO_NSC_PC87309_H
-
-/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */
-
-#define PC87309_FDC 0x00 /* Floppy */
-#define PC87309_PP 0x01 /* Parallel port */
-#define PC87309_SP2 0x02 /* Com2 / IR */
-#define PC87309_SP1 0x03 /* Com1 */
-#define PC87309_PM 0x04 /* Power management */
-#define PC87309_KBCM 0x05 /* Mouse */
-#define PC87309_KBCK 0x06 /* Keyboard */
-
-#endif /* SUPERIO_NSC_PC87309_H */
diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c
deleted file mode 100644
index 4f8f967..0000000
--- a/src/superio/nsc/pc87309/superio.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "pc87309.h"
-
-static void init(struct device *dev)
-{
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case PC87309_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_enable,
- .init = init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
- 0x07f8, },
- { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- /* TODO: PM. */
- { NULL, PC87309_KBCM, PNP_IRQ0, },
- { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nsc_pc87309_ops = {
- CHIP_NAME("NSC PC87309 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/nsc/pc87360/Kconfig b/src/superio/nsc/pc87360/Kconfig
deleted file mode 100644
index b70b935..0000000
--- a/src/superio/nsc/pc87360/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_NSC_PC87360
- bool
- select SUPERIO_NSC_COMMON_PRE_RAM
diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc
deleted file mode 100644
index 81e2d3d..0000000
--- a/src/superio/nsc/pc87360/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c
diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h
deleted file mode 100644
index c969746..0000000
--- a/src/superio/nsc/pc87360/pc87360.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87360_H
-#define SUPERIO_NSC_PC87360_H
-
-#define PC87360_FDC 0x00 /* Floppy */
-#define PC87360_PP 0x01 /* Parallel port */
-#define PC87360_SP2 0x02 /* Com2 */
-#define PC87360_SP1 0x03 /* Com1 */
-#define PC87360_SWC 0x04
-#define PC87360_KBCM 0x05 /* Mouse */
-#define PC87360_KBCK 0x06 /* Keyboard */
-#define PC87360_GPIO 0x07
-#define PC87360_ACB 0x08
-#define PC87360_FSCM 0x09
-#define PC87360_WDT 0x0A
-
-#endif /* SUPERIO_NSC_PC87360_H */
diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c
deleted file mode 100644
index 33f27e1..0000000
--- a/src/superio/nsc/pc87360/superio.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "pc87360.h"
-
-static void init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case PC87360_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_enable,
- .init = init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
- 0x07f8, },
- { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87360_KBCM, PNP_IRQ0, },
- { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nsc_pc87360_ops = {
- CHIP_NAME("NSC PC87360 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/nsc/pc87366/Kconfig b/src/superio/nsc/pc87366/Kconfig
deleted file mode 100644
index bf17117..0000000
--- a/src/superio/nsc/pc87366/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_NSC_PC87366
- bool
- select SUPERIO_NSC_COMMON_PRE_RAM
diff --git a/src/superio/nsc/pc87366/Makefile.inc b/src/superio/nsc/pc87366/Makefile.inc
deleted file mode 100644
index f432530..0000000
--- a/src/superio/nsc/pc87366/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c
diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h
deleted file mode 100644
index b1df69f..0000000
--- a/src/superio/nsc/pc87366/pc87366.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87366_H
-#define SUPERIO_NSC_PC87366_H
-
-#define PC87366_FDC 0x00 /* Floppy */
-#define PC87366_PP 0x01 /* Parallel port */
-#define PC87366_SP2 0x02 /* Com2 */
-#define PC87366_SP1 0x03 /* Com1 */
-#define PC87366_SWC 0x04
-#define PC87366_KBCM 0x05 /* Mouse */
-#define PC87366_KBCK 0x06 /* Keyboard */
-#define PC87366_GPIO 0x07
-#define PC87366_ACB 0x08
-#define PC87366_FSCM 0x09
-#define PC87366_WDT 0x0A
-#define PC87366_GMP 0x0b
-#define PC87366_MIDI 0x0C
-#define PC87366_VLM 0x0D
-#define PC87366_TMS 0x0E
-
-#endif /* SUPERIO_NSC_PC87366_H */
diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c
deleted file mode 100644
index 6d8c66e..0000000
--- a/src/superio/nsc/pc87366/superio.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "pc87366.h"
-
-static void init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case PC87366_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_enable,
- .init = init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
- 0x07f8, },
- { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87366_KBCM, PNP_IRQ0, },
- { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nsc_pc87366_ops = {
- CHIP_NAME("NSC PC87366 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/nsc/pc97317/Kconfig b/src/superio/nsc/pc97317/Kconfig
deleted file mode 100644
index 38f6d34..0000000
--- a/src/superio/nsc/pc97317/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_NSC_PC97317
- bool
diff --git a/src/superio/nsc/pc97317/Makefile.inc b/src/superio/nsc/pc97317/Makefile.inc
deleted file mode 100644
index 2f8ee76..0000000
--- a/src/superio/nsc/pc97317/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c
-romstage-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c
diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c
deleted file mode 100644
index 74489fa..0000000
--- a/src/superio/nsc/pc97317/early_serial.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp.h>
-#include <stdint.h>
-#include "pc97317.h"
-
-#define PM_DEV PNP_DEV(0x2e, PC97317_PM)
-#define PM_BASE 0xe8
-
-/* The PC97317 needs clocks to be set up before the serial port will operate. */
-void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- /* Set base address of power management unit. */
- pnp_set_logical_device(PM_DEV);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
- pnp_set_enable(dev, 1);
-
- /* Use on-chip clock multiplier. */
- outb(0x03, PM_BASE);
- outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
-
- /* Wait for the clock to stabilise. */
- while(!(inb(PM_BASE + 1) & 0x80))
- ;
-
- /* Set the base address of the port. */
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc97317/pc97317.h b/src/superio/nsc/pc97317/pc97317.h
deleted file mode 100644
index 76717fa..0000000
--- a/src/superio/nsc/pc97317/pc97317.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC97317_H
-#define SUPERIO_NSC_PC97317_H
-
-#define PC97317_KBCK 0x00 /* Keyboard */
-#define PC97317_KBCM 0x01 /* Mouse */
-#define PC97317_RTC 0x02 /* Real-Time Clock */
-#define PC97317_FDC 0x03 /* Floppy */
-#define PC97317_PP 0x04 /* Parallel port */
-#define PC97317_SP2 0x05 /* Com2 */
-#define PC97317_SP1 0x06 /* Com1 */
-#define PC97317_GPIO 0x07
-#define PC97317_PM 0x08 /* Power Management */
-
-#include <device/pnp_type.h>
-#include <stdint.h>
-
-void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif /* SUPERIO_NSC_PC97317_H */
diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c
deleted file mode 100644
index 42f5434..0000000
--- a/src/superio/nsc/pc97317/superio.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <stdlib.h>
-#include <pc80/keyboard.h>
-#include "pc97317.h"
-
-static void init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case PC97317_KBCK:
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0); /* Disable keyboard */
- pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
- pnp_set_enable(dev, 1); /* Enable keyboard */
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- default:
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_enable,
- .init = init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, },
- { NULL, PC97317_KBCM, PNP_IRQ0, },
- { NULL, PC97317_RTC, PNP_IO0 | PNP_IRQ0, 0xfffe, },
- { NULL, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xfff8, },
- { NULL, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x03fc, },
- { NULL, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
- 0xfff8, },
- { NULL, PC97317_SP1, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC97317_GPIO, PNP_IO0, 0xfff8, },
- { NULL, PC97317_PM, PNP_IO0, 0xfffe, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nsc_pc97317_ops = {
- CHIP_NAME("NSC PC97317 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c
index 29418db..eaa3c5a 100644
--- a/src/superio/nuvoton/common/early_serial.c
+++ b/src/superio/nuvoton/common/early_serial.c
@@ -65,10 +65,6 @@
{
nuvoton_pnp_enter_conf_state(dev);
- if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A))
- /* Route COM A to GPIO8 pin group */
- pnp_write_config(dev, 0x2a, 0x40);
-
if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A))
/* Route COM A to GPIO8 pin group */
pnp_write_config(dev, 0x2a, 0x40);
diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig
deleted file mode 100644
index 0dd1402..0000000
--- a/src/superio/nuvoton/nct5539d/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_NUVOTON_NCT5539D
- bool
- select SUPERIO_NUVOTON_COMMON_PRE_RAM
-
-config SUPERIO_NUVOTON_NCT5539D_COM_A
- bool
- depends on SUPERIO_NUVOTON_NCT5539D
- default n
diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc
deleted file mode 100644
index 6e3fdf2..0000000
--- a/src/superio/nuvoton/nct5539d/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c
diff --git a/src/superio/nuvoton/nct5539d/nct5539d.h b/src/superio/nuvoton/nct5539d/nct5539d.h
deleted file mode 100644
index d4e8d08..0000000
--- a/src/superio/nuvoton/nct5539d/nct5539d.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NUVOTON_NCT5539D_H
-#define SUPERIO_NUVOTON_NCT5539D_H
-
-/* Logical Device Numbers (LDN). */
-#define NCT5539D_SP1 0x02 /* UART A */
-#define NCT5539D_KBC 0x05 /* Keyboard Controller */
-#define NCT5539D_CIR 0x06 /* Consumer IR */
-#define NCT5539D_GPIO78 0x07 /* GPIO 7 & 8 */
-#define NCT5539D_WDT1_WDT3_GPIO0 0x08 /* WDT1, WDT3, GPIO 0 & KBC P20 */
-#define NCT5539D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */
-#define NCT5539D_ACPI 0x0A /* ACPI */
-#define NCT5539D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */
-#define NCT5539D_WDT2 0x0D /* WDT2 */
-#define NCT5539D_CIRWUP 0x0E /* CIR Wake-Up */
-#define NCT5539D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */
-#define NCT5539D_GPIO_PSO 0x11 /* GPIO, RI PSOUT Wake-Up Status */
-#define NCT5539D_SWEC 0x12 /* SW Error Control */
-#define NCT5539D_FLED 0x15 /* Fading LED */
-#define NCT5539D_DS 0x16 /* Deep Sleep */
-
-/* Virtual LDNs */
-#define NCT5539D_WDT1 ((0 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
-#define NCT5539D_WDT3 ((4 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
-#define NCT5539D_GPIOBASE ((3 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
-#define NCT5539D_GPIO0 ((1 << 8) | NCT5539D_WDT1_WDT3_GPIO0)
-#define NCT5539D_GPIO2 ((0 << 8) | NCT5539D_GPIO2345)
-#define NCT5539D_GPIO3 ((1 << 8) | NCT5539D_GPIO2345)
-#define NCT5539D_GPIO4 ((2 << 8) | NCT5539D_GPIO2345)
-#define NCT5539D_GPIO5 ((3 << 8) | NCT5539D_GPIO2345)
-#define NCT5539D_GPIO7 ((1 << 8) | NCT5539D_GPIO78)
-#define NCT5539D_GPIO8 ((2 << 8) | NCT5539D_GPIO78)
-#define NCT5539D_DS5 ((0 << 8) | NCT5539D_DS)
-#define NCT5539D_DS3 ((1 << 8) | NCT5539D_DS)
-
-#endif /* SUPERIO_NUVOTON_NCT5539D_H */
diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c
deleted file mode 100644
index e38f845..0000000
--- a/src/superio/nuvoton/nct5539d/superio.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
- * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com>
- * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
-* Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include <superio/conf_mode.h>
-
-#include "nct5539d.h"
-
-
-static void nct5539d_init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case NCT5539D_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = nct5539d_init,
- .ops_pnp_mode = &pnp_conf_mode_8787_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0,
- 0x0ff8, },
- { NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
- 0x0fff, 0x0fff, },
- { NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0,
- 0x0ff8, },
- { NULL, NCT5539D_ACPI},
- { NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IRQ0,
- 0x0ffe, 0x0ffe, },
- { NULL, NCT5539D_WDT2},
- { NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0,
- 0x0ff8, },
- { NULL, NCT5539D_GPIO_PP_OD},
- { NULL, NCT5539D_WDT1},
- { NULL, NCT5539D_WDT3},
- { NULL, NCT5539D_GPIOBASE, PNP_IO0,
- 0x0ff8, },
- { NULL, NCT5539D_GPIO0},
- { NULL, NCT5539D_GPIO2},
- { NULL, NCT5539D_GPIO3},
- { NULL, NCT5539D_GPIO4},
- { NULL, NCT5539D_GPIO5},
- { NULL, NCT5539D_GPIO7},
- { NULL, NCT5539D_GPIO8},
- { NULL, NCT5539D_GPIO_PSO},
- { NULL, NCT5539D_SWEC},
- { NULL, NCT5539D_FLED},
- { NULL, NCT5539D_DS5},
- { NULL, NCT5539D_DS3},
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_nuvoton_nct5539d_ops = {
- CHIP_NAME("NUVOTON NCT5539D Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/smsc/dme1737/Kconfig b/src/superio/smsc/dme1737/Kconfig
deleted file mode 100644
index 20cb12c..0000000
--- a/src/superio/smsc/dme1737/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_SMSC_DME1737
- bool
diff --git a/src/superio/smsc/dme1737/Makefile.inc b/src/superio/smsc/dme1737/Makefile.inc
deleted file mode 100644
index e106a02..0000000
--- a/src/superio/smsc/dme1737/Makefile.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c
-romstage-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_SMSC_DME1737) += superio.c
diff --git a/src/superio/smsc/dme1737/dme1737.h b/src/superio/smsc/dme1737/dme1737.h
deleted file mode 100644
index f40cc35..0000000
--- a/src/superio/smsc/dme1737/dme1737.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_SMSC_DME1737_H
-#define SUPERIO_SMSC_DME1737_H
-
-#define DME1737_FDC 0 /* Floppy */
-#define DME1737_PP 3 /* Parallel Port */
-#define DME1737_SP1 4 /* Com1 */
-#define DME1737_SP2 5 /* Com2 */
-#define DME1737_KBC 7 /* Keyboard & Mouse */
-#define DME1737_RT 10 /* Runtime reg*/
-
-#include <device/pnp_type.h>
-#include <stdint.h>
-
-void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif /* SUPERIO_SMSC_DME1737_H */
diff --git a/src/superio/smsc/dme1737/early_serial.c b/src/superio/smsc/dme1737/early_serial.c
deleted file mode 100644
index 58ad177..0000000
--- a/src/superio/smsc/dme1737/early_serial.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp.h>
-#include <stdint.h>
-#include "dme1737.h"
-
-static void pnp_enter_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c
deleted file mode 100644
index 0bfd3b8..0000000
--- a/src/superio/smsc/dme1737/superio.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <device/smbus.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "dme1737.h"
-
-static void dme1737_init(struct device *dev)
-{
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case DME1737_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = dme1737_init,
- .ops_pnp_mode = &pnp_conf_mode_55_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, DME1737_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, DME1737_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
- 0x07ff, 0x07ff, },
- { NULL, DME1737_RT, PNP_IO0, 0x0780, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_smsc_dme1737_ops = {
- CHIP_NAME("SMSC DME1737 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/smsc/lpc47b272/Kconfig b/src/superio/smsc/lpc47b272/Kconfig
deleted file mode 100644
index 07e6472..0000000
--- a/src/superio/smsc/lpc47b272/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_SMSC_LPC47B272
- bool
diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc
deleted file mode 100644
index 51d77d4..0000000
--- a/src/superio/smsc/lpc47b272/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2005 Digital Design Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c
-romstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c
diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c
deleted file mode 100644
index 26fdfaf..0000000
--- a/src/superio/smsc/lpc47b272/early_serial.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp.h>
-#include <stdint.h>
-#include "lpc47b272.h"
-
-static void pnp_enter_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47b272/lpc47b272.h b/src/superio/smsc/lpc47b272/lpc47b272.h
deleted file mode 100644
index 3fbd043..0000000
--- a/src/superio/smsc/lpc47b272/lpc47b272.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_SMSC_LPC47B272_H
-#define SUPERIO_SMSC_LPC47B272_H
-
-#define LPC47B272_FDC 0 /* Floppy */
-#define LPC47B272_PP 3 /* Parallel Port */
-#define LPC47B272_SP1 4 /* Com1 */
-#define LPC47B272_SP2 5 /* Com2 */
-#define LPC47B272_KBC 7 /* Keyboard & Mouse */
-#define LPC47B272_RT 10 /* Runtime reg*/
-
-#define LPC47B272_MAX_CONFIG_REGISTER 0x5F
-
-#include <device/pnp_type.h>
-#include <stdint.h>
-
-void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif /* SUPERIO_SMSC_LPC47B272_H */
diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c
deleted file mode 100644
index 6ac2d6d..0000000
--- a/src/superio/smsc/lpc47b272/superio.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* RAM driver for SMSC LPC47B272 Super I/O chip. */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <device/smbus.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "lpc47b272.h"
-
-/**
- * Initialize the specified Super I/O device.
- *
- * Devices other than COM ports and the keyboard controller are ignored.
- * For COM ports, we configure the baud rate.
- *
- * @param dev Pointer to structure describing a Super I/O device.
- */
-static void lpc47b272_init(struct device *dev)
-{
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case LPC47B272_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = lpc47b272_init,
- .ops_pnp_mode = &pnp_conf_mode_55_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
- 0x07ff, 0x07ff, },
- { NULL, LPC47B272_RT, PNP_IO0, 0x0780, },
-};
-
-/**
- * Create device structures and allocate resources to devices specified in the
- * pnp_dev_info array (above).
- *
- * @param dev Pointer to structure describing a Super I/O device.
- */
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_smsc_lpc47b272_ops = {
- CHIP_NAME("SMSC LPC47B272 Super I/O")
- .enable_dev = enable_dev
-};
diff --git a/src/superio/smsc/lpc47b397/Kconfig b/src/superio/smsc/lpc47b397/Kconfig
deleted file mode 100644
index 80264c4..0000000
--- a/src/superio/smsc/lpc47b397/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_SMSC_LPC47B397
- bool
diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc
deleted file mode 100644
index ddb251d..0000000
--- a/src/superio/smsc/lpc47b397/Makefile.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-## Copyright (C) 2004 Tyan
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c
-romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c
diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c
deleted file mode 100644
index a07cd99..0000000
--- a/src/superio/smsc/lpc47b397/early_serial.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp.h>
-#include <stdint.h>
-#include "lpc47b397.h"
-
-static void pnp_enter_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47b397/lpc47b397.h b/src/superio/smsc/lpc47b397/lpc47b397.h
deleted file mode 100644
index 5f3a504..0000000
--- a/src/superio/smsc/lpc47b397/lpc47b397.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_SMSC_LPC47B397_H
-#define SUPERIO_SMSC_LPC47B397_H
-
-#define LPC47B397_FDC 0 /* Floppy */
-#define LPC47B397_PP 3 /* Parallel Port */
-#define LPC47B397_SP1 4 /* Com1 */
-#define LPC47B397_SP2 5 /* Com2 */
-#define LPC47B397_KBC 7 /* Keyboard & Mouse */
-#define LPC47B397_HWM 8 /* HW Monitor */
-#define LPC47B397_RT 10 /* Runtime reg*/
-
-#include <device/pnp_type.h>
-#include <stdint.h>
-
-void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif /* SUPERIO_SMSC_LPC47B397_H */
diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c
deleted file mode 100644
index 4b9e345..0000000
--- a/src/superio/smsc/lpc47b397/superio.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <console/console.h>
-#include <device/smbus.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "lpc47b397.h"
-
-static void enable_hwm_smbus(struct device *dev)
-{
- /* Enable SensorBus register access. */
- u8 reg8;
-
- reg8 = pnp_read_config(dev, 0xf0);
- reg8 |= (1 << 1);
- pnp_write_config(dev, 0xf0, reg8);
-}
-
-static void lpc47b397_init(struct device *dev)
-{
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case LPC47B397_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static void lpc47b397_pnp_enable_resources(struct device *dev)
-{
- pnp_enable_resources(dev);
-
- pnp_enter_conf_mode(dev);
- switch (dev->path.pnp.device) {
- case LPC47B397_HWM:
- printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n");
- pnp_set_logical_device(dev);
- enable_hwm_smbus(dev);
- break;
- }
- /* dump_pnp_device(dev); */
- pnp_exit_conf_mode(dev);
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = lpc47b397_pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = lpc47b397_init,
- .ops_pnp_mode = &pnp_conf_mode_55_aa,
-};
-
-#define HWM_INDEX 0
-#define HWM_DATA 1
-#define SB_INDEX 0x0b
-#define SB_DATA0 0x0c
-#define SB_DATA1 0x0d
-#define SB_DATA2 0x0e
-#define SB_DATA3 0x0f
-
-static int lsmbus_read_byte(struct device *dev, u8 address)
-{
- unsigned int device;
- struct resource *res;
- int result;
-
- device = dev->path.i2c.device;
-
- res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
-
- pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */
-
- /* We only read it one byte one time. */
- result = pnp_read_index(res->base + SB_INDEX, address);
-
- return result;
-}
-
-static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
-
- pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */
-
- /* We only write it one byte one time. */
- pnp_write_index(res->base+SB_INDEX, address, val);
-
- return 0;
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
- /* .recv_byte = lsmbus_recv_byte, */
- /* .send_byte = lsmbus_send_byte, */
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
-};
-
-static struct device_operations ops_hwm = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = lpc47b397_pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = lpc47b397_init,
- .ops_smbus_bus = &lops_smbus_bus,
- .ops_pnp_mode = &pnp_conf_mode_55_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
- 0x07ff, 0x07ff, },
- { &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, },
- { NULL, LPC47B397_RT, PNP_IO0, 0x0780, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_smsc_lpc47b397_ops = {
- CHIP_NAME("SMSC LPC47B397 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/smsc/sch4037/Kconfig b/src/superio/smsc/sch4037/Kconfig
deleted file mode 100644
index ce87f75..0000000
--- a/src/superio/smsc/sch4037/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_SMSC_SCH4037
- bool
diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc
deleted file mode 100644
index ac7d7de..0000000
--- a/src/superio/smsc/sch4037/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-bootblock-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c
-romstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += sch4037_early_init.c
-ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c
diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h
deleted file mode 100644
index f0fa3cd..0000000
--- a/src/superio/smsc/sch4037/sch4037.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_SCH_4037_H
-#define SUPERIO_SCH_4037_H
-
-#define SCH4037_FDD 0 /* FDD */
-#define SCH4037_LPT 3 /* LPT */
-#define SMSCSUPERIO_SP1 4 /* Com1 */
-#define SMSCSUPERIO_SP2 5 /* Com2 */
-#define SCH4037_RTC 6 /* RTC */
-#define SCH4037_KBC 7 /* KBC */
-#define SCH4037_HWM 8 /* HWM */
-#define SCH4037_RUNTIME 0x0A /* Runtime */
-#define SCH4037_XBUS 0x0B /* X-BUS */
-
-void sch4037_early_init(unsigned port);
-
-#endif /* SUPERIO_SCH_4037_H */
diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c
deleted file mode 100644
index a416ab8..0000000
--- a/src/superio/smsc/sch4037/sch4037_early_init.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp.h>
-#include <stdint.h>
-
-#include "sch4037.h"
-
-static void pnp_enter_conf_state(pnp_devfn_t dev)
-{
- unsigned port = dev >> 8;
- outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(pnp_devfn_t dev)
-{
- unsigned port = dev >> 8;
- outb(0xaa, port);
-}
-
-void sch4037_early_init(unsigned port)
-{
- pnp_devfn_t dev;
-
- dev = PNP_DEV(port, SMSCSUPERIO_SP1);
- pnp_enter_conf_state(dev);
-
- /* Auto power management */
- pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
- pnp_write_config(dev, 0x23, 0);
-
- /* Enable SMSC UART 0 */
- dev = PNP_DEV(port, SMSCSUPERIO_SP1);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
-
- pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
- pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
-
- /* Enabled High speed, disabled MIDI support. */
- pnp_write_config(dev, 0xF0, 0x02);
- pnp_set_enable(dev, 1);
-
- /* Enable keyboard */
- dev = PNP_DEV(port, SCH4037_KBC);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
- pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
- pnp_set_enable(dev, 1);
-
- pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c
deleted file mode 100644
index 5e49aa7..0000000
--- a/src/superio/smsc/sch4037/superio.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* RAM driver for the SMSC KBC1100 Super I/O chip */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-
-#include "sch4037.h"
-
-static void sch4037_init(struct device *dev)
-{
- if (!dev->enabled) {
- return;
- }
-
- switch (dev->path.pnp.device) {
- case SCH4037_KBC:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = sch4037_init,
- .ops_pnp_mode = &pnp_conf_mode_55_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
- 0x7ff, 0x7ff, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_smsc_sch4037_ops = {
- CHIP_NAME("SMSC SCH4037 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/smsc/sio1036/Kconfig b/src/superio/smsc/sio1036/Kconfig
deleted file mode 100644
index df519de..0000000
--- a/src/superio/smsc/sio1036/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_SMSC_SIO1036
- bool
diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc
deleted file mode 100644
index e9fdae2..0000000
--- a/src/superio/smsc/sio1036/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c
-romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c
-ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c
diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h
deleted file mode 100644
index 610beba..0000000
--- a/src/superio/smsc/sio1036/sio1036.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_SMSC_SIO1306_H
-#define SUPERIO_SMSC_SIO1306_H
-
-#define SIO1036_SP1 0 /* Com1 */
-
-#define UART_POWER_DOWN (1 << 7)
-#define LPT_POWER_DOWN (1 << 2)
-#define IR_OUTPUT_MUX (1 << 6)
-
-#include <device/pnp_type.h>
-#include <stdint.h>
-
-void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif /* SUPERIO_SMSC_SIO1306_H */
diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c
deleted file mode 100644
index 47f317f..0000000
--- a/src/superio/smsc/sio1036/sio1036_early_init.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <stdint.h>
-
-#include "sio1036.h"
-
-static inline void sio1036_enter_conf_state(pnp_devfn_t dev)
-{
- unsigned port = dev >> 8;
- outb(0x55, port);
-}
-
-static inline void sio1036_exit_conf_state(pnp_devfn_t dev)
-{
- unsigned port = dev >> 8;
- outb(0xaa, port);
-}
-
-/* Detect SMSC SIO1036 LPC Debug Card status */
-static u8 detect_sio1036_chip(unsigned port)
-{
- pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1);
- unsigned data;
-
- sio1036_enter_conf_state(dev);
- data = pnp_read_config(dev, 0x0D);
- sio1036_exit_conf_state(dev);
-
- /* Detect SMSC SIO1036 chip */
- if (data == 0x82) {
- /* Found SMSC SIO1036 chip */
- return 0;
- }
- else {
- return 1;
- };
-}
-
-void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- unsigned port = dev >> 8;
-
- if (detect_sio1036_chip(port) != 0)
- return;
-
- sio1036_enter_conf_state(dev);
-
- /* Enable SMSC UART 0 */
- /* Valid configuration cycle */
- pnp_write_config(dev, 0x00, 0x28);
-
- /* PP power/mode/cr lock */
- pnp_write_config(dev, 0x01, 0x98 | LPT_POWER_DOWN);
- pnp_write_config(dev, 0x02, 0x08 | UART_POWER_DOWN);
-
- /*Auto power management*/
- pnp_write_config(dev, 0x07, 0x00);
-
- /*ECP FIFO threhod */
- pnp_write_config(dev, 0x0A, 0x00 | IR_OUTPUT_MUX);
-
- /*GPIO direction register 2 */
- pnp_write_config(dev, 0x033, 0x00);
-
- /*UART Mode */
- pnp_write_config(dev, 0x0C, 0x02);
-
- /* GPIO polarity regisgter 2 */
- pnp_write_config(dev, 0x034, 0x00);
-
- /* Enable SMSC UART 0 */
- /*Set base io address */
- pnp_write_config(dev, 0x25, (u8)(iobase >> 2));
-
- /* Set UART IRQ onto 0x04 */
- pnp_write_config(dev, 0x28, 0x04);
-
- sio1036_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c
deleted file mode 100644
index a192831..0000000
--- a/src/superio/smsc/sio1036/superio.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* RAM driver for the SMSC SIO1036 Super I/O chip */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <stdlib.h>
-
-#include "sio1036.h"
-
-static void sio1036_init(struct device *dev)
-{
- if (!dev->enabled) {
- return;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = sio1036_init,
- .ops_pnp_mode = &pnp_conf_mode_55_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_smsc_sio1036_ops = {
- CHIP_NAME("SMSC SIO1036 Super I/O")
- .enable_dev = enable_dev
-};
diff --git a/src/superio/via/vt1211/Kconfig b/src/superio/via/vt1211/Kconfig
deleted file mode 100644
index b2de1d3..0000000
--- a/src/superio/via/vt1211/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_VIA_VT1211
- bool
diff --git a/src/superio/via/vt1211/Makefile.inc b/src/superio/via/vt1211/Makefile.inc
deleted file mode 100644
index d3044af..0000000
--- a/src/superio/via/vt1211/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += superio.c
diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c
deleted file mode 100644
index 4d7c8de..0000000
--- a/src/superio/via/vt1211/superio.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <stdlib.h>
-#include "vt1211.h"
-
-static u8 hwm_io_regs[] = {
- 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f,
- 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a,
- 0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00,
- 0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67,
- 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2,
- 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00,
- 0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff,
- 0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff,
- 0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff,
- 0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff,
- 0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff,
- 0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0,
- 0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77,
- 0x5c,0x00, 0x5f,0x33, 0x40,0x01,
-};
-
-static void vt1211_set_iobase(struct device *dev, u8 index, u16 iobase)
-{
- switch (dev->path.pnp.device) {
- case VT1211_FDC:
- case VT1211_PP:
- case VT1211_SP1:
- case VT1211_SP2:
- pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff);
- break;
- case VT1211_ROM:
- /* TODO: Error. VT1211_ROM doesn't have an I/O base. */
- break;
- case VT1211_MIDI:
- case VT1211_GAME:
- case VT1211_GPIO:
- case VT1211_WDG:
- case VT1211_WUC:
- case VT1211_HWM:
- case VT1211_FIR:
- default:
- pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
- pnp_write_config(dev, index + 1, iobase & 0xff);
- break;
- }
-}
-
-/* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */
-static void init_hwm(u16 base)
-{
- int i;
-
- for (i = 0; i < sizeof(hwm_io_regs); i += 2)
- outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]);
-}
-
-static void vt1211_init(struct device *dev)
-{
- struct resource *res0;
-
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case VT1211_HWM:
- res0 = find_resource(dev, PNP_IDX_IO0);
- init_hwm(res0->base);
- break;
- case VT1211_FDC:
- case VT1211_PP:
- case VT1211_MIDI:
- case VT1211_GAME:
- case VT1211_GPIO:
- case VT1211_WDG:
- case VT1211_WUC:
- case VT1211_FIR:
- case VT1211_ROM:
- /* TODO: Any init needed for these LDNs? */
- break;
- default:
- printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n");
- }
-}
-
-static void vt1211_pnp_enable_resources(struct device *dev)
-{
- printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev));
- pnp_enable_resources(dev);
-}
-
-static void vt1211_pnp_set_resources(struct device *dev)
-{
- struct resource *res;
-
-#if CONFIG(CONSOLE_SERIAL) && CONFIG(DRIVERS_UART_8250IO)
- /* TODO: Do the same for SP2? */
- if (dev->path.pnp.device == VT1211_SP1) {
- for (res = dev->resource_list; res; res = res->next) {
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
- return;
- }
-#endif
-
- pnp_enter_conf_mode(dev);
-
- pnp_set_logical_device(dev);
-
- /* Paranoia says I should disable the device here... */
- for (res = dev->resource_list; res; res = res->next) {
- if (!(res->flags & IORESOURCE_ASSIGNED)) {
- printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx "
- "not assigned\n", dev_path(dev), res->index,
- resource_type(res), res->size);
- continue;
- }
-
- /* Now store the resource. */
- if (res->flags & IORESOURCE_IO) {
- vt1211_set_iobase(dev, res->index, res->base);
- } else if (res->flags & IORESOURCE_DRQ) {
- pnp_set_drq(dev, res->index, res->base);
- } else if (res->flags & IORESOURCE_IRQ) {
- pnp_set_irq(dev, res->index, res->base);
- } else {
- printk(BIOS_ERR, "ERROR: %s %02lx unknown resource "
- "type\n", dev_path(dev), res->index);
- return;
- }
- res->flags |= IORESOURCE_STORED;
-
- report_resource_stored(dev, res, "");
- }
-
- pnp_exit_conf_mode(dev);
-}
-
-struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = vt1211_pnp_set_resources,
- .enable_resources = vt1211_pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = vt1211_init,
- .ops_pnp_mode = &pnp_conf_mode_8787_aa,
-};
-
-/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
-static struct pnp_info pnp_dev_info[] = {
- { NULL, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, VT1211_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, VT1211_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, 0xfffc, },
- { NULL, VT1211_GAME, PNP_IO0, 0xfff8, },
- { NULL, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, VT1211_WDG, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, VT1211_WUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, VT1211_HWM, PNP_IO0 | PNP_IRQ0, 0xff00, },
- { NULL, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xff00, },
- { NULL, VT1211_ROM, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_via_vt1211_ops = {
- CHIP_NAME("VIA VT1211 Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/via/vt1211/vt1211.h b/src/superio/via/vt1211/vt1211.h
deleted file mode 100644
index 9f0a1ef..0000000
--- a/src/superio/via/vt1211/vt1211.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_VIA_VT1211_VT1211_H
-#define SUPERIO_VIA_VT1211_VT1211_H
-
-/* Logical device numbers (LDNs). */
-#define VT1211_FDC 0x00 /* Floppy */
-#define VT1211_PP 0x01 /* Parallel port */
-#define VT1211_SP1 0x02 /* COM1 */
-#define VT1211_SP2 0x03 /* COM2 */
-#define VT1211_MIDI 0x06 /* MIDI */
-#define VT1211_GAME 0x07 /* Game port (GMP) */
-#define VT1211_GPIO 0x08 /* GPIO */
-#define VT1211_WDG 0x09 /* Watchdog timer (WDG) */
-#define VT1211_WUC 0x0a /* Wake-up control (WUC) */
-#define VT1211_HWM 0x0b /* Hardware monitor (HM) */
-#define VT1211_FIR 0x0c /* Very fast IR (VFIR/FIR) */
-#define VT1211_ROM 0x0d /* Flash ROM */
-
-#endif
diff --git a/src/superio/winbond/w83697hf/Kconfig b/src/superio/winbond/w83697hf/Kconfig
deleted file mode 100644
index 6ca03fe..0000000
--- a/src/superio/winbond/w83697hf/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_WINBOND_W83697HF
- bool
- select SUPERIO_WINBOND_COMMON_PRE_RAM
diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc
deleted file mode 100644
index d1ef2b0..0000000
--- a/src/superio/winbond/w83697hf/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c
diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h
deleted file mode 100644
index f7fc798..0000000
--- a/src/superio/winbond/w83697hf/chip.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_WINBOND_W83697HF_CHIP_H
-#define SUPERIO_WINBOND_W83697HF_CHIP_H
-
-
-struct superio_winbond_w83697hf_config {
- unsigned int hwmon_fan1_divisor;
- unsigned int hwmon_fan2_divisor;
-};
-
-#endif /* SUPERIO_WINBOND_W83697HF_CHIP_H */
diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c
deleted file mode 100644
index a3c132c..0000000
--- a/src/superio/winbond/w83697hf/superio.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include <superio/conf_mode.h>
-#include <console/console.h>
-#include <lib.h>
-#include <stdlib.h>
-#include "chip.h"
-#include "w83697hf.h"
-
-static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) {
- unsigned char enc, buf;
-
- if (divisor) {
- enc = log2(divisor);
- if (1 << enc != divisor || enc > 7)
- die("invalid fan divisor");
- outb(0x4e, base + 5);
- outb(0x00, base + 6);
- outb(0x47, base + 5);
- outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6);
- outb(0x5d, base + 5);
- buf = inb(base + 6);
- /* the above inb() auto-increments the address pointer ... */
- outb(0x5d, base + 5);
- outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6);
- }
-}
-
-static void w83697hf_init(struct device *dev)
-{
- struct resource *res0;
- struct superio_winbond_w83697hf_config *cfg;
-
- if (!dev->enabled)
- return;
-
- cfg = dev->chip_info;
-
- switch (dev->path.pnp.device) {
- case W83697HF_HWM:
- if (cfg) {
- res0 = find_resource(dev, PNP_IDX_IO0);
- hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor);
- hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor);
- }
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_alt_enable,
- .init = w83697hf_init,
- .ops_pnp_mode = &pnp_conf_mode_8787_aa,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
- 0x07ff, 0x07fe, },
- { NULL, W83697HF_MIDI_GPIO5, },
- { NULL, W83697HF_GPIO234, },
- { NULL, W83697HF_ACPI, },
- { NULL, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_winbond_w83697hf_ops = {
- CHIP_NAME("Winbond W83697HF Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h
deleted file mode 100644
index 52466a8..0000000
--- a/src/superio/winbond/w83697hf/w83697hf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_WINBOND_W83697HF_H
-#define SUPERIO_WINBOND_W83697HF_H
-
-#define W83697HF_FDC 0 /* Floppy */
-#define W83697HF_PP 1 /* Parallel port */
-#define W83697HF_SP1 2 /* Com1 */
-#define W83697HF_SP2 3 /* Com2 */
-#define W83697HF_CIR 6 /* Consumer IR */
-#define W83697HF_GAME_GPIO1 7 /* Game port, GPIO 1 */
-#define W83697HF_MIDI_GPIO5 8 /* MIDI, GPIO 5 */
-#define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */
-#define W83697HF_ACPI 10 /* ACPI */
-#define W83697HF_HWM 11 /* Hardware monitor */
-
-#endif /* SUPERIO_WINBOND_W83697HF_H */
diff --git a/src/superio/winbond/wpcd376i/Kconfig b/src/superio/winbond/wpcd376i/Kconfig
deleted file mode 100644
index 57cce7b..0000000
--- a/src/superio/winbond/wpcd376i/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SUPERIO_WINBOND_WPCD376I
- bool
- select SUPERIO_WINBOND_COMMON_PRE_RAM
diff --git a/src/superio/winbond/wpcd376i/Makefile.inc b/src/superio/winbond/wpcd376i/Makefile.inc
deleted file mode 100644
index cebd175..0000000
--- a/src/superio/winbond/wpcd376i/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2000 AG Electronics Ltd.
-## Copyright (C) 2003-2004 Linux Networx
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-bootblock-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c
-romstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c
-ramstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += superio.c
diff --git a/src/superio/winbond/wpcd376i/chip.h b/src/superio/winbond/wpcd376i/chip.h
deleted file mode 100644
index c16743d..0000000
--- a/src/superio/winbond/wpcd376i/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_WINBOND_WPCD376I_CHIP_H
-#define SUPERIO_WINBOND_WPCD376I_CHIP_H
-
-struct superio_winbond_wpcd376i_config {
-};
-#endif
diff --git a/src/superio/winbond/wpcd376i/early_serial.c b/src/superio/winbond/wpcd376i/early_serial.c
deleted file mode 100644
index 9f9ff6b..0000000
--- a/src/superio/winbond/wpcd376i/early_serial.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Pre-RAM driver for the Winbond WPCD376I Super I/O chip. */
-
-
-#include <device/pnp_ops.h>
-#include <device/pnp_def.h>
-#include "wpcd376i.h"
-
-void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c
deleted file mode 100644
index ae4fce4..0000000
--- a/src/superio/winbond/wpcd376i/superio.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pnp.h>
-#include <drivers/uart/uart8250reg.h>
-#include <pc80/keyboard.h>
-#include <stdlib.h>
-#include "chip.h"
-#include "wpcd376i.h"
-
-static void init(struct device *dev)
-{
- if (!dev->enabled)
- return;
-
- switch (dev->path.pnp.device) {
- case WPCD376I_KBCK:
- pc_keyboard_init(NO_AUX_DEVICE);
- break;
- }
-}
-
-static struct device_operations ops = {
- .read_resources = pnp_read_resources,
- .set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
- .enable = pnp_enable,
- .init = init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
- { NULL, WPCD376I_FDC,
- PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC8,
- 0x07f8, },
- { NULL, WPCD376I_LPT,
- PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC8,
- 0x03f8, },
- { NULL, WPCD376I_SP1,
- PNP_IO0 | PNP_IRQ0 | PNP_MSC0,
- 0x07f8, },
- { NULL, WPCD376I_SWC,
- PNP_IO0 | PNP_IO1 | PNP_IRQ0,
- 0xfff0, 0xfff0, },
- { NULL, WPCD376I_KBCM,
- PNP_IRQ0, },
- { NULL, WPCD376I_KBCK,
- PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
- 0x07f8, 0x07f8, },
- { NULL, WPCD376I_GPIO,
- PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 |
- PNP_MSC8,
- 0xffe0, },
- { NULL, WPCD376I_ECIR,
- PNP_IO0 | PNP_IO1 | PNP_IRQ0,
- 0xfff0, 0xfff0, },
- { NULL, WPCD376I_IR,
- PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1 | PNP_MSC0,
- 0xfff8, },
-};
-
-static void enable_dev(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
-struct chip_operations superio_winbond_wpcd376i_ops = {
- CHIP_NAME("Winbond WPCD376I Super I/O")
- .enable_dev = enable_dev,
-};
diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h
deleted file mode 100644
index a90b13b..0000000
--- a/src/superio/winbond/wpcd376i/wpcd376i.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H
-#define SUPERIO_WINBOND_WPCD376I_WPCD376I_H
-
-#include <device/pnp_type.h>
-
-/* Logical Device Numbers (LDN). */
-#define WPCD376I_FDC 0x00 /* Floppy */
-#define WPCD376I_LPT 0x01 /* Parallel port */
-/* 0x02 Undefined */
-#define WPCD376I_SP1 0x03 /* UART1 */
-#define WPCD376I_SWC 0x04 /* System wake-up control */
-#define WPCD376I_KBCM 0x05 /* PS/2 mouse */
-#define WPCD376I_KBCK 0x06 /* PS/2 keyboard */
-#define WPCD376I_GPIO 0x07 /* General Purpose I/O */
-#define WPCD376I_ECIR 0x15 /* Enhanced Consumer Infrared Functions (ECIR) */
-#define WPCD376I_IR 0x16 /* UART3 & Infrared port */
-
-void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase);
-
-#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4
Gerrit-Change-Number: 35428
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
6
17
Change in ...coreboot[master]: arch/x86: Add option for running Romstage out of RAM
by Martin Roth (Code Review) 23 Jan '20
by Martin Roth (Code Review) 23 Jan '20
23 Jan '20
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32414
Change subject: arch/x86: Add option for running Romstage out of RAM
......................................................................
arch/x86: Add option for running Romstage out of RAM
AMD's Picasso SOC brings up memory before releasing the X86 processor,
and jumps directly to Romstage. Add a global config option to handle
that.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
---
M src/Kconfig
M src/arch/x86/assembly_entry.S
M src/arch/x86/memlayout.ld
3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32414/1
diff --git a/src/Kconfig b/src/Kconfig
index 62b3818..bfa0b51 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -146,6 +146,16 @@
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.
+config ROMSTAGE_IN_RAM
+ bool
+ depends on ARCH_X86
+ help
+ Some newer x86 processors come alive with memory enabled, and the
+ reset vector's physical address falling within DRAM. Select this
+ item to build romstage to execute in DRAM instead of XIP. Because
+ this is not a standard, the soc/ or cpu/ code must handle the reset
+ natively before jumping into the standard romstage code.
+
config COMPRESS_BOOTBLOCK
bool
help
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 4ead9ea..01c0865 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -26,6 +26,16 @@
* variables that are stage specific.
*/
.section ".text._start", "ax", @progbits
+#if ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_IN_RAM)
+/*
+ * Systems that run romstage in DRAM, i.e. where romstage is the first
+ * executed code, are responsible for getting the processor into protected
+ * mode, setting the stack pointer, and jumping to this location.
+ */
+.global _romstage_in_ram_continue
+_romstage_in_ram_continue:
+
+#else
.global _start
_start:
@@ -34,6 +44,7 @@
/* reset stack pointer to CAR stack */
mov $_car_stack_end, %esp
+#endif
/* clear CAR_GLOBAL area as it is not shared */
cld
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index cc72552..da63b05 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -57,6 +57,10 @@
#endif
}
+#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM)
+#include <soc/romstage.ld>
+#endif
+
#if ENV_BOOTBLOCK
/* Bootblock specific scripts which provide more SECTION directives. */
#include <cpu/x86/16bit/entry16.ld>
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
Gerrit-Change-Number: 32414
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
8
40
Change in ...coreboot[master]: HACK PATCH: SDM845: Enable DFS mode for QUP
by mturney mturney (Code Review) 21 Jan '20
by mturney mturney (Code Review) 21 Jan '20
21 Jan '20
mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33813
Change subject: HACK PATCH: SDM845: Enable DFS mode for QUP
......................................................................
HACK PATCH: SDM845: Enable DFS mode for QUP
Enable DFS mode for QUP which are PORed with I2C & SPI use case in kernel.
Change-Id: Id36f20c562337c645db8fc127fe0370d4b0c10fa
Signed-off-by: Akash Asthana <akashast(a)codeaurora.org>
---
M src/mainboard/google/cheza/mainboard.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33813/1
diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c
index 1a2e42a..a5d1bdb 100644
--- a/src/mainboard/google/cheza/mainboard.c
+++ b/src/mainboard/google/cheza/mainboard.c
@@ -82,6 +82,14 @@
qupv3_fw_init();
setup_usb();
i2c_init(QUPV3_1_SE4, I2C_SPEED_FAST); /* Speaker amp */
+ write32((void *)0x117048, 0x21);
+ write32((void *)0x1172a8, 0x21);
+ write32((void *)0x1173d8, 0x21);
+ write32((void *)0x117638, 0x21);
+ write32((void *)0x11828c, 0x21);
+ write32((void *)0x1183bc, 0x21);
+ write32((void *)0x1184ec, 0x21);
+ write32((void *)0x11874c, 0x21);
sdm845_sound_init();
}
--
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Gerrit-Change-Id: Id36f20c562337c645db8fc127fe0370d4b0c10fa
Gerrit-Change-Number: 33813
Gerrit-PatchSet: 1
Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com>
Gerrit-MessageType: newchange
1
1