Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33777
Change subject: asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836
......................................................................
asus/am1i-a: set VGA_BIOS_ID to 1002,9830 instead of default 1002,9836
The majority of Socket AM1 APUs [1] - three out of five (three Athlons, the
most powerful for this socket) - have the integrated VGA with 1002,9830 ID,
while only one Sempron has 1002,9836. Set the default to more common one.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22K…
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
---
M src/mainboard/asus/am1i-a/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/33777/1
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
index d50edbe..42ab5c6 100644
--- a/src/mainboard/asus/am1i-a/Kconfig
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -44,7 +44,7 @@
config VGA_BIOS_ID
string
- default "1002,9836"
+ default "1002,9830"
config HUDSON_LEGACY_FREE
bool
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Gerrit-Change-Number: 33777
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33872
Change subject: MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A
......................................................................
MAINTAINERS: Add myself as a maintainer for Lenovo G505S and ASUS AM1I-A
These are the boards I have and currently working on.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I874770813a96ecd27138b02a16f6bc737572351a
---
M MAINTAINERS
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33872/1
diff --git a/MAINTAINERS b/MAINTAINERS
index 73ca6df..14d075a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -164,6 +164,11 @@
S: Maintained
F: src/mainboard/lenovo/
+LENOVO G505S MAINBOARD
+M: Mike Banon <mikebdp2(a)gmail.com>
+S: Maintained
+F: src/mainboard/lenovo/g505s
+
APPLE MAINBOARDS
M: Evgeny Zinoviev <me(a)ch1p.io>
S: Maintained
@@ -333,6 +338,11 @@
S: Maintained
F: src/mainboard/asrock/h81m-hds/
+ASUS AM1I-A MAINBOARD
+M: Mike Banon <mikebdp2(a)gmail.com>
+S: Maintained
+F: src/mainboard/asus/am1i-a
+
ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
M: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
S: Supported
--
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Gerrit-Branch: master
Gerrit-Change-Id: I874770813a96ecd27138b02a16f6bc737572351a
Gerrit-Change-Number: 33872
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
Ravi Chandra Sadineni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34801 )
Change subject: chromeec: Depend on events_copy_b to identify the wake source.
......................................................................
chromeec: Depend on events_copy_b to identify the wake source.
Using google_chromeec_get_event() clears the event too. Thus if the
kernel has to identify the wake source, it has no way to do that. Thus
instead depend on events_copy_b to log the wake source. Please look at
go/hostevent-refactor for more info.
BUG=b:133262012
BRANCH=None
TEST=Hack hatch bios and make sure hostevent log is correct.
Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c
Signed-off-by: Ravi Chandra Sadineni <ravisadineni(a)chromium.org>
---
M src/ec/google/chromeec/ec.c
1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34801/1
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 5a2630e..9ba9b1b 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -428,7 +428,8 @@
void google_chromeec_log_events(uint64_t mask)
{
- u8 event;
+ u64 events;
+ int i;
uint64_t wake_mask;
bool restore_wake_mask = false;
@@ -445,11 +446,14 @@
restore_wake_mask = true;
}
- while ((event = google_chromeec_get_event()) != 0) {
- if (EC_HOST_EVENT_MASK(event) & mask)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
+ events = google_chromeec_get_events_b() & mask;
+ for (i = 0; i < sizeof(events) * 8; i++) {
+ if (EC_HOST_EVENT_MASK(i) & events)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, i);
}
+ google_chromeec_clear_events_b(events);
+
if (restore_wake_mask)
google_chromeec_set_wake_mask(wake_mask);
}
@@ -467,10 +471,6 @@
/* Disable SMI and wake events. */
google_chromeec_set_smi_mask(0);
- /* Clear pending events. */
- while (google_chromeec_get_event() != 0)
- ;
-
/* Restore SCI event mask. */
google_chromeec_set_sci_mask(info->sci_events);
--
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Gerrit-Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c
Gerrit-Change-Number: 34801
Gerrit-PatchSet: 1
Gerrit-Owner: Ravi Chandra Sadineni <ravisadineni(a)chromium.org>
Gerrit-MessageType: newchange
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35429 )
Change subject: PDCurses: Remove unused code/directories
......................................................................
PDCurses: Remove unused code/directories
There are a number of directories that came in with pdcurses that we
don't need as a part of libpayload. Get rid of them.
Signed-off-by: Martin Roth <martin(a)coreboot.org>
Change-Id: I3b09104f64254d768d27a3d2e3fba8418e7ba2ca
---
D payloads/libpayload/curses/PDCurses/demos/README
D payloads/libpayload/curses/PDCurses/demos/firework.c
D payloads/libpayload/curses/PDCurses/demos/newdemo.c
D payloads/libpayload/curses/PDCurses/demos/ptest.c
D payloads/libpayload/curses/PDCurses/demos/rain.c
D payloads/libpayload/curses/PDCurses/demos/testcurs.c
D payloads/libpayload/curses/PDCurses/demos/tui.c
D payloads/libpayload/curses/PDCurses/demos/tui.h
D payloads/libpayload/curses/PDCurses/demos/tuidemo.c
D payloads/libpayload/curses/PDCurses/demos/worm.c
D payloads/libpayload/curses/PDCurses/demos/xmas.c
D payloads/libpayload/curses/PDCurses/dos/README
D payloads/libpayload/curses/PDCurses/dos/bccdos.lrf
D payloads/libpayload/curses/PDCurses/dos/bccdos.mak
D payloads/libpayload/curses/PDCurses/dos/gccdos.mak
D payloads/libpayload/curses/PDCurses/dos/mscdos.lrf
D payloads/libpayload/curses/PDCurses/dos/mscdos.mak
D payloads/libpayload/curses/PDCurses/dos/pdcclip.c
D payloads/libpayload/curses/PDCurses/dos/pdcdisp.c
D payloads/libpayload/curses/PDCurses/dos/pdcdos.h
D payloads/libpayload/curses/PDCurses/dos/pdcgetsc.c
D payloads/libpayload/curses/PDCurses/dos/pdckbd.c
D payloads/libpayload/curses/PDCurses/dos/pdcscrn.c
D payloads/libpayload/curses/PDCurses/dos/pdcsetsc.c
D payloads/libpayload/curses/PDCurses/dos/pdcutil.c
D payloads/libpayload/curses/PDCurses/dos/wccdos16.mak
D payloads/libpayload/curses/PDCurses/dos/wccdos4g.mak
D payloads/libpayload/curses/PDCurses/os2/README
D payloads/libpayload/curses/PDCurses/os2/bccos2.mak
D payloads/libpayload/curses/PDCurses/os2/gccos2.mak
D payloads/libpayload/curses/PDCurses/os2/iccos2.lrf
D payloads/libpayload/curses/PDCurses/os2/iccos2.mak
D payloads/libpayload/curses/PDCurses/os2/pdcclip.c
D payloads/libpayload/curses/PDCurses/os2/pdcdisp.c
D payloads/libpayload/curses/PDCurses/os2/pdcgetsc.c
D payloads/libpayload/curses/PDCurses/os2/pdckbd.c
D payloads/libpayload/curses/PDCurses/os2/pdcos2.h
D payloads/libpayload/curses/PDCurses/os2/pdcscrn.c
D payloads/libpayload/curses/PDCurses/os2/pdcsetsc.c
D payloads/libpayload/curses/PDCurses/os2/pdcutil.c
D payloads/libpayload/curses/PDCurses/os2/wccos2.mak
D payloads/libpayload/curses/PDCurses/sdl1/Makefile
D payloads/libpayload/curses/PDCurses/sdl1/Makefile.mng
D payloads/libpayload/curses/PDCurses/sdl1/README
D payloads/libpayload/curses/PDCurses/sdl1/deffont.h
D payloads/libpayload/curses/PDCurses/sdl1/deficon.h
D payloads/libpayload/curses/PDCurses/sdl1/pdcclip.c
D payloads/libpayload/curses/PDCurses/sdl1/pdcdisp.c
D payloads/libpayload/curses/PDCurses/sdl1/pdcgetsc.c
D payloads/libpayload/curses/PDCurses/sdl1/pdckbd.c
D payloads/libpayload/curses/PDCurses/sdl1/pdcscrn.c
D payloads/libpayload/curses/PDCurses/sdl1/pdcsdl.h
D payloads/libpayload/curses/PDCurses/sdl1/pdcsetsc.c
D payloads/libpayload/curses/PDCurses/sdl1/pdcutil.c
D payloads/libpayload/curses/PDCurses/sdl1/sdltest.c
D payloads/libpayload/curses/PDCurses/win32/README
D payloads/libpayload/curses/PDCurses/win32/bccwin32.mak
D payloads/libpayload/curses/PDCurses/win32/dmcwin32.mak
D payloads/libpayload/curses/PDCurses/win32/gccwin32.mak
D payloads/libpayload/curses/PDCurses/win32/lccwin32.mak
D payloads/libpayload/curses/PDCurses/win32/mingwin32.mak
D payloads/libpayload/curses/PDCurses/win32/pdcclip.c
D payloads/libpayload/curses/PDCurses/win32/pdcdisp.c
D payloads/libpayload/curses/PDCurses/win32/pdcgetsc.c
D payloads/libpayload/curses/PDCurses/win32/pdckbd.c
D payloads/libpayload/curses/PDCurses/win32/pdcscrn.c
D payloads/libpayload/curses/PDCurses/win32/pdcsetsc.c
D payloads/libpayload/curses/PDCurses/win32/pdcurses.ico
D payloads/libpayload/curses/PDCurses/win32/pdcurses.rc
D payloads/libpayload/curses/PDCurses/win32/pdcutil.c
D payloads/libpayload/curses/PDCurses/win32/pdcwin.h
D payloads/libpayload/curses/PDCurses/win32/vcwin32.mak
D payloads/libpayload/curses/PDCurses/win32/wccwin32.mak
D payloads/libpayload/curses/PDCurses/x11/Makefile.aix.in
D payloads/libpayload/curses/PDCurses/x11/Makefile.in
D payloads/libpayload/curses/PDCurses/x11/README
D payloads/libpayload/curses/PDCurses/x11/ScrollBox.c
D payloads/libpayload/curses/PDCurses/x11/ScrollBox.h
D payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h
D payloads/libpayload/curses/PDCurses/x11/big_icon.xbm
D payloads/libpayload/curses/PDCurses/x11/compose.h
D payloads/libpayload/curses/PDCurses/x11/little_icon.xbm
D payloads/libpayload/curses/PDCurses/x11/ncurses_cfg.h
D payloads/libpayload/curses/PDCurses/x11/pdcclip.c
D payloads/libpayload/curses/PDCurses/x11/pdcdisp.c
D payloads/libpayload/curses/PDCurses/x11/pdcgetsc.c
D payloads/libpayload/curses/PDCurses/x11/pdckbd.c
D payloads/libpayload/curses/PDCurses/x11/pdcscrn.c
D payloads/libpayload/curses/PDCurses/x11/pdcsetsc.c
D payloads/libpayload/curses/PDCurses/x11/pdcutil.c
D payloads/libpayload/curses/PDCurses/x11/pdcx11.c
D payloads/libpayload/curses/PDCurses/x11/pdcx11.h
D payloads/libpayload/curses/PDCurses/x11/sb.c
D payloads/libpayload/curses/PDCurses/x11/x11.c
D payloads/libpayload/curses/PDCurses/x11/xcurses-config.in
95 files changed, 0 insertions(+), 20,512 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35429/1
--
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Gerrit-Change-Id: I3b09104f64254d768d27a3d2e3fba8418e7ba2ca
Gerrit-Change-Number: 35429
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30856
Change subject: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
......................................................................
arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
This was used to enforce 4kiB alignment of _start16bit in
romcc bootblock. Platforms requiring this moved away to
C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment.
Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/failover.ld
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/model_106cx/Kconfig
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_mPGA604/Kconfig
M src/cpu/x86/16bit/entry16.inc
7 files changed, 5 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 242a7cf..c2fc914 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -81,13 +81,6 @@
default n
depends on ARCH_X86 && SMP
-# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
-# can boot AP CPUs to enable their shared caches.
-config SIPI_VECTOR_IN_ROM
- bool
- default n
- depends on ARCH_X86
-
# Set the rambase for systems that still need it, only 5 chipsets as of
# Sep 2018. This value was 0x100000, chosen to match the entry point
# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
index b32aa29..eabc9f7 100644
--- a/src/arch/x86/failover.ld
+++ b/src/arch/x86/failover.ld
@@ -23,12 +23,11 @@
TARGET(binary)
SECTIONS
{
- /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
- * with Startup IPI message without RAM. Align .rom to next 4 byte
- * boundary anyway, so no pad byte appears between _rom and _start.
+ /* Align .rom to 4 byte boundary so no pad byte appears
+ * between _rom and _start.
*/
.bogus ROMLOC_MIN : {
- . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
+ . = ALIGN(4);
ROMLOC = .;
} >rom = 0xff
@@ -49,12 +48,7 @@
* may cause the total size of a section to change when the start
* address gets applied.
*/
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
-
- /* Post-check proper SIPI vector. */
- _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff),
- "Address mismatch on AP_SIPI_VECTOR");
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
/DISCARD/ : {
*(.comment)
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index fda572d..5c579a1 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,10 +23,6 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
-/* Fixed location, ASSERTED in failover.ld if it changes. */
-.set ap_sipi_vector_in_rom, 0xff
-#endif
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index f365cf1..2a324fb 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -7,7 +7,6 @@
select SMP
select SSE2
select UDELAY_LAPIC
- select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..6c3d837 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -13,7 +13,6 @@
select CPU_INTEL_MODEL_1067X
select MMX
select SSE
- select SIPI_VECTOR_IN_ROM
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index ca2f7b3..e860ded 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -9,7 +9,6 @@
select MMX
select SSE
select UDELAY_TSC
- select SIPI_VECTOR_IN_ROM
select C_ENVIRONMENT_BOOTBLOCK
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2a9f8c5..f110980 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,8 +29,7 @@
#include <arch/rom_segs.h>
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
- IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
--
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Gerrit-Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396
Gerrit-Change-Number: 30856
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34662 )
Change subject: Documentation/binaries: Add AMD FSP documentation
......................................................................
Documentation/binaries: Add AMD FSP documentation
Create a document explaining, at a high level, the differences between
Intel's FSP and the one developed by AMD.
BUG=none.
TEST=none.
Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59
Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
---
A Documentation/binaries/AMD_FSP_family_17h.md
A Documentation/binaries/index.md
2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34662/1
diff --git a/Documentation/binaries/AMD_FSP_family_17h.md b/Documentation/binaries/AMD_FSP_family_17h.md
new file mode 100644
index 0000000..b46beb3
--- /dev/null
+++ b/Documentation/binaries/AMD_FSP_family_17h.md
@@ -0,0 +1,41 @@
+# FSP implementation differences between Intel and AMD
+
+## Introduction
+Starting with family 17h, AMD is developing an "_As Close As Possible_" FSP
+binary. However, some premisses are different for family 17h and beyond,
+making it necessary to have some FSP implementation differences. Some other
+implementation differences were more of an engineering decision.
+
+The family 17h deviation from older AMD and Intel CPU/SOC are:
+* The memory is initialized by the PSP (similar to Intel's ME) ARM.
+* There's _**no support**_ for cache as RAM.
+* Reset vector is not the old 0xFFFFFFF0.
+
+This document is a "work in progress", documenting the differences at a
+high level. This document will be updated as more information becomes
+available.
+
+## Differences caused by differences in premisses
+1. **No FSP-T**
+Because family 17h does not support CAR, there's no FSP-T.
+2. **FSP-M only reports memory**
+Because memory is inittialized by the PSP, FSP-M only reports the final
+memory configuration.
+3. **FSP-M is loaded to DRAM**
+PSP can be made to load a section of the flash into RAM before releasing
+the reset, thus FSP-M can be made to run directly from memory.
+4. **FSP-M can be made position independent**
+Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC
+(Position Independent Code).
+
+## Differences by engineering decision
+1. **Memory fragmentation**
+Though FSP still fragments memory, it has added control for flexibility
+of where the chunks will reside.
+2. **UPD interface**
+UPD interface uses native intergers and don't need to be packed by compiler.
+3. **UPD with no UEFI dependencies**
+UPD interface can be made C99 or C11 compatible with no hard dependencies
+to UEFI.
+4. **Platform specific code**
+Similar to AGESA, FSP will make call back to platform specific code.
diff --git a/Documentation/binaries/index.md b/Documentation/binaries/index.md
new file mode 100644
index 0000000..9093bf7
--- /dev/null
+++ b/Documentation/binaries/index.md
@@ -0,0 +1,8 @@
+# binaries-specific documentation
+
+This section contains documentation about any binary used by coreboot
+
+## Video
+
+## Platform initialization
+- [AMD FSP](AMD_FSP_family_17h.md)
--
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