coreboot-gerrit September 2019

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Change in ...coreboot[master]: google/mistral: Enable additional GBB flags in vboot.
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31171 Change subject: google/mistral: Enable additional GBB flags in vboot. ...................................................................... google/mistral: Enable additional GBB flags in vboot. Enable GBB_FLAG_FORCE_MANUAL_RECOVERY and GBB_FLAG_DEV_SCREEN_SHORT_DELAY as additional default flags. Change-Id: If1e7effb2d74b861f196ce861a3c8779ce89b3b2 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 --- M src/mainboard/google/mistral/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31171/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index c369472..5e97bb6 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -20,7 +20,9 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 Gerrit-Change-Number: 31171 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qclib: Differentiate between ES_1.0 and ES1.1 silicon
by Name of user not set (Code Review) 11 Mar '20

11 Mar '20

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30903 Change subject: qclib: Differentiate between ES_1.0 and ES1.1 silicon ...................................................................... qclib: Differentiate between ES_1.0 and ES1.1 silicon The PBL data ptr gets passed at a different location for 1.0 vs 1.1. So let us read the revision from TCSR and pass the right value. Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/qclib_execute.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30903/1 diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c index 917a04c..214128f 100644 --- a/src/soc/qualcomm/qcs405/qclib_execute.c +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -14,6 +14,7 @@ */ #include <string.h> +#include <arch/io.h> #include <arch/cache.h> #include <arch/mmu.h> #include <cbfs.h> @@ -28,7 +29,12 @@ #define DCB_NAME "/dcb" #define QCLIB_NAME "/qclib" -#define PBL_DATA_PTR 0x8c101a0 //0x14810188 +#define TCSR_SOC_HW_VERSION 0x0194D000 +#define ES_1_0 0x20140100 +#define ES_1_1 0x20140101 + +#define PBL_DATA_PTR_ES_1_0 0x8c101a0 +#define PBL_DATA_PTR_ES_1_1 0x8c111a0 void qclib_load_and_run(void) { @@ -36,6 +42,7 @@ void *arg; int ret_code; struct mmu_context pre_qclib_mmu_context; + void *pbl_data_ptr; struct prog qclib = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); @@ -67,7 +74,12 @@ if (cbfs_prog_stage_load(&qclib)) goto fail; - prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + if (read32((void *) TCSR_SOC_HW_VERSION) == ES_1_1) + pbl_data_ptr = (void *) 0x8c111a0; + else + pbl_data_ptr = (void *) 0x8c101a0; + + prog_set_entry(&qclib, qclib.entry, (void *)pbl_data_ptr); printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/30903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Gerrit-Change-Number: 30903 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: Update memory layout
by Name of user not set (Code Review) 11 Mar '20

11 Mar '20

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32108 Change subject: qcs405: Update memory layout ...................................................................... qcs405: Update memory layout Update the memory layout so that we get to use the unused space. This enables us to use default kernel size of 512 MB configuration in depthcharge. Change-Id: I419bfefadb610c3fdf2b8ed56965801be0dc4e90 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32108/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 68642d6..6856919 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -45,6 +45,6 @@ DRAM_START(0x80000000) /* DDR Carveout for BL31 usage */ REGION(dram_reserved, 0x85000000, 0x5100000, 4096) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + POSTRAM_CBFS_CACHE(0x8A100000, 384K) + RAMSTAGE(0x8A160000, 128K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/32108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419bfefadb610c3fdf2b8ed56965801be0dc4e90 Gerrit-Change-Number: 32108 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistral: move bootblock and fmap to their previous location
by Patrick Georgi (Code Review) 11 Mar '20

11 Mar '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30965 Change subject: google/mistral: move bootblock and fmap to their previous location ...................................................................... google/mistral: move bootblock and fmap to their previous location Helps with the current boot hack that requires them to be at certain locations. Also make GBB smaller. We don't store graphics in there anymore. Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30965/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index a9bdd7b..ffeec16 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -2,9 +2,9 @@ WP_RO@0x0 0x400000 { RO_SECTION@0x0 0x3e0000 { BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x2e0000 - FMAP@0x300000 0x1000 - GBB@0x301000 0xdef00 + COREBOOT(CBFS)@0x3e000 0x1e0000 + FMAP@0x21e000 0x1000 + GBB@0x3dd000 0x2f00 RO_FRID@0x3dff00 0x100 } RO_VPD@0x3e0000 0x20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/30965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Gerrit-Change-Number: 30965 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/common: Add more GPIO definition macros
by Thomas Heijligen (Code Review) 10 Mar '20

10 Mar '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31350 to review the following change. Change subject: soc/intel/common: Add more GPIO definition macros ...................................................................... soc/intel/common: Add more GPIO definition macros Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31350/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9..4d9f2be 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -236,6 +236,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Gerrit-Change-Number: 31350 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34714 ) Change subject: soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling ...................................................................... soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling This code also sets unused interrupt lines to the recommended safe value of 0xff instead of ignoring such devices. Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434 Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/lpc.c 1 file changed, 259 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/34714/1 diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 5af0781..5f43e63 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -65,6 +65,261 @@ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } +/* interrupt router lookup for internal devices */ +struct dnv_ir_lut { + /* (dev << 3) | fn */ + u8 devfn; + u8 ir; +}; + +#define DEVFN(dev, fn) ((dev << 3) | (fn)) + +static const struct dnv_ir_lut dnv_ir_lut[] = { + {.devfn = DEVFN(0x05, 0), .ir = 3}, /* RCEC */ + {.devfn = DEVFN(0x06, 0), .ir = 4}, /* Virtual RP to QAT */ + {.devfn = DEVFN(0x09, 0), .ir = 7}, /* PCIe RP0 */ + {.devfn = DEVFN(0x0a, 0), .ir = 7}, /* PCIe RP1 */ + {.devfn = DEVFN(0x0b, 0), .ir = 7}, /* PCIe RP2 */ + {.devfn = DEVFN(0x0c, 0), .ir = 7}, /* PCIe RP3 */ + {.devfn = DEVFN(0x0e, 0), .ir = 8}, /* PCIe RP4 */ + {.devfn = DEVFN(0x0f, 0), .ir = 8}, /* PCIe RP5 */ + {.devfn = DEVFN(0x10, 0), .ir = 8}, /* PCIe RP6 */ + {.devfn = DEVFN(0x11, 0), .ir = 8}, /* PCIe RP7 */ + {.devfn = DEVFN(0x12, 0), .ir = 10}, /* SMBus - Host */ + {.devfn = DEVFN(0x13, 0), .ir = 6}, /* AHCI0 */ + {.devfn = DEVFN(0x14, 0), .ir = 11}, /* AHCI1 */ + {.devfn = DEVFN(0x15, 0), .ir = 9}, /* USB */ + {.devfn = DEVFN(0x16, 0), .ir = 1}, /* Virtual RP to LAN0 */ + {.devfn = DEVFN(0x17, 0), .ir = 2}, /* Virtual RP to LAN1 */ + {.devfn = DEVFN(0x18, 0), .ir = 5}, /* ME HECI1 */ + {.devfn = DEVFN(0x18, 1), .ir = 5}, /* ME HECI1 */ + {.devfn = DEVFN(0x18, 2), .ir = 5}, /* ME PTIO-IDER */ + {.devfn = DEVFN(0x18, 3), .ir = 5}, /* ME PTIO-KT */ + {.devfn = DEVFN(0x18, 4), .ir = 5}, /* ME HECI3 */ + {.devfn = DEVFN(0x1a, 0), .ir = 10}, /* HSUART0 */ + {.devfn = DEVFN(0x1a, 1), .ir = 10}, /* HSUART1 */ + {.devfn = DEVFN(0x1a, 2), .ir = 10}, /* HSUART2 */ + {.devfn = DEVFN(0x1b, 0), .ir = 12}, /* IE HECI1 */ + {.devfn = DEVFN(0x1b, 1), .ir = 12}, /* IE HECI1 */ + {.devfn = DEVFN(0x1b, 2), .ir = 12}, /* IE PTIO-IDER */ + {.devfn = DEVFN(0x1b, 3), .ir = 12}, /* IE PTIO-KT */ + {.devfn = DEVFN(0x1b, 4), .ir = 12}, /* IE HECI3 */ + {.devfn = DEVFN(0x1c, 0), .ir = 12}, /* SDHCI */ + {.devfn = DEVFN(0x1f, 0), .ir = 0}, /* LPC */ + {.devfn = DEVFN(0x1f, 1), .ir = 0}, /* PS2B */ + {.devfn = DEVFN(0x1f, 4), .ir = 0}, /* SMBus - Legacy */ + {.devfn = DEVFN(0x1f, 7), .ir = 0}, /* Trace Hub */ +}; + +/* + * Only 6 of the 8 root ports have swizzling, return '1' if this bdf is one of + * them, '0' otherwise + */ +static int is_dnv_swizzled_rp(uint16_t bdf) +{ + switch (bdf) { + case DEVFN(10, 0): + case DEVFN(11, 0): + case DEVFN(12, 0): + case DEVFN(15, 0): + case DEVFN(16, 0): + case DEVFN(17, 0): + return 1; + } + + return 0; +} + +/* + * Figure out which upstream interrupt pin a downstream device gets swizzled to + * + * config - pointer to chip_info containing routing info + * devfn - device/function of root port to check swizzling for + * pin - interrupt pin 1-4 = A-D + * + * Return new pin mapping, 0 if invalid pin + */ +static int dnv_get_swizzled_pin(config_t *config, u8 devfn, u8 pin) +{ + if (pin < 1 || pin > 4) + return 0; + + devfn >>= 3; + if (devfn < 13) + devfn -= 9; + else + devfn -= 14; + + return ((pin - 1 + devfn) % 4) + 1; +} + +/* + * Figure out which upstream interrupt pin a downstream device gets swizzled to + * + * config - pointer to chip_info containing routing info + * devfn - device/function of root port to check swizzling for + * pin - interrupt pin 1-4 = A-D + * + * Return new pin mapping, 0 if invalid pin + */ +static int dnv_get_ir(config_t *config, u8 devfn, u8 pin) +{ + int i = 0; + int line = 0xff; + u16 ir = 0xffff; + + /* The only valid pin values are 1-4 for A-D */ + if (pin < 1 || pin > 4) { + printk(BIOS_WARNING, "%s: pin %d is invalid\n", __func__, pin); + goto dnv_get_ir_done; + } + + for (i = 0; i < ARRAY_SIZE(dnv_ir_lut); i++) { + if (dnv_ir_lut[i].devfn == devfn) + break; + } + + if (i == ARRAY_SIZE(dnv_ir_lut)) { + printk(BIOS_WARNING, "%s: no entry\n", __func__); + goto dnv_get_ir_done; + } + + switch (dnv_ir_lut[i].ir) { + case 0: + ir = config->ir00_routing; + break; + case 1: + ir = config->ir01_routing; + break; + case 2: + ir = config->ir02_routing; + break; + case 3: + ir = config->ir03_routing; + break; + case 4: + ir = config->ir04_routing; + break; + case 5: + ir = config->ir05_routing; + break; + case 6: + ir = config->ir06_routing; + break; + case 7: + ir = config->ir07_routing; + break; + case 8: + ir = config->ir08_routing; + break; + case 9: + ir = config->ir09_routing; + break; + case 10: + ir = config->ir10_routing; + break; + case 11: + ir = config->ir11_routing; + break; + case 12: + ir = config->ir12_routing; + break; + default: + printk(BIOS_ERR, "%s: invalid ir %d for entry %d\n", __func__, dnv_ir_lut[i].ir, + i); + goto dnv_get_ir_done; + } + + ir >>= (pin - 1) * 4; + ir &= 0xf; + switch (ir) { + case 0: + line = config->pirqa_routing; + break; + case 1: + line = config->pirqb_routing; + break; + case 2: + line = config->pirqc_routing; + break; + case 3: + line = config->pirqd_routing; + break; + case 4: + line = config->pirqe_routing; + break; + case 5: + line = config->pirqf_routing; + break; + case 6: + line = config->pirqg_routing; + break; + case 7: + line = config->pirqh_routing; + break; + default: + printk(BIOS_ERR, "%s: invalid ir pirq %d for entry %d\n", __func__, ir, i); + break; + } + +dnv_get_ir_done: + return line; +} + +/* + * PCI devices have the INT_LINE (0x3C) and INT_PIN (0x3D) registers which + * report interrupt routing information to operating systems and drivers. The + * INT_PIN register is generally read only and reports which interrupt pin + * A - D it uses. The INT_LINE register is configurable and reports which IRQ + * (generally the PIC IRQs 1 - 15) it will use. This needs to take interrupt + * pin swizzling on devices that are downstream on a PCI bridge into account. + */ +static u8 dnv_get_int_line(struct device *irq_dev) +{ + config_t *config; + struct device *targ_dev = NULL; + uint16_t parent_bdf = 0; + int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0; + uint8_t int_line = 0xff; + + if (irq_dev->path.type != DEVICE_PATH_PCI || !irq_dev->enabled) { + printk(BIOS_ERR, "%s for non pci device?\n", __func__); + goto dnv_get_int_line_done; + } + + /* + * Get the INT_PIN swizzled up to the root port if necessary + * using the existing coreboot pci_device code + */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + goto dnv_get_int_line_done; + + printk(BIOS_DEBUG, "%s: irq_dev %s, targ_dev %s:\n", __func__, dev_path(irq_dev), + dev_path(targ_dev)); + printk(BIOS_DEBUG, "%s: std swizzle %s from %c to %c\n", __func__, dev_path(targ_dev), + '@' + original_int_pin, '@' + new_int_pin); + + /* Swizzle this device if needed */ + config = targ_dev->chip_info; + parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8; + if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) { + swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin); + printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__, + dev_path(targ_dev), '@' + new_int_pin, '@' + swiz_int_pin); + } else { + swiz_int_pin = new_int_pin; + } + + /* Look up the routing for the pin */ + int_line = dnv_get_ir(config, parent_bdf, swiz_int_pin); + +dnv_get_int_line_done: + printk(BIOS_DEBUG, "\tINT_LINE\t\t: %d\n", int_line); + return int_line; +} + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -150,6 +405,7 @@ config->ipc3); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + int devfn = irq_dev->path.pci.devfn; u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) @@ -157,23 +413,9 @@ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; - case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; - case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; - case 4: /* INTD# */ - int_line = config->pirqd_routing; - break; - } - - if (!int_line) - continue; + int_line = dnv_get_int_line(irq_dev); + printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__, + irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434 Gerrit-Change-Number: 34714 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Add ACPI _PRT methods for virtual root ports
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34713 ) Change subject: soc/intel/dnv: Add ACPI _PRT methods for virtual root ports ...................................................................... soc/intel/dnv: Add ACPI _PRT methods for virtual root ports This eliminates Linux kernel warnings that look like: pcieport 0000:00:17.0: can't derive routing for PCI INT B ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10 Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/acpi/pcie.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/34713/1 diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index f212557..14c55d8 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -168,4 +168,9 @@ // Virtual root port 2 Device (VRP2) { Name (_ADR, 0x00060000) + + Method (_PRT) + { + Return (IRQM (6)) + } } diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index c9bbd3f..bc47b77 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -118,7 +118,52 @@ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 } }) + /* Interrupt Map INTA->INTC, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQIA, Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQIP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQJA, Package() { + Package() { 0x0000ffff, 0, 0, 23 }, + Package() { 0x0000ffff, 1, 0, 20 }, + Package() { 0x0000ffff, 2, 0, 21 }, + Package() { 0x0000ffff, 3, 0, 22 } }) + Name (IQJP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTB, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQKA, Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQKP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + Switch (ToInteger (Arg0)) { + /* Virtual Root Port 2 - QAT */ + Case (Package() { 6 }) { + If (PICM) { + Return (IQIA) + } Else { + Return (IQIP) + } + } + /* PCIe Root Port 1 */ Case (Package() { 9 }) { If (PICM) { @@ -191,6 +236,24 @@ } } + /* Virtual Root Port 0 - LAN 0 */ + Case (Package() { 22 }) { + If (PICM) { + Return (IQJA) + } Else { + Return (IQJP) + } + } + + /* Virtual Root Port 1 - LAN 1 */ + Case (Package() { 23 }) { + If (PICM) { + Return (IQKA) + } Else { + Return (IQKP) + } + } + Default { If (PICM) { Return (IQDA) diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index bcc8a5c..674f043 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -62,11 +62,21 @@ // Virtual root port 0 Device (VRP0) { Name (_ADR, 0x00160000) + + Method (_PRT) + { + Return (IRQM (22)) + } } // Virtual root port 1 Device (VRP1) { Name (_ADR, 0x00170000) + + Method (_PRT) + { + Return (IRQM (23)) + } } // ME HECI -- To view, visit https://review.coreboot.org/c/coreboot/+/34713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d Gerrit-Change-Number: 34713 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34712 ) Change subject: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing ...................................................................... soc/intel/dnv: Fix ACPI reporting of root port interrupt routing pcie_port.asl defines an IRQM method that looks up legacy interrupt swizzling based on incoming interrupt "pin" A-D and root port number. Unfortunately the 8-bit root port number stored at offset 0x4F in the config space matches the device number, not the 1-8 scheme used in the LUT reported to the OS. Fix the case values to match the hardware. Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/acpi/pcie.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/34712/1 diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index cb14cf8..c9bbd3f 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -120,7 +120,7 @@ Switch (ToInteger (Arg0)) { /* PCIe Root Port 1 */ - Case (Package() { 1 }) { + Case (Package() { 9 }) { If (PICM) { Return (IQAA) } Else { @@ -129,7 +129,7 @@ } /* PCIe Root Port 2 */ - Case (Package() { 2 }) { + Case (Package() { 10 }) { If (PICM) { Return (IQBA) } Else { @@ -138,7 +138,7 @@ } /* PCIe Root Port 3 */ - Case (Package() { 3 }) { + Case (Package() { 11 }) { If (PICM) { Return (IQCA) } Else { @@ -147,7 +147,7 @@ } /* PCIe Root Port 4 */ - Case (Package() { 4 }) { + Case (Package() { 12 }) { If (PICM) { Return (IQDA) } Else { @@ -156,7 +156,7 @@ } /* PCIe Root Port 5 */ - Case (Package() { 5 }) { + Case (Package() { 14 }) { If (PICM) { Return (IQEA) } Else { @@ -165,7 +165,7 @@ } /* PCIe Root Port 6 */ - Case (Package() { 6 }) { + Case (Package() { 15 }) { If (PICM) { Return (IQFA) } Else { @@ -174,7 +174,7 @@ } /* PCIe Root Port 7 */ - Case (Package() { 7 }) { + Case (Package() { 16 }) { If (PICM) { Return (IQGA) } Else { @@ -183,7 +183,7 @@ } /* PCIe Root Port 8 */ - Case (Package() { 8 }) { + Case (Package() { 17 }) { If (PICM) { Return (IQHA) } Else { -- To view, visit https://review.coreboot.org/c/coreboot/+/34712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Gerrit-Change-Number: 34712 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34663 ) Change subject: soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode ...................................................................... soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode SATA Mode Select is bit 16 of the SATA General Configuration register. This code currently incorrectly pokes at the Port Clock Disable bits in the Port Mapping Register, and without clock the affected ports can't link. Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/sata.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34663/1 diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ddb8b02..610a4c6 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -31,7 +31,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u32 abar; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -46,10 +45,9 @@ printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set the controller mode */ - reg16 = pci_read_config16(dev, SATA_MAP); - reg16 &= ~(3 << 6); - reg16 |= SATA_MAP_AHCI; - pci_write_config16(dev, SATA_MAP, reg16); + reg32 = pci_read_config16(dev, SATAGC); + reg32 &= ~SATAGC_AHCI; + pci_write_config16(dev, SATAGC, reg32); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); -- To view, visit https://review.coreboot.org/c/coreboot/+/34663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Gerrit-Change-Number: 34663 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Update codenames
by Swift Geek (Sebastian Grzywna) (Code Review) 10 Mar '20

10 Mar '20

Swift Geek (Sebastian Grzywna) has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34352 ) Change subject: Documentation: Update codenames ...................................................................... Documentation: Update codenames austin-3 was a devel board, retracting t60 comes in variants with discrete gpu and only intel gpu one Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek(a)gmail.com> --- M Documentation/mainboard/lenovo/codenames.csv 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34352/1 diff --git a/Documentation/mainboard/lenovo/codenames.csv b/Documentation/mainboard/lenovo/codenames.csv index ad77059..655ff7b 100644 --- a/Documentation/mainboard/lenovo/codenames.csv +++ b/Documentation/mainboard/lenovo/codenames.csv @@ -1,4 +1,6 @@ -t60,magi-5|magi-7|austin-3 +t60,magi (dGPU) | lisa (iGPU) +z61m,BW2 +z61t,BV2 t400,malibu-3 t400s,shinai t410,nozomi-1 @@ -16,13 +18,18 @@ w520,kendo-3 workstation w530,kendo-4 workstation w700,n-note +w701,n-note 3.0 (nico-3) x1_carbon_gen1,genesis-1 x60,ks note x61,ks note-3 x200,mocha-1 +x200s,pecan-1 +x200t,caramel-1 x201,mocha-3 x220,dasher-1 +x220t,comet-1 x230,dasher-2 +x230t,comet-2 x230s,rogue-1 x240,rogue-2 x300,kodachi -- To view, visit https://review.coreboot.org/c/coreboot/+/34352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d Gerrit-Change-Number: 34352 Gerrit-PatchSet: 1 Gerrit-Owner: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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