coreboot-gerrit August 2019

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Change in coreboot[master]: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME
by Frans Hendriks (Code Review) 15 Nov '19

15 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34442 ) Change subject: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME ...................................................................... 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME Upgrade to blobs version with descriptor and Intel ME binary BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34442/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index d7600dd..c7dc4f2 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc +Subproject commit c7dc4f25229fd3c022afdb410264b02f292ddca6 -- To view, visit https://review.coreboot.org/c/coreboot/+/34442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Gerrit-Change-Number: 34442 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489 Change subject: [WIP] soc/amd/common: Use static allocation for params ...................................................................... [WIP] soc/amd/common: Use static allocation for params Lifetime of the structure is the duration of call to AGESA. There is no need to allocate and release these from AGESA's internal heap for every single call. Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 821535d..e769a45 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -410,6 +410,26 @@ } +union AMD_MAX_ALLOC_PARAMS { + AMD_INTERFACE_PARAMS p1; + AMD_RESET_PARAMS p2; + AMD_EARLY_PARAMS p3; + AMD_POST_PARAMS p4; + AMD_RESUME_PARAMS p5; + AMD_ENV_PARAMS p6; + AMD_MID_PARAMS p7; + AMD_LATE_PARAMS p8; +#if 1 + AMD_RTB_PARAMS p9; +#else + AMD_S3SAVE_PARAMS p10; +#endif + AMD_S3LATE_PARAMS p11; + AMD_S3FINAL_PARAMS p12; +}; + +static union AMD_MAX_ALLOC_PARAMS sp; + AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) { AGESA_STATUS status = AGESA_UNSUPPORTED; @@ -417,19 +437,9 @@ AMD_CONFIG_PARAMS *StdHeader = &template; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; - union { - AMD_RESET_PARAMS ResetParams; - AMD_S3LATE_PARAMS S3LateParams; - AMD_S3FINAL_PARAMS S3FinalParams; - } sp; - if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || - (func == AMD_S3FINAL_RESTORE)) { - memset(&sp, 0, sizeof(sp)); - amd_create_struct(aip, func, &sp, sizeof(sp)); - } else { - amd_create_struct(aip, func, NULL, 0); - } + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); StdHeader = aip->NewStructPtr; StdHeader->Func = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/31489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Gerrit-Change-Number: 31489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: cpu/x86: Move some PARALLEL_MP prototypes
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34152 ) Change subject: cpu/x86: Move some PARALLEL_MP prototypes ...................................................................... cpu/x86: Move some PARALLEL_MP prototypes The implementations live inside platform directories, but the function signatures must match those defined by PARALLEL_MP implementation. Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/smm/gen1/smi.h M src/include/cpu/x86/mp.h M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/skylake/include/soc/smm.h 8 files changed, 7 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34152/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cd8d5cb..2c52caf 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -160,13 +160,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Determine if HyperThreading is disabled. The variable is not valid until diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 3d5149a..4c80230 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -24,11 +24,4 @@ bool cpu_has_alternative_smrr(void); /* parallel MP helper functions */ -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); void southbridge_smm_clear_state(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_relocate(void); -void smm_lock(void); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index c04252e..05f2471 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -154,4 +154,11 @@ /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +/* Parallel MP helper functions. */ +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_initialize(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); +void smm_relocate(void); +void smm_lock(void); + #endif /* _X86_MP_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index d3e1cdd..fe38dc9 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -53,13 +53,6 @@ return CONFIG_SMM_TSEG_SIZE; } -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f..5cf7407 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,12 +50,5 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 72aa7fa..a3400ff 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -54,13 +54,6 @@ return CONFIG_SMM_TSEG_SIZE; } -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593..9777599 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,12 +49,5 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e976..4dfa627 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,12 +48,5 @@ int smm_save_state_in_msrs; }; -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2 Gerrit-Change-Number: 34152 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: device/hypertransport: Drop dev_find_slot() debugging
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704 Change subject: device/hypertransport: Drop dev_find_slot() debugging ...................................................................... device/hypertransport: Drop dev_find_slot() debugging Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device.c M src/device/device_const.c M src/include/device/device.h 3 files changed, 5 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1 diff --git a/src/device/device.c b/src/device/device.c index 20a4077..7836af1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,7 +1253,4 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); - - if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index 480ac76..cdae33d 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -177,15 +177,6 @@ * Work around the devicetree topology being manipulated on-the-fly * on systems with HyperTransport Support. */ - -static int ht_tree_needs_fixing, ht_tree_fixup_failed; - -void ht_report_devtree_sanity(void) -{ - printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", - ht_tree_needs_fixing, ht_tree_fixup_failed); -} - static const struct bus *ht_bus_reloc(const struct bus *parent, pci_devfn_t devfn) { @@ -222,34 +213,20 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { - DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; + const struct bus *root; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - dev = pcidev_path_behind(pci_domain->link_list, devfn); + root = pci_domain->link_list; /* Static devicetree with HyperTransport has whacky topology. */ - if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - return dev; + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + root = ht_bus_reloc(root, devfn); - DEVTREE_CONST struct device *dev_fixup, *dev_old_method; - - const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); - dev_fixup = pcidev_path_behind(root, devfn); - dev_old_method = dev_find_slot(0, devfn); - - if (ENV_RAMSTAGE) { - if (dev != dev_old_method) - ht_tree_needs_fixing++; - - if (dev_fixup != dev_old_method) - ht_tree_fixup_failed++; - } - - return dev_old_method; + return pcidev_path_behind(root, devfn); } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/include/device/device.h b/src/include/device/device.h index 40a0f58..540b7e3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,7 +227,6 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); -void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Gerrit-Change-Number: 30704 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: device/hypertransport: Fix regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30703 Change subject: device/hypertransport: Fix regression on dev_find_slot() removal ...................................................................... device/hypertransport: Fix regression on dev_find_slot() removal The regression is with the implementation of the functions introduced in commit ad7674e device: Introduce pcidev_on_root() and friends For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy, and the topology (bus->children and dev->sibling links) are being manipulated during HyperTransport enumeration. This workaround reverts to old method of using dev_find_slot() while keeping track of whether the new method would give equivalent result. Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/device/device.c M src/device/device_const.c M src/device/hypertransport.c M src/include/device/device.h M src/include/device/pci.h 6 files changed, 87 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30703/1 diff --git a/Makefile.inc b/Makefile.inc index 2741b19..24b5164 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,7 +577,10 @@ verstage-y+=$(DEVICETREE_STATIC_C) bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) + +ifneq ($(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT),y) smm-y+=$(DEVICETREE_STATIC_C) +endif ####################################################################### # Clean up rules diff --git a/src/device/device.c b/src/device/device.c index 7836af1..20a4077 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,4 +1253,7 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); + + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index ec128e8..480ac76 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -173,6 +173,43 @@ return child; } +/*** + * Work around the devicetree topology being manipulated on-the-fly + * on systems with HyperTransport Support. + */ + +static int ht_tree_needs_fixing, ht_tree_fixup_failed; + +void ht_report_devtree_sanity(void) +{ + printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", + ht_tree_needs_fixing, ht_tree_fixup_failed); +} + +static const struct bus *ht_bus_reloc(const struct bus *parent, + pci_devfn_t devfn) +{ + DEVTREE_CONST struct device *dev; + DEVTREE_CONST struct bus *bus; + + /* HyperTransport enumeration fixes up the whacky + * topology present in static devicetree. + */ + if (ENV_RAMSTAGE && (SCAN_COMPLETE == ht_scanning_status())) + return parent; + + if (devfn >= PCI_DEVFN(0x18, 0)) + return parent; + + /* One of the links is bus for devices 0:00.x to 0:17.x. */ + dev = pcidev_path_behind(parent, PCI_DEVFN(0x18, 0)); + for (bus = dev->link_list; bus; bus = bus->next) + if (bus->children) + return bus; + + return NULL; +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -185,12 +222,34 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { + DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - return pcidev_path_behind(pci_domain->link_list, devfn); + + dev = pcidev_path_behind(pci_domain->link_list, devfn); + + /* Static devicetree with HyperTransport has whacky topology. */ + if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + return dev; + + DEVTREE_CONST struct device *dev_fixup, *dev_old_method; + + const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); + dev_fixup = pcidev_path_behind(root, devfn); + dev_old_method = dev_find_slot(0, devfn); + + if (ENV_RAMSTAGE) { + if (dev != dev_old_method) + ht_tree_needs_fixing++; + + if (dev_fixup != dev_old_method) + ht_tree_fixup_failed++; + } + + return dev_old_method; } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index ed6b2dd..fd4961e 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -244,6 +244,13 @@ } } +static int ht_scan_chain_process = SCAN_NOT_STARTED; + +int ht_scanning_status(void) +{ + return ht_scan_chain_process; +} + static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unitid_base, @@ -276,6 +283,9 @@ /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_IN_PROGRESS; + /* See which static device nodes I have. */ old_devices = bus->children; bus->children = 0; @@ -472,6 +482,9 @@ last_func->sibling = old_devices; } + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_COMPLETE; + return next_unitid; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 540b7e3..40a0f58 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,6 +227,7 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 7cf7e06..41ad281 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -122,6 +122,13 @@ int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); struct msix_entry *pci_msix_get_table(struct device *dev); +enum { + SCAN_NOT_STARTED = 0, + SCAN_IN_PROGRESS, + SCAN_COMPLETE +}; +int ht_scanning_status(void); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -- To view, visit https://review.coreboot.org/c/coreboot/+/30703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Gerrit-Change-Number: 30703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: ec/google/chromeec: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 14 Nov '19

14 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32142 Change subject: ec/google/chromeec: Remove redundant use of ACPI offset operator ...................................................................... ec/google/chromeec: Remove redundant use of ACPI offset operator Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32142/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 962988e..b6c2231 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -41,7 +41,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte @@ -54,7 +53,6 @@ TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number // DFUD must be 0 for the other 31 values to be valid - Offset (0x0a), DFUD, 1, // Device Features Undefined FLSH, 1, // Flash commands present PFAN, 1, // PWM Fan control present @@ -88,7 +86,6 @@ RWSG, 1, // EC has RWSIG task enabled DEVE, 1, // EC supports device events // make sure we're within our space envelope - Offset (0x0e), Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 982ec5b..77b4708 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -17,7 +17,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */ -Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8 Gerrit-Change-Number: 32142 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 14 Nov '19

14 Nov '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35119 ) Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: I18948d31c0bf0bf9d641480a35fc710b9ee8ae84 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/mainboard/sifive/hifive-unleashed/Kconfig M src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/include/soc/memlayout.ld 3 files changed, 98 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35119/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 2453178..fc9bc1e 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -19,6 +19,7 @@ select BOARD_ROMSIZE_KB_32768 select MISSING_BOARD_RESET select FLATTENED_DEVICE_TREE + select SPI_SDCARD config HEAP_SIZE default 0x10000 diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index b0198a7..29cca08 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -15,15 +15,91 @@ */ #include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/mmio.h> +#include <soc/addressmap.h> #include <soc/spi.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> +#include <spi_sdcard.h> + +static struct spi_sdcard card; /* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = +static struct mem_region_device spi_mdev = MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + size_t start_block_address = offset / 512; + size_t end_block_address = (offset + count - 1) / 512; + size_t has_begin = !!(offset % 512); + size_t has_end = !!((offset + count) % 512); + + if (start_block_address == end_block_address) { + uint8_t tmp[512]; + size_t o = offset % 512; + size_t l = count; + spi_sdcard_single_read(&card, start_block_address, tmp); + memcpy(dest, tmp + o, l); + return count; + } + + if (has_begin) { + uint8_t tmp[512]; + size_t o = offset % 512; + size_t l = 512 - o; + spi_sdcard_single_read(&card, start_block_address, tmp); + memcpy(dest, tmp + o, l); + } + + if (start_block_address + has_begin <= end_block_address - has_end) { + size_t start_lba = start_block_address + has_begin; + size_t end_lba = end_block_address - has_end; + size_t o = has_begin ? 512 - offset % 512 : 0; + if (start_lba < end_lba) + spi_sdcard_multiple_read(&card, + start_lba, end_lba, dest + o); + else + spi_sdcard_single_read(&card, start_lba, dest + o); + } + + if (has_end) { + uint8_t tmp[512]; + size_t o = 0; + size_t l = (offset + count) % 512; + spi_sdcard_single_read(&card, end_block_address, tmp); + memcpy(dest + count - l, tmp + o, l); + } + + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + const struct region_device *boot_device_ro(void) { - return &mdev.rdev; + + switch (read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; } const static struct fu540_spi_mmap_config spi_mmap_config = { @@ -40,10 +116,22 @@ void boot_device_init(void) { struct spi_slave slave; + switch (read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + /* initialize spi controller */ + spi_setup_slave(0, 0, &slave); - /* initialize spi controller */ - spi_setup_slave(0, 0, &slave); - - /* map flash to memory space */ - fu540_spi_mmap(&slave, &spi_mmap_config); + /* map flash to memory space */ + fu540_spi_mmap(&slave, &spi_mmap_config); + break; + case 11: + spi_sdcard_init(&card, 2, 0); + mmap_helper_device_init(&sd_mdev, + _cbfs_cache, REGION_SIZE(cbfs_cache)); + break; + default: + die("Wrong configuration of MSEL"); + } } diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/35119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18948d31c0bf0bf9d641480a35fc710b9ee8ae84 Gerrit-Change-Number: 35119 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

6 35

Change in coreboot[master]: drivers/spi: add drivers for sdcard mounted on the spi bus
by Xiang Wang (Code Review) 14 Nov '19

14 Nov '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35118 ) Change subject: drivers/spi: add drivers for sdcard mounted on the spi bus ...................................................................... drivers/spi: add drivers for sdcard mounted on the spi bus Currently supports initialization, read, write, and erase operations. Tested on HiFive Uneashed Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.inc A src/drivers/spi/spi_sdcard.c A src/include/spi_sdcard.h 4 files changed, 768 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35118/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b15a502..dab6d0e 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -30,6 +30,13 @@ Select this option if your chipset driver needs to store certain data in the SPI flash. +config SPI_SDCARD + bool + default n + help + Select this option if your chipset driver needs to store certain + data in the SPI sdcard. + if SPI_FLASH # Keep at 0 because lots of boards assume this default. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index e55233e..6dbc43a 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -15,6 +15,7 @@ $(1)-y += bitbang.c $(1)-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c $(1)-$(CONFIG_SPI_FLASH) += spi_flash.c +$(1)-$(CONFIG_SPI_SDCARD) += spi_sdcard.c $(1)-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP$(2)) += boot_device_rw_nommap.c $(1)-$(CONFIG_CONSOLE_SPI_FLASH) += flashconsole.c $(1)-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c new file mode 100644 index 0000000..7fc6afd --- /dev/null +++ b/src/drivers/spi/spi_sdcard.c @@ -0,0 +1,706 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <spi-generic.h> +#include <spi_sdcard.h> +#include <commonlib/helpers.h> +#include <console/console.h> + +//#define SPI_SDCARD_DEBUG + +#ifdef SPI_SDCARD_DEBUG +#define dprintk(fmt, args...) \ + printk(BIOS_DEBUG, fmt, ##args) +#else +#define dprintk(fmt, args...) \ + do {} while (0) +#endif + +#define SDCARD_TYPE_SDSC 1 +#define SDCARD_TYPE_SDHC 2 +#define SDCARD_TYPE_SDXC 3 + +/* CMD */ +#define GO_IDLE_STATE 0 +#define SEND_OP_COND 1 +#define SWITCH_FUNC 6 +#define SEND_IF_COND 8 +#define SEND_CSD 9 +#define SEND_CID 10 +#define STOP_TRANSMISSION 12 +#define SEND_STATUS 13 +#define SET_BLOCKLEN 16 +#define READ_SINGLE_BLOCK 17 +#define READ_MULTIPLEBLOCK 18 +#define WRITE_BLOCK 24 +#define WRITE_MULTIPLEBLOCK 25 +#define PROGRAM_CSD 27 +#define SET_WRITE_PROT 28 +#define CLR_WRITE_PROT 29 +#define SEND_WRITE_PROT 30 +#define ERASE_WR_BLK_START_ADDR 32 +#define ERASE_WR_BLK_END_ADDR 33 +#define ERASE 38 +#define LOCK_UNLOCK 42 +#define APP_CMD 55 +#define GEN_CMD 56 +#define READ_OCR 58 +#define CRC_ON_OFF 59 + +/* ACMD */ +#define SD_STATUS 13 +#define SEND_NUM_WR_BLOCKS 22 +#define SET_WR_BLK_ERASE_COUNT 23 +#define SD_SEND_OP_COND 41 +#define SET_CLR_CARD_DETECT 42 +#define SEND_SCR 51 + +/* control tokens */ +#define CT_BLOCK_START 0xFE +#define CT_MULTIPLE_BLOCK_START 0xFC +#define CT_MULTIPLE_BLOCK_STOP 0xFD +#define CT_RESPONSE_MASK 0x1F +#define CT_RESPONSE_ACCEPTED 0x05 +#define CT_RESPONSE_REJECTED_CRC 0x0B +#define CT_RESPONSE_REJECTED_WRITE_ERR 0x0D + +/* response type */ +#define RSP_R1 0 +#define RSP_R1b 1 +#define RSP_R2 2 +#define RSP_R3 3 +#define RSP_R4 4 +#define RSP_R5 5 +#define RSP_R7 7 + +#define RSP_ERR_CARD_IS_LOCKED (1 << 0) +#define RSP_ERR_WP_ERASE_SKIP (1 << 1) +#define RSP_ERR_GENERAL (1 << 2) +#define RSP_ERR_CC (1 << 3) +#define RSP_ERR_ECC (1 << 4) +#define RSP_ERR_WP_VIOLATION (1 << 5) +#define RSP_ERR_ERASE_PARAM (1 << 6) +#define RSP_ERR_OUT_OF_RANGE (1 << 7) +#define RSP_ERR_IN_IDLE (1 << 8) +#define RSP_ERR_ERASE_RESET (1 << 9) +#define RSP_ERR_ILLEGAL_COMMAND (1 << 10) +#define RSP_ERR_COM_CRC (1 << 11) +#define RSP_ERR_ERASE_SEQUENCE (1 << 12) +#define RSP_ERR_ADDRESS (1 << 13) +#define RSP_ERR_PARAMETER (1 << 14) + +static const uint8_t crc7_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, + 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, + 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, + 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, + 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, + 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, + 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, + 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, + 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, + 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, + 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, + 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, + 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, + 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, + 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, + 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, + 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, + 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, + 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79 +}; + +static uint8_t crc7_byte(uint8_t crc, uint8_t data) +{ + return crc7_table[(crc << 1) ^ data]; +} + +static const uint16_t crc16_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, +}; + +static uint16_t crc16_byte(uint16_t prev, uint8_t in) +{ + return crc16_tab[((prev >> 8) ^ in) & 0xff] ^ (prev << 8); +} + +static unsigned long long extract_bits(uint8_t *buff, + int width, int start, int end) +{ + unsigned long long r = 0; + for (int i = end; i >= start; i--) { + int bitpos = width - i - 1; + int b = bitpos / 8; + int shift = 7 - bitpos % 8; + r = (r << 1) | ((buff[b] >> shift) & 1); + } + return r; +} + +static void spi_sdcard_sendbyte(const struct spi_sdcard *card, uint8_t b) +{ + dprintk("sdcard -> %#x\n", b); + spi_xfer(&card->slave, &b, 1, NULL, 0); +} + +static uint8_t spi_sdcard_recvbyte(const struct spi_sdcard *card) +{ + uint8_t b, t = 0xff; + spi_xfer(&card->slave, &t, 1, &b, 1); + dprintk("sdcard <- %#x\n", b); + return b; +} + +static uint8_t spi_sdcard_calculate_command_crc(uint8_t cmd, uint32_t argument) +{ + uint8_t crc = 0; + crc = crc7_byte(crc, (cmd | 0x40) & 0x7f); + crc = crc7_byte(crc, (argument >> (3 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (2 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (1 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (0 * 8)) & 0xff); + return (crc << 1) | 1; +} + +static int lookup_cmd_response_type(uint8_t cmd) +{ + switch (cmd) { + case 0: + case 1: + case 6: + case 9: + case 10: + case 16: + case 17: + case 18: + case 24: + case 25: + case 27: + case 30: + case 32: + case 33: + case 42: + case 55: + case 56: + case 59: + return RSP_R1; + case 12: + case 28: + case 29: + case 38: + return RSP_R1b; + case 13: + return RSP_R2; + case 58: + return RSP_R3; + case 8: + return RSP_R7; + } + return -1; +} + +static int lookup_acmd_response_type(uint8_t cmd) +{ + switch (cmd) { + case 22: + case 23: + case 41: + case 42: + case 51: + return RSP_R1; + case 13: + return RSP_R2; + } + return -1; +} + +static int lookup_response_length(int response_type) +{ + switch (response_type) { + case RSP_R1: + case RSP_R1b: + return 1; + case RSP_R2: + return 2; + case RSP_R3: + case RSP_R7: + return 5; + } + return -1; +} + +static int response_resolve(int response_type, uint8_t *response, + uint32_t *out_register) +{ + __unused static const char * const sd_err[] = { + "Card is locked", + "wp erase skip | lock/unlok cmd failed", + "error", + "CC error", + "card err failed", + "wp violation", + "erase param", + "out of range | csd overwrite", + "in idle state", + "erase reset", + "illegal command", + "com crc error", + "erase sequence error", + "address error", + "parameter error" + }; + uint8_t r1 = 0, r2 = 0; + + if ((response_type == RSP_R1) + || (response_type == RSP_R1b) + || (response_type == RSP_R2) + || (response_type == RSP_R3) + || (response_type == RSP_R7)) + r1 = response[0]; + + if (response_type == RSP_R2) + r2 = response[1]; + + if (((response_type == RSP_R3) || (response_type == RSP_R7)) + && (out_register != NULL)) { + *out_register = 0; + *out_register = (*out_register << 8) | response[1]; + *out_register = (*out_register << 8) | response[2]; + *out_register = (*out_register << 8) | response[3]; + *out_register = (*out_register << 8) | response[4]; + } + + if (r1 != 0 || r2 != 0) { + int i = 0; + uint16_t r = (r1 << 8) | r2; + while (r) { + if (r & 1) + dprintk("SDCARD ERROR: %s\n", sd_err[i]); + r = r >> 1; + i++; + } + return (r1 << 8) | r2; + } + + return 0; +} + +static int spi_sdcard_do_command_help(const struct spi_sdcard *card, + int is_acmd, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + int ret, type, length; + uint8_t crc, c, response[5]; + + /* calculate crc for command */ + crc = spi_sdcard_calculate_command_crc(cmd, argument); + + if (is_acmd) + dprintk("\nsdcard execute acmd%d, argument = %#x, crc = %#x\n", + cmd, argument, crc); + else + dprintk("\nsdcard execute cmd%d, argument = %#x, crc = %#x\n", + cmd, argument, crc); + + /* lookup response type of command */ + type = lookup_cmd_response_type(cmd); + if (is_acmd) + type = lookup_acmd_response_type(cmd); + + /* lookup response length of command */ + length = lookup_response_length(type); + + /* enable CS to communicate */ + spi_claim_bus(&card->slave); + + spi_sdcard_recvbyte(card); + + /* send command */ + spi_sdcard_sendbyte(card, (cmd | 0x40) & 0x7f); + /* send argument */ + spi_sdcard_sendbyte(card, (argument >> (8 * 3)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 2)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 1)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 0)) & 0xff); + /* send crc */ + spi_sdcard_sendbyte(card, crc); + + /* waitting for response */ + while ((c = spi_sdcard_recvbyte(card)) & 0x80) + ; + + /* obtain response */ + response[0] = c; + for (int i = 1; i < length; i++) + response[i] = spi_sdcard_recvbyte(card); + + if (type == RSP_R1b) + while (spi_sdcard_recvbyte(card) != 0xff) + ;/* waitting done */ + + + ret = response_resolve(type, response, out_register); + if (ret) + /* disable CS if the command fail to execute */ + spi_release_bus(&card->slave); + + return ret; +} + +static int spi_sdcard_do_command(const struct spi_sdcard *card, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + return spi_sdcard_do_command_help(card, 0, cmd, argument, out_register); +} + +static int spi_sdcard_do_app_command(const struct spi_sdcard *card, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + /* CMD55 */ + spi_sdcard_do_command(card, APP_CMD, 0, NULL); + return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register); +} + + +size_t spi_sdcard_size(const struct spi_sdcard *card) +{ + uint8_t csd[16]; + uint16_t c = 0; + + /* CMD9, send csd (128bits register) */ + if (spi_sdcard_do_command(card, SEND_CSD, 0, NULL)) { + spi_release_bus(&card->slave); + return -1; + } + + while (spi_sdcard_recvbyte(card) != CT_BLOCK_START) + ; + + for (int i = 0; i < 16; i++) { + csd[i] = spi_sdcard_recvbyte(card); + c = crc16_byte(c, csd[i]); + } + + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + + if (extract_bits(csd, 128, 126, 127) == 0) { + /* csd version 1.0 */ + size_t c_size = extract_bits(csd, 128, 62, 73); + size_t mult = extract_bits(csd, 128, 47, 49); + size_t read_bl_len = extract_bits(csd, 128, 80, 83); + return (c_size + 1) * mult * (1 << read_bl_len); + } + + if (extract_bits(csd, 128, 126, 127) == 1) { + /* csd version 2.0 */ + size_t c_size = extract_bits(csd, 128, 48, 69); + return (c_size + 1) * 512 * 1024; + } + + return -1; +} + +int spi_sdcard_init(struct spi_sdcard *card, + unsigned int bus, unsigned int cs) +{ + int resolve; + uint32_t ocr; + + /* initialize spi controller */ + spi_setup_slave(bus, cs, &card->slave); + + spi_release_bus(&card->slave); + for (int i = 0; i < 10; i++) + spi_sdcard_sendbyte(card, 0xff); + + /* CMD0, reset sdcard */ + while (spi_sdcard_do_command(card, GO_IDLE_STATE, 0, NULL) + != RSP_ERR_IN_IDLE) + ; + + /* CMD8 */ + resolve = spi_sdcard_do_command(card, SEND_IF_COND, 0x1aa, NULL); + if (resolve & RSP_ERR_ILLEGAL_COMMAND) + /* ACMD41, initialize card */ + while (spi_sdcard_do_app_command(card, SD_SEND_OP_COND, + 0, NULL)) + ; + else + /* ACMD41, initialize card */ + while (spi_sdcard_do_app_command(card, SD_SEND_OP_COND, + 0x40000000, NULL)) + ; + + /* CMD58, read ocr register */ + if (spi_sdcard_do_command(card, READ_OCR, 0, &ocr)) + return -1; + + /* CMD16, set block length to 512 bytes */ + if (spi_sdcard_do_command(card, SET_BLOCKLEN, 512, NULL)) + return -1; + + /* CCS is bit30 of ocr register + * CCS = 0 -> SDSC + * CCS = 1 -> SDHC/SDXC + * */ + if ((ocr & 0x40000000) == 0) + card->type = SDCARD_TYPE_SDSC; + else { + /* size > 32G -> SDXC */ + if (spi_sdcard_size(card) > 32LL * 1024 * 1024 * 1024) + card->type = SDCARD_TYPE_SDXC; + else + card->type = SDCARD_TYPE_SDHC; + } + + return 0; +} + +int spi_sdcard_single_read(const struct spi_sdcard *card, + size_t block_address, + void *buff) +{ + uint16_t c = 0; + + if (card->type == SDCARD_TYPE_SDSC) + block_address = block_address * 512; + + /* CMD17, start single block read */ + if (spi_sdcard_do_command(card, READ_SINGLE_BLOCK, block_address, NULL)) + return -1; + + while (spi_sdcard_recvbyte(card) != CT_BLOCK_START) + ; + for (int i = 0; i < 512; i++) { + ((uint8_t *)buff)[i] = spi_sdcard_recvbyte(card); + c = crc16_byte(c, ((uint8_t *)buff)[i]); + } + + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + + return 0; +} + +int spi_sdcard_multiple_read(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff) +{ + int block_num = end_block_address - start_block_address + 1; + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + /* CMD18, start multiple block read */ + if (spi_sdcard_do_command(card, + READ_MULTIPLEBLOCK, start_block_address, NULL)) + return -1; + + for (int i = 0; i < block_num; i++) { + uint16_t c = 0; + while (spi_sdcard_recvbyte(card) != CT_BLOCK_START) + ; + for (int k = 0; k < 512; k++) { + uint8_t tmp = spi_sdcard_recvbyte(card); + ((uint8_t *)buff)[512 * i + k] = tmp; + c = crc16_byte(c, tmp); + } + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + } + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + return -1; + return 0; +} + +int spi_sdcard_single_write(const struct spi_sdcard *card, + size_t block_address, + void *buff) +{ + uint16_t c = 0; + if (card->type == SDCARD_TYPE_SDSC) + block_address = block_address * 512; + + if (spi_sdcard_do_command(card, WRITE_BLOCK, block_address, NULL)) + return -1; + + spi_sdcard_sendbyte(card, CT_BLOCK_START); + for (int i = 0; i < 512; i++) { + spi_sdcard_sendbyte(card, ((uint8_t *)buff)[i]); + c = crc16_byte(c, ((uint8_t *)buff)[i]); + } + spi_sdcard_sendbyte(card, 0xff & (c >> 8)); + spi_sdcard_sendbyte(card, 0xff & (c >> 0)); + + while (((c = spi_sdcard_recvbyte(card)) & 0x11) != 0x01) + ; + if ((c & CT_RESPONSE_MASK) == CT_RESPONSE_ACCEPTED) { + while (spi_sdcard_recvbyte(card) != 0xff) + ;/* wait for complete */ + return 0; + } + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + return -1; + + return -1; +} + +int spi_sdcard_multiple_write(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff) +{ + int ret = 0; + int block_num = end_block_address - start_block_address + 1; + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + + if (spi_sdcard_do_command(card, WRITE_MULTIPLEBLOCK, + start_block_address, NULL)) + return -1; + + for (int i = 0; i < block_num; i++) { + uint16_t c = 0; + spi_sdcard_sendbyte(card, CT_MULTIPLE_BLOCK_START); + for (int k = 0; k < 512; k++) { + spi_sdcard_sendbyte(card, + ((uint8_t *)buff)[512 * i + k]); + c = crc16_byte(c, ((uint8_t *)buff)[512 * i + k]); + } + spi_sdcard_sendbyte(card, 0xff & (c >> 8)); + spi_sdcard_sendbyte(card, 0xff & (c >> 0)); + + while (((c = spi_sdcard_recvbyte(card)) & 0x11) != 0x01) + ; + if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) { + ret = -1; + break; + } + while (spi_sdcard_recvbyte(card) != 0xff) + ;/* wait for complete */ + } + spi_sdcard_sendbyte(card, CT_MULTIPLE_BLOCK_STOP); + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + return -1; + + return ret; +} + +int spi_sdcard_erase(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address) +{ + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + + /* CMD32, set erase start address */ + if (spi_sdcard_do_command(card, ERASE_WR_BLK_START_ADDR, + start_block_address, NULL)) + return -1; + + /* CMD33, set erase end address */ + if (spi_sdcard_do_command(card, ERASE_WR_BLK_END_ADDR, + end_block_address, NULL)) + return -1; + + /* CMD38, erase */ + if (spi_sdcard_do_command(card, ERASE, 0, NULL)) + return -1; + + return 0; +} + +int spi_sdcard_erase_all(const struct spi_sdcard *card) +{ + return spi_sdcard_erase(card, 0, spi_sdcard_size(card) / 512); +} diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h new file mode 100644 index 0000000..40d351d --- /dev/null +++ b/src/include/spi_sdcard.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SPI_SDCARD_H_ +#define _SPI_SDCARD_H_ + +struct spi_sdcard { + int type; + struct spi_slave slave; +}; + +int spi_sdcard_init(struct spi_sdcard *card, + unsigned int bus, + unsigned int cs); + +int spi_sdcard_single_read(const struct spi_sdcard *card, + size_t block_address, + void *buff); + +int spi_sdcard_multiple_read(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff); + +int spi_sdcard_single_write(const struct spi_sdcard *card, + size_t block_address, + void *buff); + +int spi_sdcard_multiple_write(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff); + +int spi_sdcard_erase(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address); + +int spi_sdcard_erase_all(const struct spi_sdcard *card); + +size_t spi_sdcard_size(const struct spi_sdcard *card); + +#endif /* _SPI_SDCARD_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a Gerrit-Change-Number: 35118 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

5 31

Change in ...coreboot[master]: [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 Nov '19

12 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33175 Change subject: [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK VERY WIP and UNTESTED Change-Id: I527b24e2e4bfd56a92ecd1bb1cebfe91f54b7fe0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/x220/Makefile.inc R src/mainboard/lenovo/x220/early_init.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc 15 files changed, 42 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33175/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index dbb8982..34b74b5 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -24,10 +24,6 @@ select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/model_206ax/bootblock.c" - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e1fa879..f0c263b 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -11,6 +11,11 @@ subdirs-y += ../microcode subdirs-y += ../turbo +bootblock-y += ../../x86/early_reset.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += bootblock.c + ramstage-y += acpi.c ramstage-y += common.c @@ -31,7 +36,6 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe37..197e94c 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -15,13 +15,11 @@ #include <stdint.h> #include <arch/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> +#include <cpu/intel/car/bootblock.h> -#include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ @@ -32,35 +30,6 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -111,10 +80,8 @@ halt(); } -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..961aa7f 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +bootblock-y += early_init.c +romstage-y += early_init.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 97% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c index a5b0c81..4e416bd 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -27,8 +27,9 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <bootblock_common.h> -void pch_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ @@ -105,10 +106,6 @@ { } -void mainboard_config_superio(void) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index d5901da..ef87335 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_ACPI select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -68,16 +69,19 @@ int default 512 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/sandybridge/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 help The MRC blob requires it to be at 0xf0000000. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages + if USE_NATIVE_RAMINIT config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ba55466..7e9c351 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,8 @@ ramstage-y += acpi.c +bootblock-y += bootblock.c + romstage-y += ram_calc.c ramstage-y += common.c diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1..b4de3a4 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -12,11 +12,12 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> /* Just re-define this instead of including sandybridge.h. It blows up romcc. */ #define PCIEXBAR 0x60 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 76b3088..114cd6f 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -54,11 +54,11 @@ if (bist == 0) enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ - early_pch_init(); + /* Init GPIO, ... */ + romstage_pch_init(); /* Initialize superio */ - mainboard_config_superio(); +// mainboard_config_superio(); /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..8b9f580 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -54,10 +54,6 @@ int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/bd82x6x/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b6023b0..7af3cec 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,12 +38,16 @@ romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c +bootblock-y += early_pch.c romstage-y += early_pch.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +bootblock-y += early_usb.c romstage-y += early_thermal.c early_me.c early_usb.c else romstage-y += early_me_mrc.c early_usb_mrc.c endif +bootblock-y += bootblock.c + endif diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 0086fe3..1566faa 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <device/pci_ops.h> #include "pch.h" @@ -66,7 +67,7 @@ RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); enable_port80_on_lpc(); @@ -74,4 +75,6 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + bootblock_pch_init(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..0aa78ae 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,13 +258,15 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -void early_pch_init(void) +void bootblock_pch_init(void) { - pch_enable_lpc(); - pch_enable_bars(); pch_generic_setup(); +} +void romstage_pch_init(void) +{ setup_pch_gpios(&mainboard_gpio_map); } + diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 4369b5c..9d9570b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,7 +75,8 @@ void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -void early_pch_init(void); +void bootblock_pch_init(void); +void romstage_pch_init(void); void early_pch_init_native_dmi_pre(void); void early_pch_init_native_dmi_post(void); diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4cf6e6f..6a5e636 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) +bootblock-y += pmbase.c verstage-y += pmbase.c romstage-y += pmbase.c ramstage-y += pmbase.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527b24e2e4bfd56a92ecd1bb1cebfe91f54b7fe0 Gerrit-Change-Number: 33175 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: northbridge/intel/sandybridge: Set up console on bootblock
by Arthur Heymans (Code Review) 12 Nov '19

12 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33187 Change subject: northbridge/intel/sandybridge: Set up console on bootblock ...................................................................... northbridge/intel/sandybridge: Set up console on bootblock The assmption is made that setting up southbridge gpio's is not needed for console in the bootblock. Change-Id: I7b242e7cde0c5799f63331b817d863a0d6c00ab3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/Makefile.inc R src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/asrock/b75pro3-m/Makefile.inc R src/mainboard/asrock/b75pro3-m/early_init.c M src/mainboard/asus/h61m-cs/Makefile.inc R src/mainboard/asus/h61m-cs/early_init.c M src/mainboard/asus/maximus_iv_gene-z/Makefile.inc R src/mainboard/asus/maximus_iv_gene-z/early_init.c M src/mainboard/asus/p8h61-m_lx/Makefile.inc R src/mainboard/asus/p8h61-m_lx/early_init.c M src/mainboard/asus/p8h61-m_pro/Makefile.inc R src/mainboard/asus/p8h61-m_pro/early_init.c M src/mainboard/compulab/intense_pc/Makefile.inc R src/mainboard/compulab/intense_pc/early_init.c M src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc R src/mainboard/gigabyte/ga-b75m-d3h/early_init.c M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc R src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c M src/mainboard/google/butterfly/Makefile.inc R src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/Makefile.inc R src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/Makefile.inc R src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/Makefile.inc R src/mainboard/google/stout/early_init.c M src/mainboard/hp/2570p/Makefile.inc R src/mainboard/hp/2570p/early_init.c M src/mainboard/hp/2760p/Makefile.inc R src/mainboard/hp/2760p/early_init.c M src/mainboard/hp/8460p/Makefile.inc R src/mainboard/hp/8460p/early_init.c M src/mainboard/hp/8470p/Makefile.inc R src/mainboard/hp/8470p/early_init.c M src/mainboard/hp/8770w/Makefile.inc R src/mainboard/hp/8770w/early_init.c M src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc R src/mainboard/hp/compaq_8200_elite_sff/early_init.c M src/mainboard/hp/folio_9470m/Makefile.inc R src/mainboard/hp/folio_9470m/early_init.c M src/mainboard/hp/revolve_810_g1/Makefile.inc R src/mainboard/hp/revolve_810_g1/early_init.c M src/mainboard/intel/dcp847ske/Makefile.inc R src/mainboard/intel/dcp847ske/early_init.c M src/mainboard/intel/emeraldlake2/Makefile.inc R src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/Makefile.inc R src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/l520/Makefile.inc R src/mainboard/lenovo/l520/early_init.c M src/mainboard/lenovo/s230u/Makefile.inc R src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t420/Makefile.inc R src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420s/Makefile.inc R src/mainboard/lenovo/t420s/early_init.c M src/mainboard/lenovo/t430/Makefile.inc R src/mainboard/lenovo/t430/early_init.c M src/mainboard/lenovo/t430s/Makefile.inc R src/mainboard/lenovo/t430s/early_init.c M src/mainboard/lenovo/t520/Makefile.inc R src/mainboard/lenovo/t520/early_init.c M src/mainboard/lenovo/t530/Makefile.inc R src/mainboard/lenovo/t530/early_init.c M src/mainboard/lenovo/x131e/Makefile.inc R src/mainboard/lenovo/x131e/early_init.c M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc R src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/lenovo/x220/Makefile.inc R src/mainboard/lenovo/x220/early_init.c M src/mainboard/lenovo/x230/Makefile.inc R src/mainboard/lenovo/x230/early_init.c M src/mainboard/msi/ms7707/Makefile.inc R src/mainboard/msi/ms7707/early_init.c M src/mainboard/roda/rv11/Makefile.inc R src/mainboard/roda/rv11/early_init.c M src/mainboard/samsung/lumpy/Makefile.inc R src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/Makefile.inc R src/mainboard/samsung/stumpy/early_init.c M src/mainboard/sapphire/pureplatinumh61/Makefile.inc R src/mainboard/sapphire/pureplatinumh61/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 86 files changed, 135 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33187/1 diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index a41ee25..b80d5da 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -6,3 +6,6 @@ spd.bin-type := spd ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/early_init.c similarity index 100% rename from src/mainboard/apple/macbookair4_2/romstage.c rename to src/mainboard/apple/macbookair4_2/early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index 017967b..3ca89fb 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/early_init.c similarity index 100% rename from src/mainboard/asrock/b75pro3-m/romstage.c rename to src/mainboard/asrock/b75pro3-m/early_init.c diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index ebe01ae..261e206 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/early_init.c similarity index 100% rename from src/mainboard/asus/h61m-cs/romstage.c rename to src/mainboard/asus/h61m-cs/early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index f81e828..dd91210 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c similarity index 100% rename from src/mainboard/asus/maximus_iv_gene-z/romstage.c rename to src/mainboard/asus/maximus_iv_gene-z/early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index 7c1bf9e..0ef22db 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/early_init.c similarity index 100% rename from src/mainboard/asus/p8h61-m_lx/romstage.c rename to src/mainboard/asus/p8h61-m_lx/early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/early_init.c similarity index 100% rename from src/mainboard/asus/p8h61-m_pro/romstage.c rename to src/mainboard/asus/p8h61-m_pro/early_init.c diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/early_init.c similarity index 100% rename from src/mainboard/compulab/intense_pc/romstage.c rename to src/mainboard/compulab/intense_pc/early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 07fc277..53aae3d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -20,3 +20,6 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/romstage.c rename to src/mainboard/gigabyte/ga-b75m-d3h/early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c rename to src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 8033e1c..9c6920e 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -22,3 +22,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/early_init.c similarity index 100% rename from src/mainboard/google/butterfly/romstage.c rename to src/mainboard/google/butterfly/early_init.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 89bb365..84e6e5e 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -41,3 +41,6 @@ spd.bin-file := $(SPD_BIN) spd.bin-type := spd romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/early_init.c similarity index 100% rename from src/mainboard/google/link/romstage.c rename to src/mainboard/google/link/early_init.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 393d582..9f057e5 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -20,3 +20,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/early_init.c similarity index 100% rename from src/mainboard/google/parrot/romstage.c rename to src/mainboard/google/parrot/early_init.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index be1f0fe..652dc6f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -25,3 +25,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/early_init.c similarity index 100% rename from src/mainboard/google/stout/romstage.c rename to src/mainboard/google/stout/early_init.c diff --git a/src/mainboard/hp/2570p/Makefile.inc b/src/mainboard/hp/2570p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/2570p/Makefile.inc +++ b/src/mainboard/hp/2570p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/early_init.c similarity index 100% rename from src/mainboard/hp/2570p/romstage.c rename to src/mainboard/hp/2570p/early_init.c diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/2760p/Makefile.inc +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/early_init.c similarity index 100% rename from src/mainboard/hp/2760p/romstage.c rename to src/mainboard/hp/2760p/early_init.c diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/early_init.c similarity index 100% rename from src/mainboard/hp/8460p/romstage.c rename to src/mainboard/hp/8460p/early_init.c diff --git a/src/mainboard/hp/8470p/Makefile.inc b/src/mainboard/hp/8470p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/8470p/Makefile.inc +++ b/src/mainboard/hp/8470p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/early_init.c similarity index 100% rename from src/mainboard/hp/8470p/romstage.c rename to src/mainboard/hp/8470p/early_init.c diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc index d57c9b5..b480ae4 100644 --- a/src/mainboard/hp/8770w/Makefile.inc +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -14,3 +14,6 @@ ## romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/early_init.c similarity index 100% rename from src/mainboard/hp/8770w/romstage.c rename to src/mainboard/hp/8770w/early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index ebe01ae..261e206 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c similarity index 100% rename from src/mainboard/hp/compaq_8200_elite_sff/romstage.c rename to src/mainboard/hp/compaq_8200_elite_sff/early_init.c diff --git a/src/mainboard/hp/folio_9470m/Makefile.inc b/src/mainboard/hp/folio_9470m/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/folio_9470m/Makefile.inc +++ b/src/mainboard/hp/folio_9470m/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/early_init.c similarity index 100% rename from src/mainboard/hp/folio_9470m/romstage.c rename to src/mainboard/hp/folio_9470m/early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/Makefile.inc b/src/mainboard/hp/revolve_810_g1/Makefile.inc index 7a211f4..e5c8647 100644 --- a/src/mainboard/hp/revolve_810_g1/Makefile.inc +++ b/src/mainboard/hp/revolve_810_g1/Makefile.inc @@ -19,3 +19,6 @@ # FIXME: Other varients with same size onboard ram may exist. SPD_SOURCES = hynix_4g + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/early_init.c similarity index 100% rename from src/mainboard/hp/revolve_810_g1/romstage.c rename to src/mainboard/hp/revolve_810_g1/early_init.c diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 4d516f6..3803149 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -2,3 +2,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/early_init.c similarity index 100% rename from src/mainboard/intel/dcp847ske/romstage.c rename to src/mainboard/intel/dcp847ske/early_init.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index b3bf53f..f2d7b97 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/early_init.c similarity index 100% rename from src/mainboard/intel/emeraldlake2/romstage.c rename to src/mainboard/intel/emeraldlake2/early_init.c diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/early_init.c similarity index 100% rename from src/mainboard/kontron/ktqm77/romstage.c rename to src/mainboard/kontron/ktqm77/early_init.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 2aa7f0f..f1a1016 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -18,3 +18,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/early_init.c similarity index 100% rename from src/mainboard/lenovo/l520/romstage.c rename to src/mainboard/lenovo/l520/early_init.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index dea2e4e..0e4c5e8 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -15,3 +15,6 @@ SPD_SOURCES += hynix_2gb # 0b1000 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/early_init.c similarity index 100% rename from src/mainboard/lenovo/s230u/romstage.c rename to src/mainboard/lenovo/s230u/early_init.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/early_init.c similarity index 100% rename from src/mainboard/lenovo/t420/romstage.c rename to src/mainboard/lenovo/t420/early_init.c diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/early_init.c similarity index 100% rename from src/mainboard/lenovo/t420s/romstage.c rename to src/mainboard/lenovo/t420s/early_init.c diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index ada25f7..0ca0ecd 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -3,3 +3,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/early_init.c similarity index 100% rename from src/mainboard/lenovo/t430/romstage.c rename to src/mainboard/lenovo/t430/early_init.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d70c22e..05763f9 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -19,3 +19,6 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/early_init.c similarity index 100% rename from src/mainboard/lenovo/t430s/romstage.c rename to src/mainboard/lenovo/t430s/early_init.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 7187013..ccf810e 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/early_init.c similarity index 100% rename from src/mainboard/lenovo/t520/romstage.c rename to src/mainboard/lenovo/t520/early_init.c diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 7187013..ccf810e 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/early_init.c similarity index 100% rename from src/mainboard/lenovo/t530/romstage.c rename to src/mainboard/lenovo/t530/early_init.c diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/early_init.c similarity index 100% rename from src/mainboard/lenovo/x131e/romstage.c rename to src/mainboard/lenovo/x131e/early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index ee08d78..5a83f28 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -19,3 +19,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/romstage.c rename to src/mainboard/lenovo/x1_carbon_gen1/early_init.c diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..c988b80 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -18,3 +18,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 100% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/early_init.c similarity index 100% rename from src/mainboard/lenovo/x230/romstage.c rename to src/mainboard/lenovo/x230/early_init.c diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 3dae61e..ea30f64 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1 +1,4 @@ romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/early_init.c similarity index 100% rename from src/mainboard/msi/ms7707/romstage.c rename to src/mainboard/msi/ms7707/early_init.c diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index 5b5ca65..fd4c498 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -19,3 +19,6 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/early_init.c similarity index 100% rename from src/mainboard/roda/rv11/romstage.c rename to src/mainboard/roda/rv11/early_init.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 7f8f966..21c855f 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -30,3 +30,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/early_init.c similarity index 100% rename from src/mainboard/samsung/lumpy/romstage.c rename to src/mainboard/samsung/lumpy/early_init.c diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index a91a061..f50c637 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -18,3 +18,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/early_init.c similarity index 100% rename from src/mainboard/samsung/stumpy/romstage.c rename to src/mainboard/samsung/stumpy/early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 7c555f9..a584a16 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c similarity index 100% rename from src/mainboard/sapphire/pureplatinumh61/romstage.c rename to src/mainboard/sapphire/pureplatinumh61/early_init.c diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 336b47e..3f7bae2 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <southbridge/intel/common/gpio.h> #include <elog.h> static void early_pch_reset_pmcon(void) @@ -53,11 +54,8 @@ if (bist == 0) enable_lapic(); - /* Init LPC, GPIO ... */ - romstage_pch_init(); - - /* Initialize superio */ - mainboard_config_superio(); + /* Init GPIO */ + setup_pch_gpios(&mainboard_gpio_map); /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index ef64825..452fb4f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -14,7 +14,9 @@ */ #include <cpu/intel/car/bootblock.h> +#include <northbridge/intel/sandybridge/sandybridge.h> #include <device/pci_ops.h> +#include <bootblock_common.h> #include "pch.h" /* @@ -78,3 +80,10 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); } + +void bootblock_mainboard_early_init(void) +{ + pch_enable_lpc(); + + mainboard_config_superio(); +} diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index c166f79..5619133 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -264,10 +264,3 @@ pch_generic_setup(); } - -void romstage_pch_init(void) -{ - pch_enable_lpc(); - - setup_pch_gpios(&mainboard_gpio_map); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 9d9570b..9102bb5 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void mainboard_rcba_config(void); void early_pch_init_native(void); void bootblock_pch_init(void); -void romstage_pch_init(void); void early_pch_init_native_dmi_pre(void); void early_pch_init_native_dmi_post(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/33187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b242e7cde0c5799f63331b817d863a0d6c00ab3 Gerrit-Change-Number: 33187 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019