coreboot-gerrit August 2019

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Change in ...coreboot[master]: nb/intel/sandybridge: Fill common MRC settings in northbridge code
by Patrick Rudolph (Code Review) 23 Nov '19

23 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32069 Change subject: nb/intel/sandybridge: Fill common MRC settings in northbridge code ...................................................................... nb/intel/sandybridge: Fill common MRC settings in northbridge code Fill northbridge and southbridge BARs in raminit code. Allows to drop duplicated code from mainboard directories. Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 852da7a..c544a74 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -275,6 +275,24 @@ u32 reserved[4]; } __packed; +static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -286,6 +304,7 @@ enable_usb_bar(); mainboard_fill_pei_data(&pei_data); + northbridge_fill_pei_data(&pei_data); post_code(0x3a); pei_data.boot_mode = s3resume ? 2 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/32069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Gerrit-Change-Number: 32069 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [test] Add -Wsign-compare warning option
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33810 Change subject: [test] Add -Wsign-compare warning option ...................................................................... [test] Add -Wsign-compare warning option Change-Id: I12961fc29ef90f73a5e09a4efdf586ee980cb6d6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33810/1 diff --git a/Makefile.inc b/Makefile.inc index 362243e..37610a2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -401,7 +401,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wsign-compare CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -- To view, visit https://review.coreboot.org/c/coreboot/+/33810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12961fc29ef90f73a5e09a4efdf586ee980cb6d6 Gerrit-Change-Number: 33810 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 13

Change in coreboot[master]: arch/x86: Fix naked reference to CONFIG_NO_CAR_GLOBAL_MIGRATION
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34440 ) Change subject: arch/x86: Fix naked reference to CONFIG_NO_CAR_GLOBAL_MIGRATION ...................................................................... arch/x86: Fix naked reference to CONFIG_NO_CAR_GLOBAL_MIGRATION Found-by: util/lint/kconfig_lint Change-Id: I43408ddd31d7da8fde3253c56053170e01a7fd22 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/car.ld M src/arch/x86/include/arch/early_variables.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34440/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5802b02..ab03da4 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -84,7 +84,7 @@ *(.sbss.*) #else /* .car.global_data objects only around when - * !CONFIG_NO_CAR_GLOBAL_MIGRATION is employed. */ + * !CONFIG(NO_CAR_GLOBAL_MIGRATION) is true. */ *(.car.global_data); #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index a69c230..ca343e7 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -83,7 +83,7 @@ /* * We might end up here if: * 1. ENV_CACHE_AS_RAM is not set for the stage or - * 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_NO_CAR_GLOBAL_MIGRATION + * 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG(NO_CAR_GLOBAL_MIGRATION) is true * is also set. In this case, there is no need to migrate CAR global * variables. But, since we might still be running out of CAR, car_active needs * to return 1 if ENV_CACHE_AS_RAM is set. -- To view, visit https://review.coreboot.org/c/coreboot/+/34440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43408ddd31d7da8fde3253c56053170e01a7fd22 Gerrit-Change-Number: 34440 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: device: Fix naked reference to CONFIG_DEBUG_RAM_SETUP
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34439 ) Change subject: device: Fix naked reference to CONFIG_DEBUG_RAM_SETUP ...................................................................... device: Fix naked reference to CONFIG_DEBUG_RAM_SETUP Found-by: util/lint/kconfig_lint Change-Id: I360c4f563c2aa2acc740eac6c4e0145bda18edb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c M src/device/dram/ddr3.c M src/include/device/dram/common.h M src/include/device/dram/ddr3.h 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/34439/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 60588b8..eec2d74 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -668,8 +668,8 @@ /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is -* selected, or for a purely informative output. +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is +* true, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure */ diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 834dc83..8d79710 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -624,8 +624,8 @@ /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is -* selected, or for a purely informative output. +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is +* true, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure */ diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index b1677c8..7be58ab 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -45,10 +45,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0f9373e..19bce96 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -49,10 +49,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is false, these messages are automatically * disabled. * @{ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I360c4f563c2aa2acc740eac6c4e0145bda18edb7 Gerrit-Change-Number: 34439 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/lenovo/t430: Add support for MRC raminit
by Petr K (Code Review) 22 Nov '19

22 Nov '19

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33539 Change subject: mb/lenovo/t430: Add support for MRC raminit ...................................................................... mb/lenovo/t430: Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on 32500 Signed-off-by: Petr K <piotrkloc94(a)hotmail.com> Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/romstage.c 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33539/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69..a992377 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,32 @@ end end + # PEI data + + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index db50bb3..fa46dc3 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -96,3 +97,19 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + + +void mainboard_fill_pei_data(struct pei_data *pei_data) + +{ + +} + + +int mainboard_should_reset_usb(int s3resume) + +{ + + return !s3resume; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 Gerrit-Change-Number: 33539 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/smm: Provide common smm_relocation_params
by Kyösti Mälkki (Code Review) 22 Nov '19

22 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34840 ) Change subject: intel/smm: Provide common smm_relocation_params ...................................................................... intel/smm: Provide common smm_relocation_params Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c A src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/Makefile.inc M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 16 files changed, 91 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5cda618..5a26aff 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -46,49 +47,10 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d200805..bb19c8c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,6 +28,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> #include "smi.h" @@ -47,15 +48,9 @@ } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; -}; /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest @@ -95,15 +90,6 @@ wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h new file mode 100644 index 0000000..cbcdb56 --- /dev/null +++ b/src/include/cpu/intel/smm_reloc.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __INTEL_SMM_RELOC_H__ +#define __INTEL_SMM_RELOC_H__ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +extern struct smm_relocation_params smm_reloc_params; + +void fill_in_smrr(struct smm_relocation_params *params); + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); +} + +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); +} + +#endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 9fbcc07..e834142 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -31,6 +31,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d25a740..05d7a82 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <reg_script.h> #include <soc/iosf.h> diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index 9ad3128..08c1ad8 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -25,20 +25,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 2cf97e3..5cac560 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -33,33 +34,8 @@ #include <soc/systemagent.h> /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index ed8cbef..3c1f35c 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -28,19 +28,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 3da1a56..a552b58 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -27,6 +27,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -37,15 +38,8 @@ #include "chip.h" /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..b5d45bb 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -4,6 +4,8 @@ subdirs-y += block/ subdirs-y += pch/ +subdirs-y += ../../../cpu/intel/smm + verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 3307cb0..3040688 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -26,18 +26,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - locations live in MSRs. This indicates to the CPUs how to adjust - the SMMBASE and IEDBASE. */ - int smm_save_state_in_msrs; -}; void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 283f5c1..d797438 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -24,6 +24,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <device/pci_ops.h> #include <soc/lpc.h> @@ -33,23 +34,8 @@ #include <soc/broadwell_de.h> /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 5d64d3b..b427085 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -27,18 +27,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 3e949b2..21b9a13 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -36,15 +37,8 @@ #include <soc/systemagent.h> /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 6eb6b1e..8fa415c 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -29,18 +29,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index ebb853a..b80aa14 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -36,15 +37,8 @@ #include "chip.h" /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, -- To view, visit https://review.coreboot.org/c/coreboot/+/34840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Gerrit-Change-Number: 34840 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: intel/microcode: Remove uses of __PRE_RAM__
by Kyösti Mälkki (Code Review) 22 Nov '19

22 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34929 ) Change subject: intel/microcode: Remove uses of __PRE_RAM__ ...................................................................... intel/microcode: Remove uses of __PRE_RAM__ Include file <smp/spinlock.h> has the required logic to define empty stubs for spinlocks. Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34929/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 44f7f1f..7bd072f 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -27,11 +27,9 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> - -#if !defined(__PRE_RAM__) #include <smp/spinlock.h> + DECLARE_SPIN_LOCK(microcode_lock) -#endif struct microcode { u32 hdrver; /* Header Version */ @@ -152,7 +150,7 @@ unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ +#if defined(__ROMCC__) struct cbfs_file *microcode_file; microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); @@ -228,15 +226,11 @@ { const void *patch = intel_microcode_find(); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_lock(&microcode_lock); -#endif intel_microcode_load_unlocked(patch); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_unlock(&microcode_lock); -#endif } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/34929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Gerrit-Change-Number: 34929 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: device/pci: Reduce scope of dev_find_slot()
by Kyösti Mälkki (Code Review) 21 Nov '19

21 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34084 ) Change subject: device/pci: Reduce scope of dev_find_slot() ...................................................................... device/pci: Reduce scope of dev_find_slot() We only keep it around because amdfam10 does not yet work correctly without it. Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34084/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index c1b0b06..691cd80 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -35,6 +35,8 @@ * @param devfn A device/function number. * @return Pointer to the device structure (if found), 0 otherwise. */ + +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn) { @@ -51,6 +53,7 @@ } return result; } +#endif /** * Given a Device Path Type, find the device structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/34084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Gerrit-Change-Number: 34084 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in ...coreboot[master]: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL)
by HAOUAS Elyes (Code Review) 21 Nov '19

21 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32915 Change subject: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) ...................................................................... {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) i945/early_init.c already set to 'RCBA32(V0CTL) = 0x80000001' Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c84..9ab4af1 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -140,9 +140,6 @@ static void rcba_config(void) { - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 0c7c0cf..8c0b3e4 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 502eac3..2404fb7 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; -- To view, visit https://review.coreboot.org/c/coreboot/+/32915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Gerrit-Change-Number: 32915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: [WIP] amdfam10: Remove generic device for SPD eeproms
by Kyösti Mälkki (Code Review) 21 Nov '19

21 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35101 ) Change subject: [WIP] amdfam10: Remove generic device for SPD eeproms ...................................................................... [WIP] amdfam10: Remove generic device for SPD eeproms Change-Id: Id675d3e53c80f84e233b61a3e5e5d127ced2eb40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/bimini_fam10/devicetree.cb M src/mainboard/amd/mahogany_fam10/devicetree.cb M src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb M src/mainboard/amd/tilapia_fam10/devicetree.cb M src/mainboard/asus/kcma-d8/devicetree.cb M src/mainboard/asus/kfsn4-dre/devicetree.cb M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/m4a78-em/devicetree.cb M src/mainboard/asus/m4a785-m/devicetree.cb M src/mainboard/asus/m4a785t-m/devicetree.cb M src/mainboard/asus/m5a88-v/devicetree.cb M src/mainboard/biostar/a68n_5200/devicetree.cb M src/mainboard/gigabyte/ma785gm/devicetree.cb M src/mainboard/gigabyte/ma785gmt/devicetree.cb M src/mainboard/gigabyte/ma78gm/devicetree.cb M src/mainboard/iei/kino-780am2-fam10/devicetree.cb M src/mainboard/jetway/pa78vm5/devicetree.cb M src/mainboard/msi/ms9652_fam10/devicetree.cb M src/mainboard/supermicro/h8dmr_fam10/devicetree.cb M src/mainboard/tyan/s2912_fam10/devicetree.cb M src/mainboard/via/epia-m850/devicetree.cb 22 files changed, 0 insertions(+), 381 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35101/1 diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index c78c508..fb87f81 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index ba6a0faf..0d40b20 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -39,18 +39,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index dba1470..81c7e73 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index 54c34f8..c827678 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -73,32 +73,8 @@ chip drivers/i2c/i2cmux2 # pca9556 smbus mux chip drivers/i2c/i2cmux2 # pca9556 smbus mux device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end end end end diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 06e33f7..9bf9d08 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -42,18 +42,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index f8a2d83..7320716 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -50,30 +50,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end chip drivers/i2c/w83795 register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb index 50e2862..8807a47 100644 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -52,30 +52,6 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end chip drivers/i2c/w83793 register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..4b5488e 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -57,30 +57,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end chip drivers/i2c/w83795 register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb index f336c2b..4ed962b 100644 --- a/src/mainboard/asus/m4a78-em/devicetree.cb +++ b/src/mainboard/asus/m4a78-em/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb index 9dc937c..f426ab5 100644 --- a/src/mainboard/asus/m4a785-m/devicetree.cb +++ b/src/mainboard/asus/m4a785-m/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index 6fce0f3..4a584f3 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -43,18 +43,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb index d0efbdf..7d7f8f5 100644 --- a/src/mainboard/asus/m5a88-v/devicetree.cb +++ b/src/mainboard/asus/m5a88-v/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index fd9b6ed..667e333 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -43,12 +43,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb index 65c76fb..cfc71a7 100644 --- a/src/mainboard/gigabyte/ma785gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb @@ -42,18 +42,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb index a38ebd8..3a99f5c 100644 --- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb @@ -42,18 +42,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 3e69cb3..cedf2f8 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index 6517c97..de7dcce 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -40,12 +40,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 79915ac..de91304 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -41,12 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index c6dae6d..3efe8ec 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -86,56 +86,11 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 1.1 on # SM 1 # PCI device SMBus address will # depend on addon PCI device, do # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index ee88c31..5c8d40c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -55,53 +55,11 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 1.1 on # SM 1 # PCI device SMBus address will # depend on addon PCI device, do # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end chip drivers/generic/generic # MAC EEPROM device i2c 51 on end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index e49e16b..dfc3139 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -55,53 +55,11 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 1.1 on # SM 1 # PCI device SMBus address will # depend on addon PCI device, do # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end chip drivers/generic/generic # MAC EEPROM device i2c 51 on end end diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb index 4dc7c27..e33b173 100644 --- a/src/mainboard/via/epia-m850/devicetree.cb +++ b/src/mainboard/via/epia-m850/devicetree.cb @@ -71,12 +71,6 @@ register "base" = "(void *)0xfec00000" device ioapic 1 on end end - #chip drivers/generic/generic # DIMM 0 channel 1 - # device i2c 50 on end - #end - #chip drivers/generic/generic # DIMM 1 channel 1 - # device i2c 51 on end - #end chip superio/fintek/f81865f # Super duper IO device pnp 4e.0 off end # Floppy device pnp 4e.3 off end # Parallel Port -- To view, visit https://review.coreboot.org/c/coreboot/+/35101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id675d3e53c80f84e233b61a3e5e5d127ced2eb40 Gerrit-Change-Number: 35101 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019