coreboot-gerrit August 2019

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Change in coreboot[master]: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
by Angel Pons (Code Review) 27 Nov '19

27 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35170 ) Change subject: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot ...................................................................... soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35170/1 diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..740ce89 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -35,6 +35,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include <soc/systemagent.h> #include "../chip.h" @@ -50,6 +51,12 @@ fast_spi_early_init(SPI_BASE_ADDRESS); p2sb_enable_bar(); p2sb_configure_hpet(); + + /* Write the IOAPIC Bus:Dev.Fun value to P2SB IBDF register */ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF); + + /* Write the HPET Bus:Dev.Fun value to P2SB HBDF register */ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 43bf27c..ed33c20 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -484,10 +484,8 @@ params->X2ApicOptOut = 0; tconfig->VtdDisable = 0; - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; - params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; - params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; + /* HPET Bus:Dev.Fun already set in coreboot, so tell FSP to ignore UPDs */ + params->PchIoApicBdfValid = 0; } soc_irq_settings(params); diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 565c885..91209c8 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -66,9 +66,11 @@ #define V_P2SB_IBDF_BUS 250 #define V_P2SB_IBDF_DEV 31 #define V_P2SB_IBDF_FUN 0 +#define V_DEFAULT_IBDF ((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN)) #define V_P2SB_HBDF_BUS 250 #define V_P2SB_HBDF_DEV 15 #define V_P2SB_HBDF_FUN 0 +#define V_DEFAULT_HBDF ((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN)) #endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 4844660..a4d1d50 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -246,10 +246,8 @@ cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; - m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; - m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; + /* HPET Bus:Dev.Fun already set in coreboot, so tell FSP to ignore UPDs */ + m_cfg->PchHpetBdfValid = 0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Gerrit-Change-Number: 35170 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: crossgcc: Upgrade llvm to version 8.0.1
by HAOUAS Elyes (Code Review) 27 Nov '19

27 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34527 ) Change subject: crossgcc: Upgrade llvm to version 8.0.1 ...................................................................... crossgcc: Upgrade llvm to version 8.0.1 Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum D util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum 9 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34527/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3b..0130e8e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -58,7 +58,7 @@ PYTHON_VERSION=3.7.4 EXPAT_VERSION=2.2.7 # CLANG version number -CLANG_VERSION=8.0.0 +CLANG_VERSION=8.0.1 MAKE_VERSION=4.2.1 CMAKE_VERSION=3.15.0 NASM_VERSION=2.14.02 diff --git a/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 45225c1..0000000 --- a/util/crossgcc/sum/cfe-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -3cb1e10af3955174a3ca5e560f674f24fac2a02f tarballs/cfe-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..08bc694 --- /dev/null +++ b/util/crossgcc/sum/cfe-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +e1d7f274c4fd623f19255cc52c6d7b39cf8769ee tarballs/cfe-8.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 4a689ab..0000000 --- a/util/crossgcc/sum/clang-tools-extra-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f341ba17494ba756fd404b2744e6f5991b50389f tarballs/clang-tools-extra-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..f2a1261 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +0174e060781fc01e5f97f2ff9b51a03165d7b37a tarballs/clang-tools-extra-8.0.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 2f6cc292..0000000 --- a/util/crossgcc/sum/compiler-rt-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5af387779120bb2a9fad5d6fff1a3d6f4fa6c352 tarballs/compiler-rt-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..b4af06a --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +f6520fb47fae9cc4362a9d50abee22019c27457a tarballs/compiler-rt-8.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum deleted file mode 100644 index 078a3d0..0000000 --- a/util/crossgcc/sum/llvm-8.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0689345d73911e24a07b24cc82dab4fb46b8c323 tarballs/llvm-8.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum new file mode 100644 index 0000000..d255950 --- /dev/null +++ b/util/crossgcc/sum/llvm-8.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +09964f9eabc364f221a3caefbdaea28557273b4a tarballs/llvm-8.0.1.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/34527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1 Gerrit-Change-Number: 34527 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: /mainboard/pcengines/apu2: implement POSTCAR_STAGE
by Krystian Hebel (Code Review) 27 Nov '19

27 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32363 Change subject: /mainboard/pcengines/apu2: implement POSTCAR_STAGE ...................................................................... /mainboard/pcengines/apu2: implement POSTCAR_STAGE As in [1], POSTCAR_STAGE will be required since October 2019. [1]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/HN… Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf --- M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc M src/mainboard/pcengines/apu2/OemCustomize.c A src/mainboard/pcengines/apu2/postcar.c M src/mainboard/pcengines/apu2/romstage.c A src/mainboard/pcengines/apu2/state_machine.c 7 files changed, 213 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32363/1 diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 535024a..0178018 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -16,6 +16,7 @@ #include <AGESA.h> #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> #include <stdlib.h> @@ -23,7 +24,6 @@ #include "imc.h" #include "hudson.h" -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -34,8 +34,7 @@ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); @@ -56,75 +55,66 @@ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ } -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams) { - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + printk(BIOS_DEBUG, "Done\n"); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams) +{ + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - FchParams->Azalia.AzaliaEnable = AzDisable; + FchParams->Azalia.AzaliaEnable = AzDisable; - /* Fan Control */ - oem_fan_control(FchParams); + /* Fan Control */ + oem_fan_control(FchParams); - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; - /* EHCI configuration */ - FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); - if (CONFIG(BOARD_PCENGINES_APU2)) { - // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = FALSE; - } else { - // Enable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = TRUE; - } + if (CONFIG(BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } - // Enable EHCI 1 (port 4 to 7) - // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. - FchParams->Usb.Ehci2Enable = TRUE; + // Enable EHCI 1 (port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; - /* sata configuration */ - FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP - FchParams->Sata.SataDevSlpPort1 = 0; + /* sata configuration */ + FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort1 = 0; - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; } printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; } static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6c3958b..28f9eb8 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4e6364e..7824996 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,10 +14,14 @@ # GNU General Public License for more details. # +romstage-y += state_machine.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c +postcar-y += postcar.c + +ramstage-y += state_machine.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 700f4c7..7ef7e00 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -14,7 +14,7 @@ */ #include <AGESA.h> -#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -76,25 +76,7 @@ .DdiLinkList = NULL, }; -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->PlatformConfig.CStateMode = CStateModeC6; diff --git a/src/mainboard/pcengines/apu2/postcar.c b/src/mainboard/pcengines/apu2/postcar.c new file mode 100644 index 0000000..b57ea94 --- /dev/null +++ b/src/mainboard/pcengines/apu2/postcar.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> + +void late_car_teardown(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index bd3c421..a6fe713 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -40,9 +40,11 @@ static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + pci_devfn_t dev; + u32 data; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for @@ -57,51 +59,32 @@ hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - pci_devfn_t dev; - u32 data; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + post_code(0x30); + early_lpc_init(); - post_code(0x30); - early_lpc_init(); + hudson_clk_output_48Mhz(); + post_code(0x31); - hudson_clk_output_48Mhz(); - post_code(0x31); + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + console_init(); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); @@ -112,27 +95,17 @@ val |= (1 << 30); pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - - timestamp_add_now(TS_BEFORE_INITRAM); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); - - timestamp_add_now(TS_AFTER_INITRAM); } -void agesa_postcar(struct sysinfo *cb) -{ - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); +//~ void agesa_postcar(struct sysinfo *cb) +//~ { + //~ //PspMboxBiosCmdDramInfo(); + //~ post_code(0x41); + //~ AGESAWRAPPER(amdinitenv); - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -} + //~ outb(0xEA, 0xCD6); + //~ outb(0x1, 0xcd7); +//~ } static void early_lpc_init(void) { diff --git a/src/mainboard/pcengines/apu2/state_machine.c b/src/mainboard/pcengines/apu2/state_machine.c new file mode 100644 index 0000000..4a10df9 --- /dev/null +++ b/src/mainboard/pcengines/apu2/state_machine.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> +#include <binaryPI/FieldAccessors.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} + +AGESA_STATUS +AmdGetValue ( + IN CONST AGESA_FIELD_NAME name, + IN OUT VOID** value, + IN UINT32 size + ) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Gerrit-Change-Number: 32363 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

8 21

Change in ...coreboot[master]: [RFC and WIP]Add an option to align FMAP regions
by Arthur Heymans (Code Review) 27 Nov '19

27 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33300 Change subject: [RFC and WIP]Add an option to align FMAP regions ...................................................................... [RFC and WIP]Add an option to align FMAP regions This eases writing FMD files when there are alignment requirement on some regions (e.g. MRC_VAR_CACHE). Some questions: - Do we want to error out on options that have a base defined but that does not follow its alignment or do we want to fix the alignment if such configuration presents itself - '~' is used. Is that the 'best' symbol Change-Id: If6e01112f0c98f45876bcc7012f195f5aa693efd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fmd.c M util/cbfstool/fmd.h M util/cbfstool/fmd_parser.y M util/cbfstool/fmd_scanner.l 4 files changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33300/1 diff --git a/util/cbfstool/fmd.c b/util/cbfstool/fmd.c index 7a289d7..d39ec20 100644 --- a/util/cbfstool/fmd.c +++ b/util/cbfstool/fmd.c @@ -248,6 +248,10 @@ } else if (!first_incomplete_it) { watermark = cur_section->offset + cur_section->size; } + if (cur_section->alignment_known) { + cur_section->offset = (cur_section->offset + cur_section->alignment - 1) + & ~(cur_section->alignment); + } } if (first_incomplete_it && diff --git a/util/cbfstool/fmd.h b/util/cbfstool/fmd.h index 90e6d6e..91ae2fd 100644 --- a/util/cbfstool/fmd.h +++ b/util/cbfstool/fmd.h @@ -53,6 +53,8 @@ bool size_known; /** It is an error to read this field unless size_known is set. */ unsigned size; + bool alignment_known; + unsigned alignment; size_t list_len; union flashmap_flags flags; /** It is an error to dereference this array if list_len is 0. */ diff --git a/util/cbfstool/fmd_parser.y b/util/cbfstool/fmd_parser.y index 3ba710c..e7e1caf 100644 --- a/util/cbfstool/fmd_parser.y +++ b/util/cbfstool/fmd_parser.y @@ -52,7 +52,8 @@ struct flashmap_descriptor *parse_descriptor( char *name, union flashmap_flags flags, struct unsigned_option offset, - struct unsigned_option size, struct descriptor_list children); + struct unsigned_option size, struct unsigned_option alignment, + struct descriptor_list children); void yyerror(const char *s); } @@ -71,6 +72,8 @@ %type <maybe_intval> region_offset %type <maybe_intval> region_size_opt %type <maybe_intval> region_size +%type <maybe_intval> region_alignment_opt +%type <maybe_intval> region_alignment %type <region_listhdr> region_list_opt %type <region_listhdr> region_list %type <region_listhdr> region_list_entries @@ -80,13 +83,14 @@ flash_chip: region_name region_offset_opt region_size region_list { union flashmap_flags flags = { .v=0 }; - if (!(res = parse_descriptor($1, flags, $2, $3, $4))) + struct unsigned_option alignment = { .val_known = false }; + if (!(res = parse_descriptor($1, flags, $2, $3, alignment, $4))) YYABORT; }; flash_region: region_name region_flags_opt region_offset_opt region_size_opt - region_list_opt + region_alignment_opt region_list_opt { - struct flashmap_descriptor *node = parse_descriptor($1, $2, $3, $4, $5); + struct flashmap_descriptor *node = parse_descriptor($1, $2, $3, $4, $5, $6); if (!node) YYABORT; @@ -115,6 +119,9 @@ region_size_opt: { $$ = (struct unsigned_option){false, 0}; } | region_size; region_size: INTEGER { $$ = (struct unsigned_option){true, $1}; }; +region_alignment_opt: { $$ = (struct unsigned_option){false, 0}; } + | region_alignment; +region_alignment: '~' INTEGER { $$ = (struct unsigned_option){true, $2}; }; region_list_opt: { $$ = (struct descriptor_list) @@ -152,7 +159,8 @@ struct flashmap_descriptor *parse_descriptor( char *name, union flashmap_flags flags, struct unsigned_option offset, - struct unsigned_option size, struct descriptor_list children) + struct unsigned_option size, struct unsigned_option alignment, + struct descriptor_list children) { struct flashmap_descriptor *region = malloc(sizeof(*region)); if (!region) { @@ -165,6 +173,8 @@ region->offset = offset.val; region->size_known = size.val_known; region->size = size.val; + region->alignment_known = alignment.val_known; + region->alignment = alignment.val; region->list_len = children.len; if (region->list_len) { region->list = malloc(region->list_len * sizeof(*region->list)); diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l index be9a5de..4c7d322 100644 --- a/util/cbfstool/fmd_scanner.l +++ b/util/cbfstool/fmd_scanner.l @@ -39,7 +39,7 @@ [1-9][0-9]*{MULTIPLIER}? return parse_integer(yytext, 10); 0[0-9]+{MULTIPLIER}? return OCTAL; 0[xX][0-9a-fA-F]+{MULTIPLIER}? return parse_integer(yytext + 2, 16); -[^#@{}()[:space:]]* return copy_string(yytext); +[^#@~{}()[:space:]]* return copy_string(yytext); . return *yytext; %% -- To view, visit https://review.coreboot.org/c/coreboot/+/33300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6e01112f0c98f45876bcc7012f195f5aa693efd Gerrit-Change-Number: 33300 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [WIP] amd/stoneyridge: Fix CAR stack location
by Kyösti Mälkki (Code Review) 26 Nov '19

26 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34883 ) Change subject: [WIP] amd/stoneyridge: Fix CAR stack location ...................................................................... [WIP] amd/stoneyridge: Fix CAR stack location As far as I can see, for BSP, gcccar.inc exits with %esp at _car_region_end, not _car_stack_end. On exit from ENABLE_AMD_STACK, %esp will have value of DCACHE_RAM_BASE + DCACHE_RAM_SIZE. This was correct for the stack placement with C_ENVIRONMENT_BOOTBLOCK=n. It would be nice if AMD code had guards so we knew how much stack it needs. Setting of DCACHE_BSP_STACK_SIZE works with inverse logic now, the higher you set it, the less space is where the stack is located. This raises the question how its size was determined. 00030000 B _car_region_start 00030000 B _car_stack_start 00034000 B _car_stack_end 00034000 B _preram_cbmem_console 00035600 B _car_relocatable_data_start 00035850 B _car_global_start 00035860 B _car_global_end 00035860 B _car_relocatable_data_end 00040000 B _car_region_end Use the symbol _car_stack_end to have early stage use the location assigned by the linker script car.ld. Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/34883/1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4f0bb3f..c23939c 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -31,6 +31,8 @@ .globl _cache_as_ram_setup, _cache_as_ram_setup_end .globl chipset_teardown_car +#if ENV_ROMSTAGE + _cache_as_ram_setup: /* Preserve BIST. */ @@ -49,6 +51,10 @@ AMD_ENABLE_STACK + /* Let arch/x86/car.ld determine our stack location. + * FIXME: Only do this for BSP. !! */ + movl $_car_stack_end, %esp + /* Align the stack. */ and $0xFFFFFFF0, %esp @@ -107,6 +113,8 @@ pushl %eax call romstage_main +#endif /* ENV_ROMSTAGE */ + #if CONFIG(POSTCAR_STAGE) /* We do not return. Execution continues with run_postcar_phase() diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 402da3a..ad0ea53 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -38,6 +38,10 @@ AMD_ENABLE_STACK + /* Let arch/x86/car.ld determine our stack location. + * FIXME: Only do this for BSP. !! */ + movl $_car_stack_end, %esp + /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp sub $8, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/34883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7 Gerrit-Change-Number: 34883 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
by Krystian Hebel (Code Review) 26 Nov '19

26 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32421 Change subject: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER ...................................................................... nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. AmdGetValue() is required by cpu_bus_scan(), it is adapted from binaryPI wrapper to use new interface for dispatcher. Tested only on 00730F01 (apu2) - no other platforms available. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc A src/northbridge/amd/pi/state_machine.c 5 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32421/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c..c64a7ba 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1006,3 +1009,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df725..08dfd84 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -991,3 +994,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 926208c..f69f226 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -40,6 +40,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1242,3 +1244,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d88..349761b 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -22,6 +22,9 @@ ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += agesawrapper.c ramstage-y += agesawrapper.c +else +romstage-y += state_machine.c +ramstage-y += state_machine.c endif romstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/state_machine.c b/src/northbridge/amd/pi/state_machine.c new file mode 100644 index 0000000..f42e97f --- /dev/null +++ b/src/northbridge/amd/pi/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2019 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Gerrit-Change-Number: 32421 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

6 24

Change in ...coreboot[master]: MSR: Move MSR_PLATFORM_INFO to common place
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33504 Change subject: MSR: Move MSR_PLATFORM_INFO to common place ...................................................................... MSR: Move MSR_PLATFORM_INFO to common place Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 13 files changed, 2 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/1 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 6c5cc31..4ee294f 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -30,8 +30,6 @@ #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4ebbe18..b7ce762 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -43,8 +43,6 @@ #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5..cc830a9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -30,8 +30,6 @@ #define FERR_ENABLE (1 << 0) #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434..795ab79 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -30,8 +30,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8c558ce..a4657c5 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,9 +25,10 @@ #define CPUID_DCA (1 << 18) #define CPUID_AES (1 << 25) #define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8dd9b75..dd333e8 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,8 +11,6 @@ #define TSC_SYNC #endif -#define MSR_PLATFORM_INFO 0xce - struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c..8b35355 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 6137820..a121180 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -18,7 +18,6 @@ #define _SOC_MSR_H_ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index e8e3aa2..58dcba8 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,7 +18,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e..655b325 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,7 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 0d469c4..d63257b 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -20,7 +20,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index b8fe7fe..8ace3f6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index e4b8c50..6ae0bae 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -19,7 +19,6 @@ #define _SOC_MSR_H_ #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 -- To view, visit https://review.coreboot.org/c/coreboot/+/33504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Gerrit-Change-Number: 33504 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: mainboard/gigabyte: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33898 Change subject: mainboard/gigabyte: remove stdlib.h when unused ...................................................................... mainboard/gigabyte: remove stdlib.h when unused Change-Id: Id80fa9cfb2cc72730fc0ced545d6f0a9d0e48715 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/ma785gm/get_bus_conf.c M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c M src/mainboard/gigabyte/ma78gm/get_bus_conf.c 3 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33898/1 diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 5c53476..16fdca1 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable -- To view, visit https://review.coreboot.org/c/coreboot/+/33898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id80fa9cfb2cc72730fc0ced545d6f0a9d0e48715 Gerrit-Change-Number: 33898 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mainboard/{advansus,tyan}: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33902 Change subject: mainboard/{advansus,tyan}: remove stdlib.h when unused ...................................................................... mainboard/{advansus,tyan}: remove stdlib.h when unused Change-Id: Id95329ee6906b1def8e9024b64088ef6ae9ca200 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/get_bus_conf.c M src/mainboard/tyan/s2912_fam10/get_bus_conf.c 2 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33902/1 diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 6b5ae68..7aca540 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index f589ef6..dc30718 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -- To view, visit https://review.coreboot.org/c/coreboot/+/33902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95329ee6906b1def8e9024b64088ef6ae9ca200 Gerrit-Change-Number: 33902 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/lenovo/*: Add MAINBOARD_FAMILY
by Patrick Rudolph (Code Review) 23 Nov '19

23 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32727 Change subject: mb/lenovo/*: Add MAINBOARD_FAMILY ...................................................................... mb/lenovo/*: Add MAINBOARD_FAMILY The Kconfig MAINBOARD_FAMILY sets the family type of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/thinkcentre_a58/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/z61t/Kconfig 19 files changed, 84 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32727/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..e6dbddd 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -39,6 +39,10 @@ string default "LENOVO G505S" +config MAINBOARD_FAMILY + string + default "LENOVO G505S" + config HW_MEM_HOLE_SIZEK hex default 0x200000 diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 4495d79..8066bf3 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -26,6 +26,10 @@ string default "ThinkPad L520" +config MAINBOARD_FAMILY + string + default "ThinkPad L520" + config VGA_BIOS_FILE string default "pci8086,0126.rom" diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 9200ad5..b388646 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -28,6 +28,10 @@ string default "ThinkPad S230U (Twist)" +config MAINBOARD_FAMILY + string + default "ThinkPad S230U (Twist)" + config EC_BASE_ADDRESS hex default 0xff000000 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9f94051..db6c98a 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -37,6 +37,13 @@ default "ThinkPad R400" if BOARD_LENOVO_R400 default "ThinkPad W500" if BOARD_LENOVO_W500 +config MAINBOARD_FAMILY + string + default "ThinkPad T400" if BOARD_LENOVO_T400 + default "ThinkPad T500" if BOARD_LENOVO_T500 + default "ThinkPad R400" if BOARD_LENOVO_R400 + default "ThinkPad W500" if BOARD_LENOVO_W500 + config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index ce81907..fb4f0ee 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -36,6 +36,10 @@ string default "ThinkPad T420" +config MAINBOARD_FAMILY + string + default "ThinkPad T420" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index c5efb55..c603753 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -35,6 +35,10 @@ string default "ThinkPad T420s" +config MAINBOARD_FAMILY + string + default "ThinkPad T420s" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb..3c2a473 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -34,6 +34,10 @@ string default "ThinkPad T430" +config MAINBOARD_FAMILY + string + default "ThinkPad T430" + config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837..9f69430 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -40,6 +40,11 @@ default "ThinkPad T430s" if BOARD_LENOVO_T430S default "ThinkPad T431s" if BOARD_LENOVO_T431S +config MAINBOARD_FAMILY + string + default "ThinkPad T430s" if BOARD_LENOVO_T430S + default "ThinkPad T431s" if BOARD_LENOVO_T431S + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..62a91a6 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -45,6 +45,11 @@ default "ThinkPad T520" if BOARD_LENOVO_T520 default "ThinkPad W520" if BOARD_LENOVO_W520 +config MAINBOARD_FAMILY + string + default "ThinkPad T520" if BOARD_LENOVO_T520 + default "ThinkPad W520" if BOARD_LENOVO_W520 + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d..62a3ac8 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -45,6 +45,11 @@ default "ThinkPad T530" if BOARD_LENOVO_T530 default "ThinkPad W530" if BOARD_LENOVO_W530 +config MAINBOARD_FAMILY + string + default "ThinkPad T530" if BOARD_LENOVO_T530 + default "ThinkPad W530" if BOARD_LENOVO_W530 + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index a6a88b3..2ef5ebf 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,6 +33,10 @@ string default "ThinkPad T60" +config MAINBOARD_FAMILY + string + default "ThinkPad T60" + config MAX_CPUS int default 2 diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index fc1c6a7..1e31c89 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -43,6 +43,10 @@ string default "ThinkCentre A58" +config MAINBOARD_FAMILY + string + default "ThinkCentre A58" + config MAX_CPUS int default 4 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0..a61c1bd 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -29,6 +29,10 @@ string default "ThinkPad X131e" +config MAINBOARD_FAMILY + string + default "ThinkPad X131e" + config MAX_CPUS int default 4 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c..6c84ba6 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -34,6 +34,10 @@ string default "ThinkPad X1 carbon gen 1" +config MAINBOARD_FAMILY + string + default "ThinkPad X1 Carbon gen 1" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7b905bc..8b341cc 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -32,6 +32,10 @@ string default "ThinkPad X200" +config MAINBOARD_FAMILY + string + default "ThinkPad X200" + config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 16f42e8..1861984 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -35,13 +35,18 @@ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I default "x1" if BOARD_LENOVO_X1 - config MAINBOARD_PART_NUMBER string default "ThinkPad X220" if BOARD_LENOVO_X220 default "ThinkPad X220i" if BOARD_LENOVO_X220I default "ThinkPad X1" if BOARD_LENOVO_X1 +config MAINBOARD_FAMILY + string + default "ThinkPad X220" if BOARD_LENOVO_X220 + default "ThinkPad X220i" if BOARD_LENOVO_X220I + default "ThinkPad X1" if BOARD_LENOVO_X1 + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83..2da651e 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -35,6 +35,10 @@ string default "ThinkPad X230" +config MAINBOARD_FAMILY + string + default "ThinkPad X230" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 6db7f11..6ffe3b6 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -36,6 +36,10 @@ string default "ThinkPad X60" +config MAINBOARD_FAMILY + string + default "ThinkPad X60" + config IRQ_SLOT_COUNT int default 18 diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index a223077..f0a20fd 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -33,6 +33,10 @@ string default "ThinkPad Z61t" +config MAINBOARD_FAMILY + string + default "ThinkPad Z61t" + config MAX_CPUS int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Gerrit-Change-Number: 32727 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019