coreboot-gerrit August 2019

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Change in coreboot[master]: util/crosgcc/patches: facilitate successful build of ipxe
by Name of user not set (Code Review) 26 Oct '19

26 Oct '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35098 ) Change subject: util/crosgcc/patches: facilitate successful build of ipxe ...................................................................... util/crosgcc/patches: facilitate successful build of ipxe New changes in the latest binutils(2.32) leads to assembler errors causes ipxe build failure. IPXE uses the divide test which requires /dev/null as input as well as the output file name. This patch facilitates the /dev/null as an exception to the current changes in binutils package while building crossgcc for coreboot leads to successful build of ipxe and further tests to pass based on /dev/null and applies automatically during the crossgcc rebuild. Also this can be reverted once binutils/ipxe provides update release in this respect. Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- A util/crossgcc/patches/binutils-2.32_as-ipxe.patch 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35098/1 diff --git a/util/crossgcc/patches/binutils-2.32_as-ipxe.patch b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch new file mode 100644 index 0000000..ab5b9b2 --- /dev/null +++ b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch @@ -0,0 +1,35 @@ +From 6984bd861cc595e56d26ea033851d9174e855129 Mon Sep 17 00:00:00 2001 +From: CunningLearner <sahdev.himan(a)gmail.com> +Date: Mon, 26 Aug 2019 16:57:13 +0530 +Subject: [PATCH] as: facilitate tests based on /dev/null Signed-off-by: + Himanshu Sahdev <himanshusah(a)hcl.com> + +--- + gas/as.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gas/as.c b/gas/as.c +index 728811bc..78b4802c 100644 +--- a/gas/as.c ++++ b/gas/as.c +@@ -1203,7 +1203,7 @@ main (int argc, char ** argv) + { + char ** argv_orig = argv; + struct stat sob; +- ++ const char *dev_null_file="/dev/null"; + int macro_strip_at; + + start_time = get_run_time (); +@@ -1252,7 +1252,7 @@ main (int argc, char ** argv) + so that switches like --hash-size can be honored. */ + parse_args (&argc, &argv); + +- if (argc > 1 && stat (out_file_name, &sob) == 0) ++ if (argc > 1 && stat (out_file_name, &sob) == 0 && strcmp(out_file_name,dev_null_file)!=0) + { + int i; + +-- +2.17.1 + -- To view, visit https://review.coreboot.org/c/coreboot/+/35098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a Gerrit-Change-Number: 35098 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

4 20

Change in ...coreboot[master]: [UNTESTED]soc/intel/braswell: Use native code to update BSP microcode
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33563 Change subject: [UNTESTED]soc/intel/braswell: Use native code to update BSP microcode ...................................................................... [UNTESTED]soc/intel/braswell: Use native code to update BSP microcode This removes the need to specify the microcode size and location in Kconfig. Change-Id: I9a391a3956b30dd8727bec669cb79a0a8588d5f0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S M src/mainboard/facebook/fbg1701/Kconfig M src/soc/intel/braswell/Kconfig 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33563/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3460b9d..733c523 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -53,6 +53,15 @@ * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. */ + +#if CONFIG(MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif + lea fake_fsp_stack, %esp jmp find_fsp find_fsp_ret: diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index b3c589d..e92022b 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -56,16 +56,6 @@ hex default 0x00800000 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x10C00 - help - This should be updated when the microcode patch changes. - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFFE9400 - config MRC_SETTINGS_CACHE_SIZE hex default 0x08000 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 920179f83..45a0cf8 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -52,6 +52,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select C_ENVIRONMENT_BOOTBLOCK + select MICROCODE_UPDATE_PRE_RAM config DCACHE_BSP_STACK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/33563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a391a3956b30dd8727bec669cb79a0a8588d5f0 Gerrit-Change-Number: 33563 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: [DONOTMERGE] Revert "soc/intel: Replace uses of dev_find_slot()"
by Matt DeVillier (Code Review) 22 Oct '19

22 Oct '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35087 ) Change subject: [DONOTMERGE] Revert "soc/intel: Replace uses of dev_find_slot()" ...................................................................... [DONOTMERGE] Revert "soc/intel: Replace uses of dev_find_slot()" This reverts commit 903b40a8a46b6e8d853f509480661c8174311f17: soc/intel: Replace uses of dev_find_slot() This commit caused more havok than initially realized. Even after f2ac0137 [soc/intel: Fix regression with hidden PCI devices], SKL/KBL still has numerous issues with XHCI and SATA devices, possibly more. With Linux as payload, XHCI and SATA fail to init/funcion. With Tianocore, Windows installer can't find any devices to install from or to. This commit is just to provide a temp fix for those that need it, and to raise awareness of the issue. Change-Id: I744a8065344a33a6e85818bf32fa669e987fea6f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c 32 files changed, 70 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35087/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index cec706f..6208c9c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -186,7 +186,7 @@ static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -219,7 +219,7 @@ * get the info and hide it again when done. */ p2sb_unhide(); - struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); + struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); p2sb_hide(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1d5e6d9..e9030dc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -256,7 +256,7 @@ int i; unsigned int inc = PCI_DEVFN(0, 1); - func0 = pcidev_path_on_root(devfn0); + func0 = dev_find_slot(0, devfn0); if (func0 == NULL) return; @@ -272,7 +272,7 @@ * as that port was move to func0. */ for (i = 1; i < num_funcs; i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); + struct device *dev = dev_find_slot(0, devfn); if (dev == NULL) continue; @@ -760,7 +760,7 @@ apl_fsp_silicon_init_params_cb(cfg, silconfig); /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_XDCI); + dev = dev_find_slot(0, PCH_DEVFN_XDCI); if (!xdci_can_enable()) dev->enabled = 0; silconfig->UsbOtg = dev->enabled; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index a334f63..335a485 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -22,8 +22,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 3436364..6058e34 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum; - dev = pcidev_path_on_root(PCH_DEVFN_LPC); + dev = dev_find_slot(0, PCH_DEVFN_LPC); assert(dev != NULL); config = dev->chip_info; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 1bf3202..22f5309 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -149,7 +149,7 @@ DEVTREE_CONST struct soc_intel_apollolake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 72a566a..5d65a00 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -100,7 +100,7 @@ /* Thermal throttle activation offset */ static void configure_thermal_target(void) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); if (!dev) { printk(BIOS_ERR, "Could not find SOC devicetree config\n"); return; @@ -320,7 +320,7 @@ { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -350,7 +350,7 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd) { #if CONFIG(SOC_INTEL_GLK) - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); if (!dev) return; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 25867c5..e51c9bf 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -580,7 +580,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 522e3eb..03456ca 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -25,8 +25,8 @@ #else #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #endif /* System Agent Devices */ diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index ea2726b..ef97a1e 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -79,7 +79,7 @@ const struct device *dev; const config_t *config; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); if (!dev || !dev->chip_info) return; config = dev->chip_info; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 26c2847..ff9da45 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -293,7 +293,7 @@ static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -306,7 +306,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU); uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a58a97c..783ebb7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -51,7 +51,7 @@ { struct device *dev; - dev = pcidev_path_on_root(serial_io_dev[dev_offset]); + dev = dev_find_slot(0, serial_io_dev[dev_offset]); if (!dev || !dev->enabled) return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled); @@ -178,7 +178,7 @@ params->PchLockDownRtcMemoryLock = 0; /* SATA */ - dev = pcidev_path_on_root(PCH_DEVFN_SATA); + dev = dev_find_slot(0, PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -192,7 +192,7 @@ } /* Lan */ - dev = pcidev_path_on_root(PCH_DEVFN_GBE); + dev = dev_find_slot(0, PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else { @@ -275,7 +275,7 @@ } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -287,7 +287,7 @@ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; /* Enable CNVi Wifi if enabled in device tree */ - dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); + dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); #if CONFIG(SOC_INTEL_COMETLAKE) if (dev) params->CnviMode = dev->enabled; @@ -314,7 +314,7 @@ sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ - dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + dev = dev_find_slot(0, PCH_DEVFN_EMMC); if (!dev) params->ScsEmmcEnabled = 0; else { @@ -329,7 +329,7 @@ } } - dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + dev = dev_find_slot(0, PCH_DEVFN_SDCARD); if (!dev) { params->ScsSdCardEnabled = 0; } else { @@ -338,7 +338,7 @@ CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } - dev = pcidev_path_on_root(PCH_DEVFN_UFS); + dev = dev_find_slot(0, PCH_DEVFN_UFS); if (!dev) params->ScsUfsEnabled = 0; else diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 1bc028f..42d3a4f 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 355c36b..3cae54f 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -219,7 +219,7 @@ uintptr_t dram_base; const struct device *dev; - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) die_with_post_code(POST_HW_INIT_FAILURE, "ERROR - IGD device not found!"); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 9997d16..ab36c70 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -177,7 +177,7 @@ DEVTREE_CONST struct soc_intel_cannonlake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index eb71f5d..a1e3d76 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -30,7 +30,7 @@ { unsigned int i; uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; @@ -85,7 +85,7 @@ m_cfg->PchIshEnable = dev->enabled; /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); + dev = dev_find_slot(0, PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else @@ -100,8 +100,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index cc5a7dd..de0c153 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -78,12 +78,12 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", __func__); - return ; + return; } config = dev->chip_info; diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 303ba67..b902097 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -27,8 +27,8 @@ #if ENV_RAMSTAGE #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index ef95f7e..ba7ba0f 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -37,7 +37,7 @@ #else struct device *get_hostbridge_dev(void) { - return pcidev_on_root(SA_DEV, SA_FUNC); + return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC)); } #endif @@ -49,7 +49,7 @@ #else struct device *get_lpc_dev(void) { - return pcidev_on_root(LPC_DEV, LPC_FUNC); + return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); } #endif @@ -61,7 +61,7 @@ #else struct device *get_pmc_dev(void) { - return pcidev_on_root(PMC_DEV, PMC_FUNC); + return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC)); } #endif @@ -73,7 +73,7 @@ #else struct device *get_smbus_dev(void) { - return pcidev_on_root(SMBUS_DEV, SMBUS_FUNC); + return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); } #endif diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 50f8a29..07e0704 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -76,7 +76,7 @@ last one. */ for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) { struct device *uart_dev; - uart_dev = pcidev_on_root(HSUART_DEV, i); + uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i)); if (uart_dev == NULL) continue; pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1); diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 1348f23b..af69247 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -23,8 +23,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 67f71da..22950ba 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -217,7 +217,7 @@ uintptr_t dram_base; const struct device *dev; - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) die_with_post_code(POST_HW_INIT_FAILURE, "ERROR - IGD device not found!"); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 45f2a70..27e7720 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -175,7 +175,7 @@ DEVTREE_CONST struct soc_intel_icelake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 3d41ee0..b39f37b 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -75,7 +75,7 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_icelake_config *config; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 910db97..bd944da 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -174,7 +174,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Set unknown wake source */ @@ -561,7 +561,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; @@ -584,7 +584,7 @@ acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); + struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; @@ -695,7 +695,7 @@ /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7fbe9e5..ce90385 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -92,7 +92,7 @@ /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; int i; @@ -152,7 +152,7 @@ params->ScsSdCardEnabled = config->ScsSdCardEnabled; /* Enable ISH if device is on */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); + dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) params->IshEnable = dev->enabled; else @@ -219,11 +219,11 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); + dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index a1fced2..859eea4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -102,7 +102,7 @@ for (group = 0; group < pci_groups; group++) { devfn0 = pcie_rp_group[group].devfn; - func0 = pcidev_path_on_root(devfn0); + func0 = dev_find_slot(0, devfn0); if (func0 == NULL) continue; @@ -119,7 +119,7 @@ */ for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); + struct device *dev = dev_find_slot(0, devfn); if (dev == NULL || !dev->enabled) continue; @@ -357,7 +357,7 @@ } /* If ISH is enabled, enable ISH elements */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); + dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) params->PchIshEnable = dev->enabled; else @@ -436,11 +436,11 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); + dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 5acaaeb..d59c800 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) @@ -39,7 +39,7 @@ #define SA_DEV_SLOT_PEG 0x01 #define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) -#define SA_DEV_PEG(func) pcidev_path_on_root(SA_DEVFN_PEG(func)) +#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) #define SA_DEV_PEG0 SA_DEV_PEG(0) #define SA_DEV_PEG1 SA_DEV_PEG(1) #define SA_DEV_PEG2 SA_DEV_PEG(2) diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 03cdb07..d10ca74 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -223,7 +223,7 @@ uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Get Device Int Count */ diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 9732aa1..7d0dc0a 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -178,7 +178,7 @@ DEVTREE_CONST struct soc_intel_skylake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2bbab47..29c4774 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -57,7 +57,7 @@ const struct soc_intel_skylake_config *config; /* Set the parameters for MemoryInit */ - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; /* diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 6884a32..fafa343 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -301,7 +301,7 @@ { const struct device *dev; - dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = dev_find_slot(0, SA_DEVFN_IGD); if (!dev || !dev->enabled) { /* * If iGPU is disabled or not defined in the devicetree.cb, @@ -331,7 +331,7 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 00f620f..7eb0bf5 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,8 +26,7 @@ static void systemagent_vtd_init(void) { - const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; if (root_dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/35087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I744a8065344a33a6e85818bf32fa669e987fea6f Gerrit-Change-Number: 35087 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/skylake/vr_config: Add VR config for Skylake S
by Maxim Polyakov (Code Review) 21 Oct '19

21 Oct '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35167 ) Change subject: soc/skylake/vr_config: Add VR config for Skylake S ...................................................................... soc/skylake/vr_config: Add VR config for Skylake S These changes are in accordance with the documentation: [*] page 112-119, 6th Generation Intel(R) Processor Families for S-Platforms, Volume 1 of 2, Datasheet, August 2018. Document Number: 332687-008EN Tested on Asrock H110M DVS with i5-6600 (4 cores) CPU Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 42 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35167/1 diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index fc48558..82f3fdc 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -113,28 +113,37 @@ * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the * Iccmax is the same among KBL-Y but KBL-U/R. * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * KBL-S #335195, KBL-H #335190 - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-S) | 11.1A | 100A | 48A | 48A | - * | | | ... | 45A | 45A | - * | | | 40A | 35A | 35A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-H) | 11.1A (45W) | 68A | 55A | 55A | - * | | 6.6A (18W) | 60A | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) | | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ + * KBL-S #335195, KBL-H #335190, SKL-S #332687 + * +---------------------+-------------+-------+------+------+-----+ + * | Domain/Setting | Cores/TDP | SA | IA | GTUS | GTS | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-S/SKL-S) | 4C/91W | 11.1A | 100A | 45A | 45A | + * | | 4C/80W * | | 82A | | | + * | | 4C/65W | | 79A | | | + * | | 4C/45W * | | 70A | 35A | 35A | + * | | 4C/35W | | 66A | | | + * | | 4C/25W * | | 55A | | | + * | | 2C/54W | | 58A | 48A | 48A | + * | | 2C/51W | | 45A | | | + * | | 2C/35W | | 40A | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-H) | 4C/45W | 11.1A | 68A | 55A | 55A | + * | | 4C/18W | 6.6A | 60A | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-U/R) | 4C/15W (U42)| 6A | 64A | 31A | 31A | + * | | 2C/15W (P/C)| 4.5A | 29A | | | + * | | 2C/28W (OPC)| | 32A | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(KBL-Y) | 2C/4.5W | 4.1A | 24A | 24A | 24A | + * | | 2C/6W | | | | | + * +---------------------+-------------+-------+------+------+-----+ + * | IccMax(AML-Y) | 2C/5W | 4.1A | 28A | 24A | 24A | + * +---------------------+-------------+-------+------+------+-----+ + * [*] - for Skylake only */ switch (mch_id) { + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: case PCI_DEVICE_ID_INTEL_KBL_ID_S: { uint16_t icc_max[NUM_VR_DOMAINS] = { VR_CFG_AMP(11.1), @@ -148,21 +157,28 @@ icc_max[VR_IA_CORE] = VR_CFG_AMP(45); return icc_max[domain]; - } + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { uint16_t icc_max[NUM_VR_DOMAINS] = { VR_CFG_AMP(11.1), - VR_CFG_AMP(66), + VR_CFG_AMP(55), VR_CFG_AMP(45), VR_CFG_AMP(45), }; if (tdp >= 91) icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + else if (tdp >= 80) + icc_max[VR_IA_CORE] = VR_CFG_AMP(82); else if (tdp >= 65) icc_max[VR_IA_CORE] = VR_CFG_AMP(79); - else if (tdp >= 35) { + else if (tdp >= 45) + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + else if (tdp >= 25) { + if (tdp >= 35) + icc_max[VR_IA_CORE] = VR_CFG_AMP(66); + icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35); icc_max[VR_GT_SLICED] = VR_CFG_AMP(35); } @@ -241,8 +257,10 @@ } switch (mch_id) { - case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ - case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: + case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: + case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { static const uint16_t loadline[NUM_VR_DOMAINS] = { VR_CFG_MOHMS(0), /* Not specified */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19 Gerrit-Change-Number: 35167 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 28

Change in coreboot[master]: [TEST-ONLY] change flashmap size for agesa debug build.
by chris wang (Code Review) 21 Oct '19

21 Oct '19

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34842 to review the following change. Change subject: [TEST-ONLY] change flashmap size for agesa debug build. ...................................................................... [TEST-ONLY] change flashmap size for agesa debug build. increse COREBOOT size which from reduced from RO_UNUSED BUG=none TEST=build careena coreboot image successfully with agesa debug enabling. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ib44338af183d404d1e422cefa484d83aca9e1a19 --- M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34842/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index b746545..f48e8e4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -28,13 +28,13 @@ WP_RO@0xC00000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0x17B000 - RO_SECTION@0x17F000 0x281000 { + RO_UNUSED@0x4000 0x170000 + RO_SECTION@0x174000 0x28C000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x210000 + COREBOOT(CBFS)@0x71000 0x21B000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/34842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib44338af183d404d1e422cefa484d83aca9e1a19 Gerrit-Change-Number: 34842 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: NOT_FOR_MERGE: soc/amd/picasso: Add dummy UPD header files
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34575 ) Change subject: NOT_FOR_MERGE: soc/amd/picasso: Add dummy UPD header files ...................................................................... NOT_FOR_MERGE: soc/amd/picasso: Add dummy UPD header files These are for internal development and put in a convenient include path. The final versions will be automatically generated and delivered with the binaries. Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/soc/amd/picasso/include/FspUpd.h A src/soc/amd/picasso/include/FspmUpd.h A src/soc/amd/picasso/include/FspsUpd.h 3 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34575/1 diff --git a/src/soc/amd/picasso/include/FspUpd.h b/src/soc/amd/picasso/include/FspUpd.h new file mode 100644 index 0000000..28bc98e --- /dev/null +++ b/src/soc/amd/picasso/include/FspUpd.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPM_UPD_SIGNATURE 0x4d5f4f5341434950 /* 'PICASO_M' */ + +#define FSPS_UPD_SIGNATURE 0x535f4f5341434950 /* 'PICASO_S' */ + +#pragma pack() + +#endif diff --git a/src/soc/amd/picasso/include/FspmUpd.h b/src/soc/amd/picasso/include/FspmUpd.h new file mode 100644 index 0000000..705af0c --- /dev/null +++ b/src/soc/amd/picasso/include/FspmUpd.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + +/** Fsp M Configuration +**/ +typedef struct { + UINT32 SerialDebugPortAddress; +} FSP_M_CONFIG; + +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0160 +**/ + UINT8 UnusedUpdSpace2[158]; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/soc/amd/picasso/include/FspsUpd.h b/src/soc/amd/picasso/include/FspsUpd.h new file mode 100644 index 0000000..1249eaa --- /dev/null +++ b/src/soc/amd/picasso/include/FspsUpd.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + +/** Fsp S Configuration +**/ +typedef struct { + UINT8 ReservedFspsUpd[16]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0380 +**/ + UINT8 UnusedUpdSpace8[46]; + +/** Offset 0x03AE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Gerrit-Change-Number: 34575 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/picasso: Adjust I2C ASL
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34915 ) Change subject: soc/picasso: Adjust I2C ASL ...................................................................... soc/picasso: Adjust I2C ASL Clarify names as I2C2, etc. Use iomap.h defines for base addresses. Update IRQs. Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/picasso/i2c.c 2 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/34915/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 13b9025..680f496 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -113,43 +113,13 @@ } } -Device (I2CA) { - Name (_HID, "AMD0010") - Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000) - }) - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (I2CB) -{ - Name (_HID, "AMD0010") - Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (I2CC) { +Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000) + IRQ (Edge, ActiveHigh, Exclusive) { 4 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -158,13 +128,27 @@ } } -Device (I2CD) +Device (I2C3) { Name (_HID, "AMD0010") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { + IRQ (Edge, ActiveHigh, Exclusive) { 6 } + Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C4) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x4) + Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + Memory32Fixed(ReadWrite, APU_I2C4_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 8786643..bcdf385 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -73,11 +73,11 @@ { switch (dev->path.mmio.addr) { case APU_I2C2_BASE: - return "I2CC"; + return "I2C2"; case APU_I2C3_BASE: - return "I2CD"; + return "I2C3"; case APU_I2C4_BASE: - return "I2CE"; + return "I2C4"; default: return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025 Gerrit-Change-Number: 34915 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Update iomap
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33991 Change subject: soc/amd/picasso: Update iomap ...................................................................... soc/amd/picasso: Update iomap Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 23 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33991/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 275e17b..49952cb 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -22,6 +22,11 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define ESPI_BASE_ADDRESS 0xfec20000 +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + /* * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. * All ranges not specified as supported below may, or may not, be listed in @@ -43,28 +48,32 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 -/* I2C fixed address */ +/* Reserved 0xfecd1000-0xfedc3fff */ + #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -#define APU_I2C_MIN_BUS 2 -#define APU_I2C_MAX_BUS 4 -#define APU_I2C_BLOCK_SIZE 0x1000 -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 3 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 3 - -#if CONFIG(HPET_ADDRESS_OVERRIDE) -#error HPET address override is not allowed and must be fixed at 0xfed00000 -#endif -#define HPET_BASE_ADDRESS 0xfed00000 - +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 #define APU_UART1_BASE 0xfedca000 +/* Reserved 0xfedcb000 */ +#define APU_DMAC2_BASE 0xfedcc000 +#define APU_DMAC3_BASE 0xfedcd000 #define APU_UART2_BASE 0xfedce000 #define APU_UART3_BASE 0xfedcf000 -#define APU_UART_MAX_PORT 3 +#define APU_UART_MAX_PORT 3 + +/* Reserved 0xfedd0000-0xfedd4fff */ +#define APU_EMMC_BASE 0xfedd5000 +#define APU_EMMC_CONFIG_BASE 0xfedd5800 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/33991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 Gerrit-Change-Number: 33991 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/amd/picasso: Update UARTs
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33767 Change subject: src/soc/amd/picasso: Update UARTs ...................................................................... src/soc/amd/picasso: Update UARTs Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/uart.c 2 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33767/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index b9d1ab5..b06e101 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -59,8 +59,11 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_UART_MAX_PORT 3 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d5d3006..339bd27 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -16,12 +16,19 @@ #include <console/uart.h> #include <soc/southbridge.h> +static const uintptr_t uart_addresses[] = { + APU_UART0_BASE, + APU_UART1_BASE, + APU_UART2_BASE, + APU_UART3_BASE, +}; + uintptr_t uart_platform_base(int idx) { - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + if (idx < 0 || idx > APU_UART_MAX_PORT) return 0; - return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); + return uart_addresses[uart]; } unsigned int uart_platform_refclk(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Gerrit-Change-Number: 33767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Update for vbios
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34422 to review the following change. Change subject: soc/amd/picasso: Update for vbios ...................................................................... soc/amd/picasso: Update for vbios Add Picasso's Device ID and default filename. Only a single Device ID is documented for Picasso so remove the oprom remapper function. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/northbridge.c 3 files changed, 3 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34422/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 10e1930..840de12 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -93,14 +93,14 @@ config VGA_BIOS_ID string - default "1002,98e4" + default "1002,15d8" help The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c. config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/picasso/VBIOS.bin" + default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" config S3_VGA_ROM_RUN bool diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index d6887f9..acde455 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -42,7 +42,7 @@ /* Internal Graphics */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ +#define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 627ce03..a39e79a 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -329,19 +329,3 @@ assign_resources(dev->link_list); } -/********************************************************************* - * Change the vendor / device IDs to match the generic VBIOS header. * - *********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; - - if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", - vendev, new_vendev); - - return new_vendev; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 Gerrit-Change-Number: 34422 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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