coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

1 participants
1942 discussions

Change in coreboot[master]: WIP: ifdtool validation documentation
by Mathew King (Code Review) 16 Oct '19

16 Oct '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34866 ) Change subject: WIP: ifdtool validation documentation ...................................................................... WIP: ifdtool validation documentation Change-Id: I160e838e816a718644f38906c877b0fa6136df40 --- R Documentation/ifdtool/Binary_Extraction.md A Documentation/ifdtool/Validation.md A Documentation/ifdtool/index.md M Documentation/index.md M Documentation/util.md M util/README.md 6 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34866/1 diff --git a/Documentation/Binary_Extraction.md b/Documentation/ifdtool/Binary_Extraction.md similarity index 100% rename from Documentation/Binary_Extraction.md rename to Documentation/ifdtool/Binary_Extraction.md diff --git a/Documentation/ifdtool/Validation.md b/Documentation/ifdtool/Validation.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Documentation/ifdtool/Validation.md diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md new file mode 100644 index 0000000..ab7061c --- /dev/null +++ b/Documentation/ifdtool/index.md @@ -0,0 +1,5 @@ + +Contents: + +* [Intel IFD Binary Extraction](Binary_Extraction.md) +* [IFD Validation](Validation.md) \ No newline at end of file diff --git a/Documentation/index.md b/Documentation/index.md index a2c2878..1d8b40b 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -169,7 +169,6 @@ * [coreboot at conferences](community/conferences.md) * [Payloads](payloads.md) * [Distributions](distributions.md) -* [Intel IFD Binary Extraction](Binary_Extraction.md) * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) diff --git a/Documentation/util.md b/Documentation/util.md index f8fabc1..3a09b00 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -47,7 +47,7 @@ * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdtool__ - Extract and dump Intel Firmware Descriptor information +* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine even if hidden `C` diff --git a/util/README.md b/util/README.md index 470013e..b42e313 100644 --- a/util/README.md +++ b/util/README.md @@ -45,7 +45,7 @@ * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdtool__ - Extract and dump Intel Firmware Descriptor information +* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine even if hidden `C` -- To view, visit https://review.coreboot.org/c/coreboot/+/34866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I160e838e816a718644f38906c877b0fa6136df40 Gerrit-Change-Number: 34866 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/sifive/fu540 : test and fix code of fu540 spi
by Xiang Wang (Code Review) 16 Oct '19

16 Oct '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35117 ) Change subject: soc/sifive/fu540 : test and fix code of fu540 spi ...................................................................... soc/sifive/fu540 : test and fix code of fu540 spi I tested the SPI through the SD card and fixed some problems. Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/soc/sifive/fu540/spi.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/1 diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index 6bf1700..3580146 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -61,6 +61,25 @@ return (uint8_t) out; } +static int spi_claim_bus_(const struct spi_slave *slave) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_HOLD; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); + return 0; +} + +static void spi_release_bus_(const struct spi_slave *slave) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_OFF; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); +} + static int spi_xfer_(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) @@ -126,6 +145,8 @@ sckmode.pol = FU540_SPI_POL_LEADING; write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + write32(&spictrl->csdef, -1); + csmode.raw_bits = 0; csmode.mode = FU540_SPI_CSMODE_AUTO; write32(&spictrl->csmode.raw_bits, csmode.raw_bits); @@ -133,7 +154,7 @@ fmt.raw_bits = 0; fmt.proto = FU540_SPI_PROTO_S; fmt.endian = FU540_SPI_ENDIAN_BIG; - fmt.dir = 1; + fmt.dir = 0; fmt.len = 8; write32(&spictrl->fmt.raw_bits, fmt.raw_bits); @@ -143,6 +164,8 @@ struct spi_ctrlr fu540_spi_ctrlr = { .xfer = spi_xfer_, .setup = spi_setup_, + .claim_bus = spi_claim_bus_, + .release_bus = spi_release_bus_, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { @@ -187,6 +210,8 @@ sckmode.pol = config->pol; write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + write32(&spictrl->csdef, -1); + csmode.raw_bits = 0; csmode.mode = FU540_SPI_CSMODE_AUTO; write32(&spictrl->csmode.raw_bits, csmode.raw_bits); @@ -194,7 +219,7 @@ fmt.raw_bits = 0; fmt.proto = config->protocol; fmt.endian = config->endianness; - fmt.dir = 1; + fmt.dir = 0; fmt.len = config->bits_per_frame; write32(&spictrl->fmt.raw_bits, fmt.raw_bits); -- To view, visit https://review.coreboot.org/c/coreboot/+/35117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6 Gerrit-Change-Number: 35117 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 18

Change in ...coreboot[master]: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
by Arthur Heymans (Code Review) 16 Oct '19

16 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33549 Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges ...................................................................... [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges Most mainboards do nothing but setting up a similar decode range so move it to a common place. All IO ports below 0x1000 are allocated to the LPC device by default so this should not be an issue. Lynxpoint does this too. TODO remove most mainboard specific setups. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 0082c91..ef3ee77 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,8 +258,16 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -static void pch_enable_lpc_gen_decode(void) +static void pch_enable_lpc_decode(void) { + /* Set COM1/COM2 decode range */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN + | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; @@ -279,9 +287,10 @@ void early_pch_init(void) { - pch_enable_lpc(); - pch_enable_lpc_gen_decode(); + pch_enable_lpc_decode(); + + pch_enable_lpc(); pch_enable_bars(); -- To view, visit https://review.coreboot.org/c/coreboot/+/33549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Gerrit-Change-Number: 33549 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 17

Change in ...coreboot[master]: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
by Michał Żygowski (Code Review) 14 Oct '19

14 Oct '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30753 Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI ...................................................................... src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 --- M src/soc/intel/fsp_baytrail/smm.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/1 diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 84f8d28..149272d 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <string.h> +#include <bootstate.h> #include <soc/iomap.h> #include <soc/pmc.h> @@ -124,3 +125,16 @@ "d" (APM_CNT) ); } + +static void finalize_chipset(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + /* Lock sleep stretching policy and set SMI lock. */ + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2), + read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)) + | SLPSX_STR_POL_LOCK | SMI_LOCK); + outb(APM_CNT_FINALIZE, APM_CNT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/30753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 Gerrit-Change-Number: 30753 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: soc/intel/skylake: Use common cpu/intel/car romstage entry
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33019 Change subject: soc/intel/skylake: Use common cpu/intel/car romstage entry ...................................................................... soc/intel/skylake: Use common cpu/intel/car romstage entry Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/romstage/Makefile.inc M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33019/1 diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index e929eba..7bb9d4b 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 96937d6..7eebc3a 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -17,6 +17,7 @@ #include <arch/early_variables.h> #include <arch/symbols.h> #include <assert.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -135,25 +136,27 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(unsigned long bist) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps; - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); +} + +void platform_enter_postcar(void) +{ + uintptr_t top_of_ram; + struct postcar_frame pcf; + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a Gerrit-Change-Number: 33019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33058 Change subject: [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM ...................................................................... [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM Fetching the option table from cbfs each time is slowing things down and adds a vulnerability during S3 resume. Change-Id: I9f9001fd0090fd1b56ee518d426aa3d3025dba59 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/pc80/rtc/mc146818rtc.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33058/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 535ba33..5ef8506 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -25,6 +25,7 @@ #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_CBTABLE 0x43425442 #define CBMEM_ID_CBTABLE_FWD 0x43425443 +#define CBMEM_ID_CMOS_TABLE 0x366f1abb #define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_COVERAGE 0x47434f56 #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 @@ -88,6 +89,7 @@ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ { CBMEM_ID_CBTABLE, "COREBOOT " }, \ { CBMEM_ID_CBTABLE_FWD, "COREBOOTFWD" }, \ + { CBMEM_ID_CMOS_TABLE, "CMOS " }, \ { CBMEM_ID_CONSOLE, "CONSOLE " }, \ { CBMEM_ID_COVERAGE, "COVERAGE " }, \ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3667354..ee16cf1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <bcd.h> +#include <cbmem.h> #include <fallback.h> #include <stdint.h> #include <version.h> @@ -272,6 +273,15 @@ static enum cb_err get_layout(struct cmos_option_table *ct) { +#if !(defined(__PRE_RAM__) || ENV_SMM) + struct cmos_option_table *table; + table = cbmem_find(CBMEM_ID_CMOS_TABLE); + if (table) { + ct = table; + return CB_SUCCESS; + } +#endif + LOCK_NVRAM_CBFS_SPINLOCK(); if (locate_cmos_layout(&rdev) != CB_SUCCESS) { @@ -286,6 +296,14 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } +#if !(defined(__PRE_RAM__) || ENV_SMM) + table = cbmem_add(CBMEM_ID_CMOS_TABLE, region_device_sz(&rdev)); + if (table) { + memcpy(table, ct, region_device_sz(&rdev)); + ct = table; + } +#endif + return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9001fd0090fd1b56ee518d426aa3d3025dba59 Gerrit-Change-Number: 33058 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: drivers/pc80/rtc: Move fetching and cleaning up the layout
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33057 Change subject: drivers/pc80/rtc: Move fetching and cleaning up the layout ...................................................................... drivers/pc80/rtc: Move fetching and cleaning up the layout Both get_option and set_option need to fetch the layout and clean up afterwards. Do this in a common location. Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 39 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33057/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 6e37cd2..3667354 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -268,22 +268,12 @@ return CB_SUCCESS; } -enum cb_err get_option(void *dest, const char *name) +struct region_device rdev; + +static enum cb_err get_layout(struct cmos_option_table *ct) { - struct cmos_option_table *ct; - struct region_device rdev; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - if (!CONFIG(USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - LOCK_NVRAM_CBFS_SPINLOCK(); - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; @@ -296,6 +286,32 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } + return CB_SUCCESS; +} + +static void clean_up_layout(struct cmos_option_table *ct) +{ + rdev_munmap(&rdev, ct); + UNLOCK_NVRAM_CBFS_SPINLOCK(); +} + +enum cb_err get_option(void *dest, const char *name) +{ + struct cmos_option_table *ct = NULL;; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + if (!CONFIG(USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + + LOCK_NVRAM_CBFS_SPINLOCK(); + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + if (get_layout(ct) != CB_SUCCESS) + return CB_CMOS_LAYOUT_NOT_FOUND; /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -308,23 +324,19 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_SUCCESS; } @@ -383,8 +395,7 @@ enum cb_err set_option(const char *name, void *value) { - struct cmos_option_table *ct; - struct region_device rdev; + struct cmos_option_table *ct = NULL; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -396,18 +407,8 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); + if (get_layout(ct) != CB_SUCCESS) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -420,7 +421,7 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -430,17 +431,17 @@ /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } } if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Gerrit-Change-Number: 33057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32969 Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point ...................................................................... soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point This moves some boilerplate like setting up timestamps and entering postcar to a common location. Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c 2 files changed, 4 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32969/1 diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463..8f009bd 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,5 +1,6 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cc3bcd9..2a530b4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -21,6 +21,7 @@ #include <bootblock_common.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> @@ -49,8 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void platform_enter_postcar(void); - static void program_base_addresses(void) { uint32_t reg; @@ -166,18 +165,12 @@ } /* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +void mainboard_romstage_entry(unsigned long bist) { struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - program_base_addresses(); tco_disable(); @@ -215,25 +208,13 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; -- To view, visit https://review.coreboot.org/c/coreboot/+/32969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Gerrit-Change-Number: 32969 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/baytrail: Place the raminit in a common location
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32968 Change subject: soc/intel/baytrail: Place the raminit in a common location ...................................................................... soc/intel/baytrail: Place the raminit in a common location Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 3 files changed, 43 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32968/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index c244c83..93b6ba4 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -58,7 +58,7 @@ return spd_ptr; } -void mainboard_romstage_entry(struct mrc_params *mrc_params) +void mainboard_pre_raminit(struct mrc_params *mrc_params) { void *spd_content; int dual_channel = 0; @@ -80,6 +80,4 @@ mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) mrc_params->mainboard.dram_data[1] = spd_content; - - romstage_common(mrc_params); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index ea6298b..7730893 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,8 +24,7 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -void mainboard_romstage_entry(struct mrc_params *mrc_params); -void romstage_common(struct mrc_params *mrc_params); +void mainboard_pre_raminit(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 73991df..cc3bcd9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -96,49 +96,6 @@ write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) -{ - struct mrc_params mrc_params; - - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - - /* Call into mainboard. */ - mainboard_romstage_entry(&mrc_params); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -208,12 +165,38 @@ return prev_sleep_state; } -/* Entry from the mainboard. */ -void romstage_common(struct mrc_params *mrc_params) +/* Entry from cache-as-ram.inc. */ +static void romstage_main(uint64_t tsc, uint32_t bist) { + struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; + /* Save initial timestamp from bootblock. */ + timestamp_init(tsc); + + /* Save romstage begin */ + timestamp_add_now(TS_START_ROMSTAGE); + + program_base_addresses(); + + tco_disable(); + + byt_config_com1_and_enable(); + + console_init(); + + spi_init(); + + set_max_freq(); + + punit_init(); + + gfx_init(); + + /* Call into mainboard. */ + mainboard_pre_raminit(&mrc_params); + timestamp_add_now(TS_BEFORE_INITRAM); ps = fill_power_state(); @@ -226,13 +209,24 @@ boot_count_increment(); #endif - /* Initialize RAM */ - raminit(mrc_params, prev_sleep_state); + raminit(&mrc_params, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); + + platform_enter_postcar(); + + /* We don't return here */ +} + +/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83 Gerrit-Change-Number: 32968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/baytrail: Extend the scope of the mrc_params
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32967 Change subject: soc/intel/baytrail: Extend the scope of the mrc_params ...................................................................... soc/intel/baytrail: Extend the scope of the mrc_params This makes it easier to call the common_romstage code in a common place. Change-Id: I58c5c376c51b48a7cb9b3bc79dd77e417c98d8ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32967/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index eba8beb..c244c83 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -21,6 +21,8 @@ #include <soc/romstage.h> #include <variant/variant.h> +static void *spd_ptr; + static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; @@ -52,7 +54,8 @@ if (dual_channel_config & (1 << ram_id)) *dual = 1; - return &spd_file_content[SPD_SIZE * ram_id]; + spd_ptr = &spd_file_content[SPD_SIZE * ram_id]; + return spd_ptr; } void mainboard_romstage_entry(struct mrc_params *mrc_params) @@ -73,6 +76,7 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); + mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) mrc_params->mainboard.dram_data[1] = spd_content; diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 4fceefb..ea6298b 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -26,7 +26,6 @@ void mainboard_romstage_entry(struct mrc_params *mrc_params); void romstage_common(struct mrc_params *mrc_params); - void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58c5c376c51b48a7cb9b3bc79dd77e417c98d8ae Gerrit-Change-Number: 32967 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2019