coreboot-gerrit August 2019

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Change in ...coreboot[master]: [WIP] Reduce (void **) pointer usage
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30684 Change subject: [WIP] Reduce (void **) pointer usage ...................................................................... [WIP] Reduce (void **) pointer usage Use uintptr_t * instead. Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/stage_cache.c M src/cpu/intel/model_206ax/stage_cache.c M src/drivers/intel/fsp1_1/include/fsp/memmap.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/include/fsp/memmap.h M src/drivers/intel/fsp2_0/stage_cache.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/baytrail/stage_cache.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/stage_cache.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/block/include/intelblocks/smm.h M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/smmrelocate.c 35 files changed, 102 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30684/1 diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c index 009cc09..fb4a6c3 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/cpu/intel/haswell/stage_cache.c @@ -17,10 +17,10 @@ #include <stage_cache.h> #include "haswell.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c index 26dc5e0..a0aaba5 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/cpu/intel/model_206ax/stage_cache.c @@ -17,12 +17,12 @@ #include <stage_cache.h> #include "model_206ax.h" -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of RAM is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = cbmem_top() + RESERVED_SMM_OFFSET; } diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7fed2a1..ad9e9dd 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -147,12 +147,12 @@ /* Display SMM area */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - char *smm_base; + uintptr_t smm_base; size_t smm_size; - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base); #endif /* Migrate CAR data */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 864ab45..41d5437 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -33,19 +33,19 @@ /* Display SMM memory map */ static void smm_memory_map(void) { - void *base; + uintptr_t base; size_t size; int i; printk(BIOS_SPEW, "SMM Memory Map\n"); smm_region(&base, &size); - printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + printk(BIOS_SPEW, "SMRAM : 0x%08x 0x%zx\n", (unsigned int)base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); + printk(BIOS_SPEW, " Subregion %d: 0x%08x 0x%zx\n", i, (unsigned int)base, size); } } diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index eb2a637..1b748aa 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -117,9 +117,8 @@ num_mtrrs++; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uint32_t tseg_base; /* * Cache the TSEG region at the top of ram. This region is not @@ -128,11 +127,10 @@ * the SMM handler as well as using the TSEG region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uint32_t)smm_base; slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + slot = stack_push32(slot, (uint32_t)smm_base | MTRR_TYPE_WRBACK); num_mtrrs++; #endif diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c index 2d594e6..4895340 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/drivers/intel/fsp1_1/stage_cache.c @@ -18,11 +18,11 @@ #include <fsp/memmap.h> #include <stage_cache.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h index 965bce6..49bd019 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h @@ -27,7 +27,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -42,6 +42,6 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..2ea6656 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -20,11 +20,11 @@ #include <reset.h> #include <program_loading.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 28cb859..2a6c3bc 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -41,7 +41,7 @@ /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..35bcce4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -32,12 +32,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -48,12 +48,12 @@ static void stage_cache_recover(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, (void *)(size + base)); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..e5b8bea 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -62,21 +62,21 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* Initialize global tracking state. */ smm_region_info(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.tseg_base = relo_attrs.smbase; relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); relo_attrs.tseg_mask |= SMM_TSEG_WB; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d62c791..82be938 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -114,12 +114,12 @@ * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); /* * Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); void domain_enable_resources(struct device *dev); void domain_read_resources(struct device *dev); void domain_set_resources(struct device *dev); diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 15968ab..ea3bd8b 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -80,18 +80,18 @@ return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } @@ -117,7 +117,7 @@ wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -143,7 +143,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9314488..e89f9e6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -82,7 +82,7 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; uintptr_t tseg_base; msr_t base, mask; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bcec28e..89faa85 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -196,9 +196,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index be15e16..50ececa 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -48,7 +48,7 @@ return tolum; } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -56,7 +56,6 @@ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region_info(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; assert(sub_size > CONFIG_SMM_RESERVED_SIZE); @@ -74,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c index 4c2a976..8e8c67f 100644 --- a/src/soc/intel/baytrail/stage_cache.c +++ b/src/soc/intel/baytrail/stage_cache.c @@ -17,7 +17,7 @@ #include <stage_cache.h> #include <soc/smm.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { char *smm_base; /* 1MiB cache size */ @@ -27,5 +27,5 @@ * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + *base = smm_base + smm_region_size() - cache_size; } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 12f34fb..b4face2 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -147,7 +147,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; /* All range registers are aligned to 4KiB */ diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d7c9952..89c3ab0 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -29,9 +29,9 @@ return smm_size; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } @@ -51,15 +51,13 @@ * | (TSEG) | * +-------------------------+ BUNIT_SMRRL */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; - void *sub_ptr; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_ptr, &sub_size); - sub_base = (uintptr_t)sub_ptr; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -75,7 +73,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; @@ -83,7 +81,7 @@ void *cbmem_top(void) { - char *smm_base; + uintptr_t smm_base; size_t smm_size; /* @@ -114,6 +112,6 @@ * +-------------------------+ */ - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 6e148b9..36b4377 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -87,7 +87,7 @@ unsigned long mmconf; unsigned long bmbound_k; unsigned long bmbound_hi; - void *smm_base; + uintptr_t smm_base; size_t smm_size; unsigned long tseg_base_k; unsigned long tseg_top_k; diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index dc59ab7..b812ced 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -18,7 +18,7 @@ #include <stage_cache.h> #include <stdint.h> -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { /* The ramstage cache lives in the TSEG region. * The top of RAM is defined to be the TSEG base address. */ @@ -26,6 +26,6 @@ offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(cbmem_top() + offset); + *base = cbmem_top() + offset; *size = CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..8aeabac 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -29,9 +29,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -46,16 +46,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -77,7 +75,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index e688592..59ae790 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -173,11 +173,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t *ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -196,9 +196,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -232,24 +232,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46..e2d38fd 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -33,6 +33,6 @@ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); /* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); +void smm_region_info(uintptr_t *start, size_t *size); #endif diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index d929975..d9b5645 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -89,9 +89,9 @@ ); } -void smm_region_info(void **start, size_t *size) +void smm_region_info(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7..683af8e 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -91,9 +91,9 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ @@ -108,7 +108,7 @@ relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 771c3d8..e597e9d 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -33,7 +33,7 @@ /* Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); +void smm_region(uintptr_t *start, size_t *size); enum { /* SMM handler area. */ @@ -48,7 +48,7 @@ /* Fills in the start and size for the requested SMM subregion. Returns * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); +int smm_subregion(int sub, uintptr_t *start, size_t *size); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index a42d861..b4812ab 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -71,13 +71,13 @@ return system_agent_region_base(TOLUD) - smm_region_start(); } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; @@ -102,7 +102,7 @@ return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; return 0; diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 617b64a..712ec83 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -147,9 +147,8 @@ uintptr_t top_of_ram; #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; #endif console_init(); @@ -190,8 +189,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); #endif run_postcar_phase(&pcf); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 027b8b0..20ae6e8 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -28,9 +28,9 @@ #include <soc/systemagent.h> #include <stdlib.h> -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -45,16 +45,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -76,7 +74,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 57a366a..bb81799 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -172,11 +172,11 @@ static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { - void *handler_base; + uintptr_t handler_base; size_t handler_size; - void *ied_base; + uintptr_t ied_base; size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -195,9 +195,9 @@ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; + params->smram_base = handler_base; - params->ied_base = (uintptr_t)ied_base; + params->ied_base = ied_base; params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -231,24 +231,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + 1 * MiB, 0, 32 * KiB); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index f0ccb1d..c33787a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,9 +40,9 @@ return 8*MiB; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -57,16 +57,14 @@ * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { - uintptr_t sub_base; size_t sub_size; - void *smm_base; + uintptr_t smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; switch (sub) { case SMM_SUBREGION_HANDLER: @@ -88,7 +86,7 @@ return -1; } - *start = (void *)sub_base; + *start = smm_base; *size = sub_size; return 0; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..248f50f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -167,7 +167,7 @@ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - void *smm_base; + uintptr_t *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -179,7 +179,7 @@ * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; + tseg_base = smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index cb4e23f..82aacd4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -241,24 +241,21 @@ static void setup_ied_area(struct smm_relocation_params *params) { - char *ied_base; - struct ied_header ied = { .signature = "INTEL RSVD", .size = params->ied_size, .reserved = {0}, }; - ied_base = (void *)params->ied_base; printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); + memcpy(params->ied_base, &ied, sizeof(ied)); /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); + memset(params->ied_base + 1 * MiB, 0, 32 * KiB); } void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, -- To view, visit https://review.coreboot.org/c/coreboot/+/30684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2 Gerrit-Change-Number: 30684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 19

Change in ...coreboot[master]: console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices'
by Arthur Heymans (Code Review) 01 Nov '19

01 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32042 Change subject: console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices' ...................................................................... console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices' This has nothing to do with console options. This also improves the help text to reflect what it actually does. Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/console/Kconfig M src/device/Kconfig 2 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32042/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667..fb87e67 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -176,13 +176,6 @@ # TODO: Deps? # TODO: Improve description. -config ONBOARD_VGA_IS_PRIMARY - bool "Use onboard VGA as primary video device" - default n - depends on PCI - help - If not selected, the last adapter found will be used. - config CONSOLE_NE2K bool "Network console over NE2000 compatible Ethernet adapter" default n diff --git a/src/device/Kconfig b/src/device/Kconfig index 8001b43..2da12bc 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -683,4 +683,14 @@ I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config ONBOARD_VGA_IS_PRIMARY + bool "Use onboard VGA as primary video device" + default n + depends on PCI + help + This option lets you select which VGA device will be used + to decode legacy VGA cycles. Not all chipsets implement this + however. If not selected, the last adapter found will be used, + else the onboard adapter is used. + endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Gerrit-Change-Number: 32042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: sb/intel/common: Make linking pmbase.c conditional
by Arthur Heymans (Code Review) 30 Oct '19

30 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33200 Change subject: sb/intel/common: Make linking pmbase.c conditional ...................................................................... sb/intel/common: Make linking pmbase.c conditional Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33200/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..42717b0 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -10,6 +10,10 @@ def_bool n depends on SOUTHBRIDGE_INTEL_COMMON +config SOUTHBRIDGE_INTEL_COMMON_PMBASE + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON + config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n @@ -35,6 +39,7 @@ def_bool n select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_PMBASE config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index dbc9c93..ac2fd8e 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -38,8 +38,10 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) -$(eval $(call add_to_all_stages,y,pmbase.c)) +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE),pmbase.c)) +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE),y) smm-y += pmbase.c +endif bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Gerrit-Change-Number: 33200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 15

Change in ...coreboot[master]: sb/intel/common/Makefile: Use the macro to link files in all stages
by Arthur Heymans (Code Review) 30 Oct '19

30 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33199 Change subject: sb/intel/common/Makefile: Use the macro to link files in all stages ...................................................................... sb/intel/common/Makefile: Use the macro to link files in all stages This links the reset function, the common pmbase functions and the spi driver in all stages. Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Makefile.inc 1 file changed, 4 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33199/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index ab5e5d8..dbc9c93 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,11 +27,7 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware -verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c -postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET),reset.c)) romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c @@ -42,10 +38,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) -verstage-y += pmbase.c -romstage-y += pmbase.c -ramstage-y += pmbase.c -postcar-y += pmbase.c +$(eval $(call add_to_all_stages,y,pmbase.c)) smm-y += pmbase.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c @@ -56,9 +49,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +$(eval $(call add_to_all_stages,$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI),spi.c)) ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c endif @@ -73,10 +64,6 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c -verstage-y += rtc.c -romstage-y += rtc.c -ramstage-y += rtc.c -postcar-y += rtc.c -smm-y += rtc.c +$(eval $(call add_to_all_stages,y,rtc.c)) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Gerrit-Change-Number: 33199 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 14

Change in ...coreboot[master]: sb/intel/common: Add macro to link a file in all stages
by Arthur Heymans (Code Review) 30 Oct '19

30 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33198 Change subject: sb/intel/common: Add macro to link a file in all stages ...................................................................... sb/intel/common: Add macro to link a file in all stages It is easy to forget to link some files which breaks the build when some Kconfig options get enabled. Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Makefile.inc 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33198/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4cf6e6f..ab5e5d8 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -13,6 +13,17 @@ ## GNU General Public License for more details. ## +# add SPI drivers per stage except smm +# $1 condition +# $2 filename +define add_to_all_stages +bootblock-$(1) += $(2) +verstage-$(1) += $(2) +romstage-$(1) += $(2) +postcar-$(1) += $(2) +ramstage-$(1) += $(2) +endef + # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware -- To view, visit https://review.coreboot.org/c/coreboot/+/33198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9 Gerrit-Change-Number: 33198 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 28

Change in coreboot[master]: mainboard: Add Lenovo ThinkPad T440p
by Iru Cai (vimacs) (Code Review) 30 Oct '19

30 Oct '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34359 to review the following change. Change subject: mainboard: Add Lenovo ThinkPad T440p ...................................................................... mainboard: Add Lenovo ThinkPad T440p The code is based on autoport. Tested: - i5-4300M, 8G+8G - keyboard and trackpoint - USB - SATA - WLAN - Arch Linux loaded from SeaBIOS - libgfxinit - ACPI support Issues: - The touchpad is misconfigured, there's no middle button, and the 3 keys on top are all identified as left button - The Fn key is on by default Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/lenovo/t440p/Kconfig A src/mainboard/lenovo/t440p/Kconfig.name A src/mainboard/lenovo/t440p/Makefile.inc A src/mainboard/lenovo/t440p/acpi/ec.asl A src/mainboard/lenovo/t440p/acpi/platform.asl A src/mainboard/lenovo/t440p/acpi/superio.asl A src/mainboard/lenovo/t440p/acpi_tables.c A src/mainboard/lenovo/t440p/board_info.txt A src/mainboard/lenovo/t440p/devicetree.cb A src/mainboard/lenovo/t440p/dsdt.asl A src/mainboard/lenovo/t440p/gma-mainboard.ads A src/mainboard/lenovo/t440p/gpio.c A src/mainboard/lenovo/t440p/hda_verb.c A src/mainboard/lenovo/t440p/mainboard.c A src/mainboard/lenovo/t440p/romstage.c A src/mainboard/lenovo/t440p/smihandler.c 16 files changed, 837 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34359/1 diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig new file mode 100644 index 0000000..59a257e --- /dev/null +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -0,0 +1,41 @@ +if BOARD_LENOVO_THINKPAD_T440P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default lenovo/t440p + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T440p" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/t440p/Kconfig.name b/src/mainboard/lenovo/t440p/Kconfig.name new file mode 100644 index 0000000..e90299d --- /dev/null +++ b/src/mainboard/lenovo/t440p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T440P + bool "ThinkPad T440p" diff --git a/src/mainboard/lenovo/t440p/Makefile.inc b/src/mainboard/lenovo/t440p/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/t440p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t440p/acpi/ec.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl new file mode 100644 index 0000000..c3569e8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl new file mode 100644 index 0000000..dfced7a --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -0,0 +1,12 @@ +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/t440p/acpi/superio.asl b/src/mainboard/lenovo/t440p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c new file mode 100644 index 0000000..5dc98d8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/t440p/board_info.txt b/src/mainboard/lenovo/t440p/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb new file mode 100644 index 0000000..df98ef8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -0,0 +1,165 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x12ba12ba" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x12ba12ba" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x89" + register "pirqe_routing" = "0x86" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8b" + register "pirqh_routing" = "0x87" + register "sata_ahci" = "1" + # 0(HDD), 5(ODD) + register "sata_port_map" = "0x21" + device pci 14.0 on # xHCI Controller + subsystemid 0x17aa 0x220e + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x220e + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x220e + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x220e + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x220e + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x220e + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x220e + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x220e + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x220e + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x0d" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x220e + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x220e + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x220e + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x220e + end + device pci 03.0 on # Mini-HD audio Audio controller + subsystemid 0x17aa 0x220e + end + end +end diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl new file mode 100644 index 0000000..4838877 --- /dev/null +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -0,0 +1,31 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/t440p/gma-mainboard.ads b/src/mainboard/lenovo/t440p/gma-mainboard.ads new file mode 100644 index 0000000..ce27742 --- /dev/null +++ b/src/mainboard/lenovo/t440p/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t440p/gpio.c b/src/mainboard/lenovo/t440p/gpio.c new file mode 100644 index 0000000..16fef44 --- /dev/null +++ b/src/mainboard/lenovo/t440p/gpio.c @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c new file mode 100644 index 0000000..ac509bf --- /dev/null +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c new file mode 100644 index 0000000..dcfd503 --- /dev/null +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c new file mode 100644 index 0000000..28f766b --- /dev/null +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0, 0xa2, 0 }, + .ec_present = 0, + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */ + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */ + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + .bist = bist, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c new file mode 100644 index 0000000..5ea7118 --- /dev/null +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +/* lynxpoint doesn't have gpi_route_interrupt, so add it */ +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + +static void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Gerrit-Change-Number: 34359 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 44

Change in ...coreboot[master]: src/cpu: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Oct '19

28 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33680 Change subject: src/cpu: Use 'include <stdlib.h>' when appropriate ...................................................................... src/cpu: Use 'include <stdlib.h>' when appropriate Also add some missing includes spotted by Jenkins Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/family_10h-family_15h/processor_name.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mirror_payload.c 4 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33680/1 diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index c5d523a..95985cd 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -94,6 +94,7 @@ #include <device/pci_ops.h> #include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> +#include <stdlib.h> static inline void print_debug_fv(const char *str, u32 val) { diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index 5672efd..ac0b57f 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -32,6 +32,8 @@ #include <device/pci.h> #include <device/pnp.h> #include <device/pci_ops.h> +#include <stddef.h> +#include <stdlib.h> /* The maximum length of CPU names is 48 bytes, including the final NULL byte. * If you change these names your BIOS will _NOT_ pass the AMD validation and diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0f73e71..e1908d8 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -34,6 +34,7 @@ #include <smp/spinlock.h> #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> +#include <stdlib.h> #include <thread.h> /* This is a lot more paranoid now, since Linux can NOT handle diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index 88c5e81..f6420f2 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -14,12 +14,12 @@ */ #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <commonlib/helpers.h> #include <console/console.h> #include <bootmem.h> #include <program_loading.h> +#include <stddef.h> void mirror_payload(struct prog *payload) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Gerrit-Change-Number: 33680 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src/southbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Oct '19

28 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33683 Change subject: src/southbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... src/southbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/cimx/sb800/smbus_spd.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/spi.c M src/southbridge/amd/sb800/sm.c M src/southbridge/intel/lynxpoint/me_9.x.c 8 files changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33683/1 diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 46eca33..92bb5c1 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -20,7 +20,7 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "hudson.h" #include "smbus.c" diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index a6881bb..a574072 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -15,7 +15,7 @@ #include <device/pci_def.h> #include <device/device.h> -#include <stdlib.h> +#include <stddef.h> #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ /* warning: Porting.h includes an open #pragma pack(1) */ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index ffda0a8..d17f99f 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi_flash.h> @@ -21,6 +20,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <stddef.h> #include "SBPLATFORM.h" #include <vendorcode/amd/cimx/sb800/ECfan.h> diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 0387567..0b4cee7 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -20,7 +20,7 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "hudson.h" #include "smbus.c" diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6631682..535e5e4 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "sb700.h" #include "smbus.h" diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index ee031e9..4c0cc68 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi-generic.h> @@ -23,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <stddef.h> #define AMD_SB_SPI_TX_LEN 8 diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 1d2daed8..e1cf05c 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "sb800.h" #include "smbus.c" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 09eeff2..1b77aff 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -34,6 +34,7 @@ #include <delay.h> #include <elog.h> #include <halt.h> +#include <stdlib.h> #include "me.h" #include "pch.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c Gerrit-Change-Number: 33683 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified ...
by Frans Hendriks (Code Review) 28 Oct '19

28 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30811 Change subject: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot. ...................................................................... lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot. Before images are loaded from cbfs it needs to be measured and/or verified. prog_locate_hook() is added and can be used to start measured/verified boot. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG-1701 Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/include/program_loading.h M src/lib/prog_loaders.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30811/1 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 468f0b3..a382daf 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -3,6 +3,7 @@ * * Copyright 2015 Google Inc. * Copyright (C) 2014 Imagination Technologies + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -136,6 +137,7 @@ /* Locate the identified program to run. Return 0 on success. < 0 on error. */ int prog_locate(struct prog *prog); +int prog_locate_hook(struct prog *prog); /* Run the program described by prog. */ void prog_run(struct prog *prog); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index b763417..4fa9a03 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,9 @@ { struct cbfsf file; + if (prog_locate_hook(prog)) + return -1; + cbfs_prepare_program_locate(); if (cbfs_boot_locate(&file, prog_name(prog), NULL)) @@ -74,6 +78,7 @@ halt(); } +int __weak prog_locate_hook(struct prog *prog) {return 0; } void __weak stage_cache_add(int stage_id, const struct prog *stage) {} void __weak stage_cache_load_stage(int stage_id, -- To view, visit https://review.coreboot.org/c/coreboot/+/30811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Gerrit-Change-Number: 30811 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

9 45

Change in ...coreboot[master]: src/{device,drivers}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 27 Oct '19

27 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33681 Change subject: src/{device,drivers}: Use 'include <stdlib.h>' when appropriate ...................................................................... src/{device,drivers}: Use 'include <stdlib.h>' when appropriate Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/device_util.c M src/device/oprom/realmode/x86.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/smmstore/store.c M src/drivers/spi/flashconsole.c M src/drivers/spi/spi-generic.c M src/drivers/spi/spi_flash.c 8 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33681/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 47df305..fdb78fa 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -23,6 +23,7 @@ #include <device/path.h> #include <device/pci_def.h> #include <device/resource.h> +#include <stdlib.h> #include <string.h> /** diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index a7631a1..e002c47 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -28,6 +28,7 @@ #include <lib/jpeg.h> #include <pc80/i8259.h> #include <pc80/i8254.h> +#include <stdlib.h> #include <string.h> #include <vbe.h> diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 19c8f6b..54d1f86 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -40,6 +40,8 @@ #include <endian.h> #include <timer.h> #include <security/tpm/tis.h> +#include <stdlib.h> + #include "tpm.h" #define CR50_MAX_BUFSIZE 63 diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 4456567..e4fc9e1 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -22,6 +22,8 @@ #include <endian.h> #include <lib.h> #include <security/tpm/tis.h> +#include <stddef.h> +#include <stdlib.h> #include <timer.h> #define RECV_TIMEOUT (1 * 1000) /* 1 second */ diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 833407d..377eebe 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -20,6 +20,8 @@ #include <commonlib/region.h> #include <console/console.h> #include <smmstore.h> +#include <stddef.h> +#include <stdlib.h> /* * The region format is still not finalized, but so far it looks like this: diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 3109012..b6351e3 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -19,6 +19,8 @@ #include <fmap.h> #include <console/console.h> #include <console/flash.h> +#include <stddef.h> +#include <stdlib.h> #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 84a42d1..d4e17fc 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -16,6 +16,8 @@ #include <assert.h> #include <spi-generic.h> +#include <stddef.h> +#include <stdlib.h> #include <string.h> int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index a81306e..5afb2f7 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -12,7 +12,7 @@ #include <boot_device.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Gerrit-Change-Number: 33681 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019