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Change in coreboot[master]: arch/x86: Drop some HAVE_SMI_HANDLER guards
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34158 ) Change subject: arch/x86: Drop some HAVE_SMI_HANDLER guards ...................................................................... arch/x86: Drop some HAVE_SMI_HANDLER guards Change-Id: I4f7196febd091325eddceb77870acd40dbe332f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc 7 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34158/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 93a8bbb..7e84e41 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -56,7 +56,7 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += smi_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -89,7 +89,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878..230640a 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -50,7 +50,7 @@ bootblock-y += southbridge.c bootblock-y += nb_util.c bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +bootblock-y += smi_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -68,7 +68,7 @@ romstage-y += southbridge.c romstage-y += nb_util.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += smi_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -105,7 +105,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index cfd8149..1f12db7 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -67,7 +67,7 @@ ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 1aba88b..d957778 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += gpio.c ramstage-y += iou_complto.c ramstage-y += smmrelocate.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c ramstage-y += vtd.c smm-y += pmutil.c smm-y += smihandler.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index cd0a1d5..5603a20 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -32,7 +32,8 @@ ramstage-y += imc.c smm-y += smihandler.c smi_util.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-y += smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c8949b0..ac198aa 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -56,7 +56,7 @@ ramstage-y += sd.c ramstage-y += sm.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..8be9234 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -38,10 +38,11 @@ ramstage-y += rcba.c ramstage-y += me_status.c ramstage-y += acpi.c +ramstage-y += pmutil.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-y += smihandler.c me_9.x.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7196febd091325eddceb77870acd40dbe332f9 Gerrit-Change-Number: 34158 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31361 to review the following change. Change subject: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs ...................................................................... [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise CAR_GLOBALs may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all. Does not fix family14. Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/gcccar.inc M src/vendorcode/amd/agesa/f14/gcccar.inc M src/vendorcode/amd/agesa/f15tn/gcccar.inc M src/vendorcode/amd/agesa/f16kb/gcccar.inc 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31361/1 diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index b13e02a..e96c7f7 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1767,6 +1767,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index c818d97..26745c9 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1131,6 +1131,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR -- To view, visit https://review.coreboot.org/c/coreboot/+/31361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Gerrit-Change-Number: 31361 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34229 ) Change subject: [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE ...................................................................... [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE Change-Id: Ib712fa2c10931da90062bd853318079d5c144f48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/x86/Kconfig M src/include/cpu/x86/tsc.h M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/skylake/Kconfig 21 files changed, 4 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34229/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 2b8a8c7..af6605e 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -25,7 +25,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI - select TSC_SYNC_LFENCE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 98be6f6..eff4e18 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -5,7 +5,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SSE2 - select TSC_SYNC_LFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 099f54c..d760cf9 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -24,7 +24,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI - select TSC_SYNC_LFENCE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 0aab0a2..2627265 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -31,7 +31,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 84a2241..127e8ce 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -16,7 +16,6 @@ select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 2399c41..f1033fa 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2d6a387..8333e1d 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -9,7 +9,6 @@ select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 6c65907..8c9c5a1 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,7 +15,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_FIXED_XIP_ROM_SIZE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 4ed1119..6117480 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -15,7 +15,6 @@ select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 49f4302..a4c3ce2 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -8,7 +8,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index b31b01d..3724cc1 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -8,7 +8,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0bf2f0d..dd7c8d9 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -30,22 +30,6 @@ help Expose monotonic time using the TSC. -config TSC_SYNC_LFENCE - bool - default n - help - The CPU driver should select this if the CPU needs - to execute an lfence instruction in order to synchronize - rdtsc. This is true for all modern AMD CPUs. - -config TSC_SYNC_MFENCE - bool - default n - help - The CPU driver should select this if the CPU needs - to execute an mfence instruction in order to synchronize - rdtsc. This is true for all modern Intel CPUs. - config NO_FIXED_XIP_ROM_SIZE bool default n diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 23b74b2..8b7807b 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -3,10 +3,12 @@ #include <stdint.h> -#if CONFIG(TSC_SYNC_MFENCE) +#if CONFIG(CPU_INTEL_COMMON) #define TSC_SYNC "mfence\n" -#elif CONFIG(TSC_SYNC_LFENCE) +#elif CONFIG(DRIVERS_AMD_PI) || CONFIG(CPU_AMD_MODEL_10XXX) #define TSC_SYNC "lfence\n" +#elif CONFIG(TSC_MONOTONIC_TIMER) +#error "Undefined rdtsc() fence" #else #define TSC_SYNC #endif diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d654e94..6f46706 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,7 +35,6 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME - select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 465df60..622fad9 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME - select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 46ef898..29be910 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -28,7 +28,6 @@ select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d2a776..bf8133b 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -37,7 +37,6 @@ select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6bec847..663dbdc 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -28,7 +28,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_SYNC_MFENCE select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3bf608e..d9b86b9 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -53,7 +53,6 @@ select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 38777c5..820b396 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3d7a530..94b6585 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -75,7 +75,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE config CPU_INTEL_NUM_FIT_ENTRIES int -- To view, visit https://review.coreboot.org/c/coreboot/+/34229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib712fa2c10931da90062bd853318079d5c144f48 Gerrit-Change-Number: 34229 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] arch/x86: Use udelay() from monotonic timer
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34204 ) Change subject: [WIP] arch/x86: Use udelay() from monotonic timer ...................................................................... [WIP] arch/x86: Use udelay() from monotonic timer Change-Id: I2e768346b21758a386064346aff2ee8592a8e991 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/cpu/amd/agesa/Kconfig M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/cpu/amd/pi/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/via/nano/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/apic_timer.c M src/cpu/x86/tsc/Makefile.inc M src/cpu/x86/tsc/delay_tsc.c M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 35 files changed, 15 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34204/1 diff --git a/src/Kconfig b/src/Kconfig index ec0f35b..4a879e3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -514,7 +514,7 @@ config GENERIC_UDELAY bool depends on HAVE_MONOTONIC_TIMER - default y if !ARCH_X86 + default y help The board/chipset uses a generic udelay function utilizing the monotonic timer. diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 4c5463c..2b8a8c7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,7 +26,6 @@ select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE - select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index df65499..98be6f6 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SSE2 select TSC_SYNC_LFENCE - select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 10fd9f5..1923b08 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -88,7 +88,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)){ + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 2cbeab8..b4719a3 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -94,7 +94,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)) { + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 3769319..761c716 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -99,7 +99,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)) { + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index a902089..099f54c 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -25,7 +25,6 @@ select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE - select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 8649777..0aab0a2 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -28,7 +28,6 @@ select SMP select MMX select SSE2 - select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select PARALLEL_CPU_INIT diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d8d8b97..84a2241 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -13,7 +13,6 @@ select SMP select MMX select SSE2 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 0c74c69..cdf7991 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index dbfda01..2f22bed 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index f098526..6c65907 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -11,7 +11,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 72f04da..4ed1119 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,6 @@ select SMP select MMX select SSE2 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 29ef306..c06922b 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index df67f51..3b58463 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_TSC select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index a2ebeb2..e4dcba3 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -8,7 +8,6 @@ select CPU_INTEL_MODEL_F2X select MMX select SSE - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index d586125..9385684 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,7 +20,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP - select UDELAY_TSC select TSC_MONOTONIC_TIMER select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index aeb81ac..ad1f612 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -25,7 +25,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select UDELAY_TSC select TSC_MONOTONIC_TIMER select MMX select SSE2 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 24dc1f4..0bf2f0d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -17,26 +17,16 @@ Allow APs to do other work after initialization instead of going to sleep. -config UDELAY_LAPIC - bool - default n - config LAPIC_MONOTONIC_TIMER def_bool n - depends on UDELAY_LAPIC help Expose monotonic time using the local APIC. config UDELAY_LAPIC_FIXED_FSB int -config UDELAY_TSC - bool - default n - config TSC_MONOTONIC_TIMER def_bool n - depends on UDELAY_TSC help Expose monotonic time using the TSC. diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..058e25b 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,9 +1,9 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S -romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +romstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c +ramstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c +postcar-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 2e0583b..639a89a 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -22,6 +22,7 @@ #include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <timer.h> void init_timer(void) { @@ -38,33 +39,6 @@ set_timer_fsb(); } -void udelay(u32 usecs) -{ - u32 start, value, ticks, timer_fsb; - - if (!thread_yield_microseconds(usecs)) - return; - - timer_fsb = get_timer_fsb(); - if (!timer_fsb || (lapic_read(LAPIC_LVTT) & - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) { - init_timer(); - timer_fsb = get_timer_fsb(); - } - - /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz - */ - ticks = usecs * timer_fsb; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while ((start - value) < ticks); -} - -#if CONFIG(LAPIC_MONOTONIC_TIMER) -#include <timer.h> - static struct monotonic_counter { int initialized; struct mono_time time; @@ -108,4 +82,3 @@ /* Save result. */ *mt = mono_counter->time; } -#endif diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..592acb3 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ -bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c -ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c -smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c +bootblock-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +ramstage-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +romstage-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +verstage-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +postcar-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c +smm-$(CONFIG_TSC_MONOTONIC_TIMER) += delay_tsc.c diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 515919a..7789c7a 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -16,6 +16,7 @@ #include <smp/spinlock.h> #include <delay.h> #include <thread.h> +#include <timer.h> static unsigned long clocks_per_usec CAR_GLOBAL; @@ -31,28 +32,6 @@ return car_get_var(clocks_per_usec); } -void udelay(unsigned int us) -{ - unsigned long long start; - unsigned long long current; - unsigned long long clocks; - - if (!thread_yield_microseconds(us)) - return; - - start = rdtscll(); - clocks = us; - clocks *= get_clocks_per_usec(); - current = rdtscll(); - while ((current - start) < clocks) { - cpu_relax(); - current = rdtscll(); - } -} - -#if CONFIG(TSC_MONOTONIC_TIMER) -#include <timer.h> - static struct monotonic_counter { int initialized; struct mono_time time; @@ -94,4 +73,3 @@ /* Save result. */ *mt = mono_counter->time; } -#endif diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 78b89e3..465df60 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -36,7 +36,6 @@ select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB - select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 36b3b82..04cfef1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -98,7 +98,6 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE - select UDELAY_TSC select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 251f4fb..46ef898 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -29,7 +29,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index a33ac2f..5d2a776 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -38,7 +38,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 4b59aaa..6bec847 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -29,7 +29,6 @@ select SPI_FLASH select SSE2 select TSC_SYNC_MFENCE - select UDELAY_TSC select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cc502f9..4750c6b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,7 +103,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index bee6e88..3bf608e 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -54,7 +54,6 @@ select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b0da459..38777c5 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -37,7 +37,6 @@ select SPI_FLASH select SSE2 select TSC_SYNC_MFENCE - select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 8e301df..38c7941 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -18,7 +18,6 @@ select PARALLEL_MP select SMP select IOAPIC - select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index ad80abc..b9dce1e 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -56,7 +56,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index bb73780..ee2e791 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -34,7 +34,6 @@ select SOC_SETS_MSRS select SPI_FLASH select UART_OVERRIDE_REFCLK - select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 04c8bd9..3d7a530 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -76,7 +76,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE - select UDELAY_TSC config CPU_INTEL_NUM_FIT_ENTRIES int -- To view, visit https://review.coreboot.org/c/coreboot/+/34204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e768346b21758a386064346aff2ee8592a8e991 Gerrit-Change-Number: 34204 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: soc/intel: Refactor em64t100 SMI handlers
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34841 ) Change subject: soc/intel: Refactor em64t100 SMI handlers ...................................................................... soc/intel: Refactor em64t100 SMI handlers Change-Id: I739940f9de97ad0392f9e7765d038ef6bf97b818 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/smm/Makefile.inc A src/cpu/intel/smm/em64t100.c M src/cpu/intel/smm/smm_reloc.c M src/include/cpu/intel/em64t100_save_state.h M src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/fsp_baytrail/cpu.c 11 files changed, 101 insertions(+), 248 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/34841/1 diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc index a49b796..97fedc9 100644 --- a/src/cpu/intel/smm/Makefile.inc +++ b/src/cpu/intel/smm/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += em64t100.c diff --git a/src/cpu/intel/smm/em64t100.c b/src/cpu/intel/smm/em64t100.c new file mode 100644 index 0000000..dcd0c0e --- /dev/null +++ b/src/cpu/intel/smm/em64t100.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> + +static void std_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + fill_in_smrr(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); +} + +static void std_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + em64t100_smm_state_save_area_t *smm_state; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d SMBASE=0x%08x\n", cpu, + (u32)staggered_smbase); + + /* Make appropriate changes to the save state map. */ + smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; + + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +void select_mp_ops_em64t100(struct mp_ops *mp_ops) +{ + mp_ops->get_smm_info = std_smm_info; + mp_ops->relocation_handler = std_relocation_handler; +} diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c index 860c095..78222c0 100644 --- a/src/cpu/intel/smm/smm_reloc.c +++ b/src/cpu/intel/smm/smm_reloc.c @@ -11,6 +11,27 @@ * GNU General Public License for more details. */ +#include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> struct smm_relocation_params smm_reloc_params; + +void fill_in_smrr(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((4 * KiB) - 1); + + smm_region(&tseg_base, &tseg_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index f76fa4b..f0bdd32 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -103,4 +103,7 @@ u64 cr0; } __packed em64t100_smm_state_save_area_t; +struct mp_ops; +void select_mp_ops_em64t100(struct mp_ops *mp_ops); + #endif diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 9b6473b..cbcdb56 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -37,6 +37,8 @@ extern struct smm_relocation_params smm_reloc_params; +void fill_in_smrr(struct smm_relocation_params *params); + #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e834142..834896e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -134,13 +134,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; -}; - -static struct smm_relocation_attrs relo_attrs; /* * Do essential initialization tasks before APs can be fired up. @@ -204,46 +197,6 @@ } #endif -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - uintptr_t smm_base; - size_t smm_size; - uintptr_t handler_base; - size_t handler_size; - - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); - - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - - relo_attrs.smbase = smm_base; - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - - *perm_smbase = handler_base; - *perm_smsize = handler_size; - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t smrr; - em64t100_smm_state_save_area_t *smm_state; - /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} /* * CPU initialization recipe * @@ -260,18 +213,19 @@ mp_run_on_all_cpus(sgx_configure, NULL, 2000); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = smm_southbridge_clear_state, - .relocation_handler = relocation_handler, .post_mp_init = post_mp_init, }; void soc_init_cpus(struct bus *cpu_bus) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + /* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 0f6969c..7f3e00d 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,7 +83,6 @@ .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ @@ -132,35 +131,6 @@ return pattrs->num_cpus; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static void get_microcode_info(const void **microcode, int *parallel) { const struct pattrs *pattrs = pattrs_get(); @@ -180,28 +150,12 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southcluster_smm_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, .post_mp_init = southcluster_smm_enable_smi, }; @@ -209,6 +163,9 @@ { struct bus *cpu_bus = dev->link_list; + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index abf6a99..75bc45f 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -91,7 +91,6 @@ .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ @@ -140,35 +139,6 @@ return pattrs->num_cpus; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static void get_microcode_info(const void **microcode, int *parallel) { const struct pattrs *pattrs = pattrs_get(); @@ -194,28 +164,12 @@ intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southcluster_smm_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, .post_mp_init = southcluster_smm_enable_smi, }; @@ -226,6 +180,9 @@ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index bda6d1d..684b0d7 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -35,8 +35,6 @@ #include <soc/smm.h> #include <soc/soc_util.h> -static struct smm_relocation_attrs relo_attrs; - static void dnv_configure_mca(void) { msr_t msr; @@ -102,53 +100,6 @@ .id_table = cpu_table, }; -/* - * MP and SMM loading initialization. - */ - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t smrr; - em64t100_smm_state_save_area_t *smm_state; - (void)cpu; - - /* Set up SMRR. */ - smrr.lo = relo_attrs.smrr_base; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_BASE, smrr); - smrr.lo = relo_attrs.smrr_mask; - smrr.hi = 0; - wrmsr(IA32_SMRR_PHYS_MASK, smrr); - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - uintptr_t smm_base; - size_t smm_size; - uintptr_t handler_base; - size_t handler_size; - - /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); - - /* Initialize global tracking state. */ - smm_region(&smm_base, &smm_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - - relo_attrs.smbase = smm_base; - relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - - *perm_smbase = handler_base; - *perm_smsize = handler_size; - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static int detect_num_cpus_via_cpuid(void) { register int ecx = 0; @@ -232,6 +183,7 @@ ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } + /* * Do essential initialization tasks before APs can be fired up * @@ -264,17 +216,18 @@ * the microcode on all cores before releasing them from reset. That means that * the BSP and all APs will come up with the same microcode revision. */ -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .pre_mp_smm_init = southcluster_smm_clear_state, - .relocation_handler = relocation_handler, .post_mp_init = post_mp_init, }; void denverton_init_cpus(struct device *dev) { + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index a020891..9de020b 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -18,12 +18,6 @@ #ifndef _DENVERTON_NS_SMM_H_ #define _DENVERTON_NS_SMM_H_ -struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; -}; - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 8f925e8..8eb71c6 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -98,35 +98,6 @@ return pattrs->num_cpus; } -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - static void get_microcode_info(const void **microcode, int *parallel) { const struct pattrs *pattrs = pattrs_get(); @@ -135,33 +106,17 @@ *parallel = 1; } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static void enable_smis(void) { if (CONFIG(HAVE_SMI_HANDLER)) southcluster_smm_enable_smi(); } -static const struct mp_ops mp_ops = { +static struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southcluster_smm_clear_state, - .relocation_handler = relocation_handler, .post_mp_init = enable_smis, }; @@ -169,6 +124,9 @@ { struct bus *cpu_bus = dev->link_list; + if (CONFIG(HAVE_SMI_HANDLER)) + select_mp_ops_em64t100(&mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739940f9de97ad0392f9e7765d038ef6bf97b818 Gerrit-Change-Number: 34841 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 18

Change in coreboot[master]: cpu,soc/intel/smm: Define inlined smm_lock()
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34875 ) Change subject: cpu,soc/intel/smm: Define inlined smm_lock() ...................................................................... cpu,soc/intel/smm: Define inlined smm_lock() Change-Id: I66983b771feb5c05744255b9000c742c4c0e5025 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/smmrelocate.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smi.c 30 files changed, 101 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34875/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 1eb6f68..e2f468d 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -332,14 +332,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index b0c2c1a..b32af6f 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -34,11 +34,6 @@ #define SMRR_SUPPORTED (1 << 11) -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) @@ -141,17 +136,6 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); } -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index cb196fc..12247ab 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -23,11 +23,24 @@ } __packed; /* These helpers are for performing SMM relocation. */ -void northbridge_write_smram(u8 smram); - -void smm_lock(void); void smm_relocate(void); +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +static inline void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + nb_smram_lock(); +} + /* The initialization of the southbridge is split into 2 components. One is * for clearing the state in the SMM registers. The other is for enabling * SMIs. They are split so that other work between the 2 actions. */ diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 7033f89..e6ccdb6 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" @@ -35,12 +36,10 @@ return (void *)tolm; } -void northbridge_write_smram(u8 smram); - -void northbridge_write_smram(u8 smram) +void nb_smram_lock(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); - pci_write_config8(mch, SMRAMC, smram); + pci_write_config8(mch, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 7eb07b8..207b120 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -124,6 +124,12 @@ return (void *) top_of_ram; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, D0F0_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 384d98a..39f98da 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -219,16 +219,6 @@ return NULL; } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, D0F0_SMRAM, smram); -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 59508be..a81a4bb 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -41,6 +41,12 @@ return (void *)smm_region_start(); } +void nb_smram_lock(void) +{ + pci_devfn_t dev = PCI_DEV(0,0,0); + pci_write_config8(dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = smm_region_start(); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 3d3457d..93b307c 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -90,6 +90,12 @@ return ggc2uma[gms] << 10; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dd4e8ac..73de993 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -154,16 +154,6 @@ return NULL; } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, SMRAM, smram); -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 8c19852..ea99da7 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -21,7 +21,8 @@ #include <cpu/intel/smm_reloc.h> -void northbridge_write_smram(u8 smram) +void nb_smram_lock(void) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_devfn_t qpd_d0f1 = PCI_DEV(QUICKPATH_BUS, 0, 1); + pci_write_config8(qpd_d0f1, QPD0F1_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2400c59..fd02f77 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -140,6 +140,12 @@ } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 34cb583..b8dbaa2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -140,16 +140,6 @@ add_fixed_resources(dev, index); } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, SMRAM, smram); -} - static void mch_domain_set_resources(struct device *dev) { struct resource *res; diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 41330f2..368456b 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -48,6 +48,12 @@ return CONFIG_SMM_TSEG_SIZE; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 58f4a68..a5872b6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -444,11 +444,6 @@ MCHBAR32(0x5500) = 0x00100001; } -void northbridge_write_smram(u8 smram) -{ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); -} - static struct pci_operations intel_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 42786bb..b802973 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -135,6 +135,12 @@ return (void *) top_of_ram; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, D0F0_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ee70527..8b5b9e0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -171,16 +171,6 @@ return NULL; } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, D0F0_SMRAM, smram); -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f4a9d0e..062963d 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -56,3 +56,8 @@ *start = tseg; *size = bgsm - tseg; } + +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 21c534a..13d591d 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -295,14 +295,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 276b9a3..15ca276 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -35,6 +35,11 @@ *size = sa_get_tseg_size(); } +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 493d003..11fe760 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -254,15 +254,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 0d41f25..94b1daf 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -33,6 +33,11 @@ *size = sa_get_tseg_size(); } +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 65505c4..bb77375 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -253,15 +253,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 9d3f377..e4f4487 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -36,6 +36,11 @@ *size = sa_get_tseg_size(); } +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..479abf7 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -253,15 +253,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index ac53ae1..678d5d7 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -37,9 +37,6 @@ void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); #endif - -void aseg_smm_lock(void); - #endif #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 94d8e14..422ed57 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -304,7 +304,7 @@ * userspace applications to deceive us: */ if (CONFIG(HAVE_SMI_HANDLER)) - aseg_smm_lock(); + smm_lock(); } static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 521b98d..d85cd63 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -27,16 +27,6 @@ #include <string.h> #include "i82801dx.h" - -void northbridge_write_smram(u8 smram); - -/* For intel/e7505. */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -343,16 +333,6 @@ restore_default_smm_area(default_smm_area); } -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* The GDT or coreboot table is going to live here. But a long time diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 31eabb6..421a101 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -212,8 +212,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -void aseg_smm_lock(void); - #if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index ba2b028..cb79e96 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -431,7 +431,7 @@ * userspace applications to deceive us: */ if (CONFIG(HAVE_SMI_HANDLER) && CONFIG(SMM_ASEG)) - aseg_smm_lock(); + smm_lock(); } static void i82801ix_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 0a80dd2..c02e823 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -30,6 +30,7 @@ #include "i82801ix.h" /* I945/GM45 */ + #define SMRAM 0x9d #define D_OPEN (1 << 6) #define D_CLS (1 << 5) @@ -126,6 +127,24 @@ static int smm_handler_copied = 0; +static void nb_smram_open(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); +} + +static void nb_smram_close(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, G_SMRAME | C_BASE_SEG); +} + +void nb_smram_lock(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -135,24 +154,20 @@ return; smm_handler_copied = 1; - /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); + nb_smram_open(); /* copy the real SMM handler */ memcpy((void *)0xa0000, _binary_smm_start, _binary_smm_end - _binary_smm_start); wbinvd(); } - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - G_SMRAME | C_BASE_SEG); + nb_smram_close(); } void smm_init(void) @@ -171,14 +186,3 @@ { restore_default_smm_area(default_smm_area); } - -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66983b771feb5c05744255b9000c742c4c0e5025 Gerrit-Change-Number: 34875 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma panel: Report used timings
by Nico Huber (Code Review) 31 Jul '20

31 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34472 ) Change subject: gma panel: Report used timings ...................................................................... gma panel: Report used timings Change-Id: If7a3b7ec755d85b9d570b8031ea4a2a31fe37514 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/72/34472/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index ba91254..bc0f7b8 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -141,7 +141,15 @@ if Delays (D) = 0 then Delays (D) := Default_EDP_Delays_US (D); Override := True; + + pragma Debug (Debug.Put ("PP: Using default ")); + else + pragma Debug (Debug.Put ("PP: Using preset ")); end if; + pragma Debug (Debug.Put (Delays_Enum'Image (D))); + pragma Debug (Debug.Put (" of ")); + pragma Debug (Debug.Put_Int32 (Int32 (Delays (D)))); + pragma Debug (Debug.Put_Line (" us.")); end loop; end Check_PP_Delays; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If7a3b7ec755d85b9d570b8031ea4a2a31fe37514 Gerrit-Change-Number: 34472 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma panel: Also wait for `power cycle delay active`
by Nico Huber (Code Review) 31 Jul '20

31 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34470 ) Change subject: gma panel: Also wait for `power cycle delay active` ...................................................................... gma panel: Also wait for `power cycle delay active` It's possible that the `power cycle progress` bits are only valid if no power-cycle delay is active. So let's check that bit, too. Also increase the timeouts to the theoretical maximum, including a pos- sibly ongoing sequence and the power-cycle delay. Change-Id: I536a094151c5cc5036c2d39a3d8d6e5826f198ac Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/70/34470/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index 968fbbe..8ccbbb9 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -1,5 +1,6 @@ -- -- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2019 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -305,8 +306,9 @@ Time.Delay_Until (Power_Up_Timer); Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, - Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK, - TOut_MS => 300); + Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK or + PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, + TOut_MS => 820 + 3_100 + 820); -- theoretical max: off + cycle + on Registers.Unset_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE); end Wait_On; @@ -327,8 +329,9 @@ end if; Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, - Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK, - TOut_MS => 600); + Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK or + PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, + TOut_MS => 820 + 3_100 + 820); -- theoretical max: on + cycle + off if Was_On then Power_Cycle_Timer := Time.US_From_Now (Delays_US (Power_Cycle_Delay)); end if; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I536a094151c5cc5036c2d39a3d8d6e5826f198ac Gerrit-Change-Number: 34470 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma panel: Add `Debug_Sts` flag to dump PP_STATUS register
by Nico Huber (Code Review) 31 Jul '20

31 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34473 ) Change subject: gma panel: Add `Debug_Sts` flag to dump PP_STATUS register ...................................................................... gma panel: Add `Debug_Sts` flag to dump PP_STATUS register Change-Id: I68955ee315ddd25a58606ac3827257b6c716342e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/73/34473/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index bc0f7b8..e8eb170 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -20,6 +20,8 @@ package body HW.GFX.GMA.Panel is + Debug_Sts : constant Boolean := True; + type Delays_Enum is (Power_Up_Delay, Power_Up_To_BL_On, @@ -252,6 +254,7 @@ procedure On (Wait : Boolean := True) is begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); Registers.Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON); if Wait then @@ -262,6 +265,7 @@ procedure Wait_On is begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, @@ -269,22 +273,32 @@ PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, TOut_MS => 820 + 3_100 + 820); -- theoretical max: off + cycle + on + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); + Registers.Unset_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE); + + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); end Wait_On; procedure Off is begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); Registers.Unset_Mask (Register => Panel_PP_Regs.CONTROL, Mask => PCH_PP_CONTROL_TARGET_ON or PCH_PP_CONTROL_VDD_OVERRIDE); + + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); + Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK or PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, TOut_MS => 820 + 3_100 + 820); -- theoretical max: on + cycle + off + + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); end Off; ---------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I68955ee315ddd25a58606ac3827257b6c716342e Gerrit-Change-Number: 34473 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable all C states in FSP
by Maulik V Vaghela (Code Review) 23 Jul '20

23 Jul '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32463 Change subject: soc/intel/cannonlake: Enable all C states in FSP ...................................................................... soc/intel/cannonlake: Enable all C states in FSP FSP will not enable all C-states by default when we use FSP to do MP initialization. We need to set UPD from coreboot to enable C-states in FSP. Change-Id: I845c61fd14f2f5de21288067eeb7c371710da249 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32463/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2b83275..7b28058 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -352,6 +352,9 @@ /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; + + /* Enable all Cx state in FSP */ + tconfig->Cx = 1; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I845c61fd14f2f5de21288067eeb7c371710da249 Gerrit-Change-Number: 32463 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019