Change in ...coreboot[master]: vboot: Turn vboot_logic_executed() into a static inline
by Julius Werner (Code Review) 28 May '20
by Julius Werner (Code Review) 28 May '20
28 May '20
Hello Aaron Durbin, Frans Hendriks, Philipp Deppenwiese,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32716
to review the following change.
Change subject: vboot: Turn vboot_logic_executed() into a static inline
......................................................................
vboot: Turn vboot_logic_executed() into a static inline
This patch moves vboot_logic_executed() (and its dependencies) into a
header and turns it into a static inline function. The function is used
to guard larger amounts of code in several places, so this should allow
us to safe some more space through compile-time elimination (and also
makes it easier to avoid undefined reference issues in some cases).
Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/security/vboot/misc.h
M src/security/vboot/vboot_loader.c
2 files changed, 58 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32716/1
diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h
index b4fae19..2a0523d 100644
--- a/src/security/vboot/misc.h
+++ b/src/security/vboot/misc.h
@@ -16,6 +16,8 @@
#ifndef __VBOOT_MISC_H__
#define __VBOOT_MISC_H__
+#include <assert.h>
+#include <arch/early_variables.h>
#include <security/vboot/vboot_common.h>
struct vb2_context;
@@ -66,13 +68,63 @@
void vboot_fill_handoff(void);
/*
- * Source: security/vboot/vboot_loader.c
- */
-int vboot_logic_executed(void);
-
-/*
* Source: security/vboot/bootmode.c
*/
void vboot_save_recovery_reason_vbnv(void);
+/*
+ * The stage loading code is compiled and entered from multiple stages. The
+ * helper functions below attempt to provide more clarity on when certain
+ * code should be called. They are implemented inline for better compile-time
+ * code elimination.
+ */
+
+static inline int verification_should_run(void)
+{
+ if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
+ return ENV_VERSTAGE;
+ else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
+ return ENV_ROMSTAGE;
+ else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))
+ return ENV_BOOTBLOCK;
+ else
+ dead_code();
+}
+
+static inline int verstage_should_load(void)
+{
+ if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
+ return ENV_BOOTBLOCK;
+ else
+ return 0;
+}
+
+/* Only for use by functions in this header, do not access directly! */
+extern int vboot_executed;
+
+static inline int vboot_logic_executed(void)
+{
+ /* If we are in the stage that runs verification, or in the stage that
+ both loads the verstage and is returned to from it afterwards, we
+ need to check a global to see if verfication has run. */
+ if (verification_should_run() ||
+ (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE)))
+ return car_get_var(vboot_executed);
+
+ if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) {
+ /* All other stages are "after the bootblock" */
+ return !ENV_BOOTBLOCK;
+ } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) {
+ /* Post-RAM stages are "after the romstage" */
+#ifdef __PRE_RAM__
+ return 0;
+#else
+ return 1;
+#endif
+ } else {
+ dead_code();
+ }
+}
+
+
#endif /* __VBOOT_MISC_H__ */
diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c
index 3bbb3da..1350307 100644
--- a/src/security/vboot/vboot_loader.c
+++ b/src/security/vboot/vboot_loader.c
@@ -36,55 +36,7 @@
CONFIG(VBOOT_SEPARATE_VERSTAGE),
"return from verstage only makes sense for separate verstages");
-/* The stage loading code is compiled and entered from multiple stages. The
- * helper functions below attempt to provide more clarity on when certain
- * code should be called. */
-
-static int verification_should_run(void)
-{
- if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
- return ENV_VERSTAGE;
- else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
- return ENV_ROMSTAGE;
- else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))
- return ENV_BOOTBLOCK;
- else
- die("impossible!");
-}
-
-static int verstage_should_load(void)
-{
- if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
- return ENV_BOOTBLOCK;
- else
- return 0;
-}
-
-static int vboot_executed CAR_GLOBAL;
-
-int vboot_logic_executed(void)
-{
- /* If we are in the stage that runs verification, or in the stage that
- both loads the verstage and is returned to from it afterwards, we
- need to check a global to see if verfication has run. */
- if (verification_should_run() ||
- (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE)))
- return car_get_var(vboot_executed);
-
- if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) {
- /* All other stages are "after the bootblock" */
- return !ENV_BOOTBLOCK;
- } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) {
- /* Post-RAM stages are "after the romstage" */
-#ifdef __PRE_RAM__
- return 0;
-#else
- return 1;
-#endif
- } else {
- die("impossible!");
- }
-}
+int vboot_executed CAR_GLOBAL;
static void vboot_prepare(void)
{
--
To view, visit https://review.coreboot.org/c/coreboot/+/32716
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324
Gerrit-Change-Number: 32716
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-MessageType: newchange
5
15
25 May '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34786 )
Change subject: mb/toshiba: Add A300-1ME
......................................................................
mb/toshiba: Add A300-1ME
Mainboard real name (to find schematics) is Inventec Potomac 10G.
Vendor firmware is InsydeH20 EFI Rev. 3.5 and shows postcodes on LPC.
This thing is a PM45/ICH9M notebook with a WPCE775 EC. It usually boots
from LPC via EC, but also has space for another flash chip, directly
attached to SPI.
Working:
- usbdebug with FT2232H (left side, the non-eSATA USB port)
- postcodes via LPC (debug card on WLAN card slot) with vendor firmware
coreboot may not be printing any postcodes on this platform, so this
may explain why postcodes don't show with coreboot. But the hw works.
- running coreboot off the ICH SPI flash chip
- fan runs at a high speed by default (no risk of overheating)
Not working:
- raminit: dies with: "DDR2 not supported at this time."
- some watchdog trips after a few seconds (likely EC watchdog)
(though coreboot currently dies first)
Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A src/mainboard/toshiba/Kconfig
A src/mainboard/toshiba/Kconfig.name
A src/mainboard/toshiba/a300-1me/Kconfig
A src/mainboard/toshiba/a300-1me/Kconfig.name
A src/mainboard/toshiba/a300-1me/Makefile.inc
A src/mainboard/toshiba/a300-1me/acpi/battery.asl
A src/mainboard/toshiba/a300-1me/acpi/ec.asl
A src/mainboard/toshiba/a300-1me/acpi/ec2.asl
A src/mainboard/toshiba/a300-1me/acpi/gpe.asl
A src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl
A src/mainboard/toshiba/a300-1me/acpi/mainboard.asl
A src/mainboard/toshiba/a300-1me/acpi/platform.asl
A src/mainboard/toshiba/a300-1me/acpi/superio.asl
A src/mainboard/toshiba/a300-1me/acpi/thermal.asl
A src/mainboard/toshiba/a300-1me/acpi_tables.c
A src/mainboard/toshiba/a300-1me/blc.c
A src/mainboard/toshiba/a300-1me/board_info.txt
A src/mainboard/toshiba/a300-1me/cmos.layout
A src/mainboard/toshiba/a300-1me/cstates.c
A src/mainboard/toshiba/a300-1me/devicetree.cb
A src/mainboard/toshiba/a300-1me/dsdt.asl
A src/mainboard/toshiba/a300-1me/fadt.c
A src/mainboard/toshiba/a300-1me/gpio.c
A src/mainboard/toshiba/a300-1me/hda_verb.c
A src/mainboard/toshiba/a300-1me/mainboard.c
A src/mainboard/toshiba/a300-1me/romstage.c
A src/mainboard/toshiba/a300-1me/smistuff.c
27 files changed, 1,899 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34786/1
diff --git a/src/mainboard/toshiba/Kconfig b/src/mainboard/toshiba/Kconfig
new file mode 100644
index 0000000..609b15d
--- /dev/null
+++ b/src/mainboard/toshiba/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_TOSHIBA
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/toshiba/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/toshiba/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "TOSHIBA"
+
+endif # VENDOR_TOSHIBA
diff --git a/src/mainboard/toshiba/Kconfig.name b/src/mainboard/toshiba/Kconfig.name
new file mode 100644
index 0000000..47dbb59
--- /dev/null
+++ b/src/mainboard/toshiba/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_TOSHIBA
+ bool "TOSHIBA"
diff --git a/src/mainboard/toshiba/a300-1me/Kconfig b/src/mainboard/toshiba/a300-1me/Kconfig
new file mode 100644
index 0000000..8099b7b
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/Kconfig
@@ -0,0 +1,33 @@
+if BOARD_TOSHIBA_A300_1ME
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_INTEL_SOCKET_BGA956
+ select NORTHBRIDGE_INTEL_GM45
+ select SOUTHBRIDGE_INTEL_I82801IX
+ select BOARD_ROMSIZE_KB_2048 # FIXME: that's the size of my flash chip
+ #select DRIVERS_GENERIC_IOAPIC
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select EC_ACPI
+ select HAVE_OPTION_TABLE
+ select INTEL_INT15
+
+config MAINBOARD_DIR
+ string
+ default toshiba/a300-1me
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A300-1ME"
+
+config MAX_CPUS
+ int
+ default 2
+
+config CBFS_SIZE
+ hex
+ default ROM_SIZE
+
+endif # BOARD_TOSHIBA_A300_1ME
diff --git a/src/mainboard/toshiba/a300-1me/Kconfig.name b/src/mainboard/toshiba/a300-1me/Kconfig.name
new file mode 100644
index 0000000..8bc568d
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_TOSHIBA_A300_1ME
+ bool "A300-1ME"
diff --git a/src/mainboard/toshiba/a300-1me/Makefile.inc b/src/mainboard/toshiba/a300-1me/Makefile.inc
new file mode 100644
index 0000000..21bbe39
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y = gpio.c
+
+ramstage-y += cstates.c
+ramstage-y += blc.c
diff --git a/src/mainboard/toshiba/a300-1me/acpi/battery.asl b/src/mainboard/toshiba/a300-1me/acpi/battery.asl
new file mode 100644
index 0000000..2f793d8
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/battery.asl
@@ -0,0 +1,226 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Name(\CBA1, 0x60)
+Name(\CBA2, 0x60)
+
+/* ACPI doesn't care if capacity is given in mWh or mAh,
+ but it has to be consistent */
+
+Device (BAT1)
+{
+ Name(_HID, EisaId("PNP0C0A"))
+ Name(_UID, 1)
+
+ Name(_PCL, Package(){ _SB })
+ Name(PSTA, 0x1f)
+
+ /* battery information */
+ Name(PBIF, Package() {
+ 0x01, // power unit
+ 0x01, // design capacity (mWh/mAh), updated by UPBI
+ 0x01, // last full charge capacity (mWh/mAh), updated by UPBI
+ 0x01, // battery technology: "rechargeable"
+ 0x01, // design voltage (mV), updated by UPBI
+ 0x0294, // design capacity of warning (mWh/mAh)
+ 0x014a, // design capacity of low (mWh/mAh)
+ 0x42, // battery capacity granularity between low and warning
+ 0x42, // battery capacity granularity between warning and full
+ "BAT1", // Name
+ "001 ", // Number
+ "LION", // Type
+ "JSE" // Vendor
+ })
+ /* battery status */
+ /* dummy values, filled in by UPBS */
+ Name(PBST, Package() {
+ 0x00, // battery state
+ // bit0: discharging
+ // bit1: charging
+ // bit2: critical energy state
+ 0x01, // battery present rate (mW/mA)
+ 0x01, // remaining capacity (mW/mA)
+ 0x01 // battery present voltage (mV)
+ })
+
+ /* Status */
+ Method(_STA, 0)
+ {
+ If(\_SB.PCI0.LPCB.EC0.ECON) {
+ If(\_SB.PCI0.LPCB.EC0.B1PR) {
+ If(\_SB.PCI0.LPCB.EC0.B1CH) {
+ Return(0x1f)
+ }
+ }
+ }
+ Return(0x0f)
+ }
+
+ /* Battery Info */
+ Method(_BIF, 0)
+ {
+ If(\_SB.PCI0.LPCB.EC0.ECON) {
+ Store (\_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1))
+ Store (\_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2))
+ Store (\_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4))
+ }
+
+ Return(PBIF)
+ }
+
+ /* Battery Status */
+ Method(_BST, 0)
+ {
+ If(\_SB.PCI0.LPCB.EC0.ECON) {
+ Store (\_SB.PCI0.LPCB.EC0.B1PW, Local0)
+ If (LGreaterEqual (Local0, 0x8000)) {
+ Subtract (0x10000, Local0, Local0)
+ }
+ Store (Local0, Index(PBST, 1))
+ Store (\_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3))
+
+ Store (\_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2))
+
+ If (\_SB.PCI0.LPCB.EC0.ACCH) {
+ If (\_SB.PCI0.LPCB.EC0.B1CH) {
+ If (\_SB.PCI0.LPCB.EC0.B1CG) {
+ Store (2, Index(PBST, 0))
+ }
+ }
+ } Else {
+ If (\_SB.PCI0.LPCB.EC0.B1LO) {
+ Store (5, Index(PBST, 0))
+ } Else {
+ Store (1, Index(PBST, 0))
+ }
+ }
+ }
+
+ Return(PBST)
+ }
+
+}
+
+Device (BAT2)
+{
+ Name(_HID, EisaId("PNP0C0A"))
+ Name(_UID, 2)
+
+ Name(_PCL, Package(){ _SB })
+ Name(PSTA, 0x1f)
+
+ /* battery information */
+ Name(PBIF, Package() {
+ 0x01, // power unit
+ 0x01, // design capacity (mWh/mAh), updated by UPBI
+ 0x01, // last full charge capacity (mWh/mAh), updated by UPBI
+ 0x01, // battery technology: "rechargeable"
+ 0x01, // design voltage (mV), updated by UPBI
+ 0x0294, // design capacity of warning (mWh/mAh)
+ 0x014a, // design capacity of low (mWh/mAh)
+ 0x42, // battery capacity granularity between low and warning
+ 0x42, // battery capacity granularity between warning and full
+ "BAT1", // Name
+ "002 ", // Number
+ "LION", // Type
+ "JSE" // Vendor
+ })
+ /* battery status */
+ /* dummy values, filled in by UPBS */
+ Name(PBST, Package() {
+ 0x00, // battery state
+ // bit0: discharging
+ // bit1: charging
+ // bit2: critical energy state
+ 0x01, // battery present rate (mW/mA)
+ 0x01, // remaining capacity (mW/mA)
+ 0x01 // battery present voltage (mV)
+ })
+
+ /* Status */
+ Method(_STA, 0)
+ {
+ If(\_SB.PCI0.LPCB.EC0.ECON) {
+ If(\_SB.PCI0.LPCB.EC0.B2PR) {
+ If(\_SB.PCI0.LPCB.EC0.B2CH) {
+ Return(0x1f)
+ }
+ }
+ }
+ Return(0x0f)
+ }
+
+ /* Battery Info */
+ Method(_BIF, 0)
+ {
+ If(\_SB.PCI0.LPCB.EC0.ECON) {
+ Store (\_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1))
+ Store (\_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2))
+ Store (\_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4))
+ }
+
+ Return(PBIF)
+ }
+
+ /* Battery Status */
+ Method(_BST, 0)
+ {
+ If(\_SB.PCI0.LPCB.EC0.ECON) {
+ Store (\_SB.PCI0.LPCB.EC0.B2PW, Local0)
+ If (LGreaterEqual (Local0, 0x8000)) {
+ Subtract (0x10000, Local0, Local0)
+ }
+ Store (Local0, Index(PBST, 1))
+ Store (\_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3))
+
+ Store (\_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2))
+
+ If (\_SB.PCI0.LPCB.EC0.ACCH) {
+ If (\_SB.PCI0.LPCB.EC0.B2CH) {
+ If (\_SB.PCI0.LPCB.EC0.B2CG) {
+ Store (2, Index(PBST, 0))
+ }
+ }
+ } Else {
+ If (\_SB.PCI0.LPCB.EC0.B2LO) {
+ Store (5, Index(PBST, 0))
+ } Else {
+ Store (1, Index(PBST, 0))
+ }
+ }
+ }
+
+ Return(PBST)
+ }
+
+}
+
+Device (ADP1)
+{
+ Name (_HID, "ACPI0003")
+ Method (_PSR, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.ACCH, PWRS)
+ Stall (0x02)
+ Return (PWRS)
+ }
+
+ Method (_PCL, 0)
+ {
+ Return (_SB)
+ }
+}
diff --git a/src/mainboard/toshiba/a300-1me/acpi/ec.asl b/src/mainboard/toshiba/a300-1me/acpi/ec.asl
new file mode 100644
index 0000000..48630b0
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/ec.asl
@@ -0,0 +1 @@
+// dummy
diff --git a/src/mainboard/toshiba/a300-1me/acpi/ec2.asl b/src/mainboard/toshiba/a300-1me/acpi/ec2.asl
new file mode 100644
index 0000000..aef4d32
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/ec2.asl
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+ Name (ECON, 0)
+ Name (QEVT, 0)
+
+ OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xb1),
+ CPWR, 1,
+ ACCH, 1, // AC connected (charger present)
+ B1PR, 1, // battery 1 present
+ B2PR, 1, // battery 2 present
+ B1CH, 1, // battery 1 charged
+ B2CH, 1, // battery 2 charged
+ Offset(0xb2),
+ B1CG, 1, // battery 1 charging
+ B2CG, 1, // battery 2 charging
+ B1LO, 1, // battery 1 low
+ B2LO, 1, // battery 2 low
+ Offset(0xb3),
+ B1DW, 16, // battery 1 design capacity
+ B1FW, 16, // battery 1 last full charge capacity
+ B1DV, 16, // battery 1 design voltage
+ B1PW, 16, // battery 1 present capacity
+ Offset(0xbd),
+ B1PV, 16, // battery 1 present voltage
+ Offset(0xc1),
+ B2DW, 16, // battery 2 design capacity
+ B2FW, 16, // battery 2 last full charge capacity
+ B2DV, 16, // battery 2 design voltage
+ B2PW, 16, // battery 2 present capacity
+ Offset(0xcb),
+ B2PV, 16, // battery 2 present voltage
+ Offset(0xcf),
+ FDDI, 1, // floppy on lpt indicator?
+ LIDC, 1, // LID switch
+ Offset(0xd0),
+ TCPU, 8, // T_CPU in deg Celcius
+ Offset(0xd6),
+ /* exact purpose of these three is guessed,
+ but it's something about cooling */
+ ALRL, 1, // active cooling low limit
+ ALRH, 1, // active cooling high limit
+ ALRC, 1, // active cooling clear
+ Offset(0xe8),
+ B1RW, 16, // battery 1 remaining capacity
+ B2RW, 16, // battery 2 remaining capacity
+ }
+
+ Method (_CRS, 0)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 1, 1)
+ IO (Decode16, 0x66, 0x66, 1, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000 for
+ // EC initialization before a driver is loaded
+
+ If (LEqual(Arg0, 0x03)) {
+ Store (Arg1, ECON)
+ }
+ }
+
+ // EC Query methods
+
+ Method (_Q11, 0)
+ {
+ Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug)
+ Notify(SLPB, 0x80)
+ }
+
+ Method (_Q30, 0)
+ {
+ Store("_Q30: AC In", Debug)
+ Notify(ADP1, 0x80) // Tell the Power Adapter
+ PNOT() // and the CPU and Battery
+ }
+
+ Method (_Q31, 0)
+ {
+ Store("_Q31: AC Out", Debug)
+ Notify(ADP1, 0x80) // Tell the Power Adapter
+ PNOT() // and the CPU and Battery
+ }
+
+ Method (_Q32, 0)
+ {
+ Store("_Q32: Bat1 In", Debug)
+ Notify(BAT1, 0x81)
+ }
+
+ Method (_Q33, 0)
+ {
+ Store("_Q33: Bat1 Out", Debug)
+ Notify(BAT1, 0x81)
+ }
+
+ Method (_Q34, 0)
+ {
+ Store("_Q34: Bat2 In", Debug)
+ Notify(BAT2, 0x81)
+ }
+
+ Method (_Q35, 0)
+ {
+ Store("_Q35: Bat2 Out", Debug)
+ Notify(BAT2, 0x81)
+ }
+
+ Method (_Q36, 0)
+ {
+ Store("_Q36: Bat1 Low Power", Debug)
+ Notify(BAT1, 0x80)
+ }
+
+ Method (_Q37, 0)
+ {
+ Store("_Q37: Bat1 Full Charge", Debug)
+ Notify(BAT1, 0x80)
+ }
+
+ Method (_Q38, 0)
+ {
+ Store("_Q38: Bat2 Low Power", Debug)
+ Notify(BAT2, 0x80)
+ }
+
+ Method (_Q39, 0)
+ {
+ Store("_Q39: Bat2 Full Charge", Debug)
+ Notify(BAT2, 0x80)
+ }
+
+ Method (_Q40, 0)
+ {
+ Store("_Q40: LID Open/Close", Debug)
+ Notify(LID0, 0x80)
+ }
+
+ Method (_Q41, 0)
+ {
+ Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug)
+ }
+
+ Method (_Q50, 0)
+ {
+ Store("_Q50: Processor is hot", Debug)
+ Notify(\_TZ.THRM, 0x80)
+ }
+
+ Method (_Q51, 0)
+ {
+ Store("_Q51: Processor is boiling", Debug)
+ Notify(\_TZ.THRM, 0x80)
+ }
+
+ Method (_Q52, 0)
+ {
+ Store("_Q52: Processor is burning", Debug)
+ Notify(\_TZ.THRM, 0x80)
+ }
+
+}
diff --git a/src/mainboard/toshiba/a300-1me/acpi/gpe.asl b/src/mainboard/toshiba/a300-1me/acpi/gpe.asl
new file mode 100644
index 0000000..5ba3538
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/gpe.asl
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (_GPE)
+{
+ /* The event numbers correspond to the bit numbers in the
+ * GPE0_EN register PMBASE + 0x28.
+ */
+ /* IMO we don't need empty Methods here. If we don't specify
+ one and don't set the GPE0_EN bit Linux won't neither enable
+ it. - Nico */
+
+ // Thermal Event - original BIOS doesn't have it
+ Method (_L00, 0)
+ {
+ /* FIXME: We should enable throttling here. */
+ }
+
+ // Hot Plug
+ Method (_L01, 0)
+ {
+
+ }
+
+ // USB1
+ Method (_L03, 0)
+ {
+
+ }
+
+ // USB2
+ Method (_L04, 0)
+ {
+
+ }
+
+ // USB5
+ Method (_L05, 0)
+ {
+
+ }
+
+ // _L06 TCOSCI
+
+ // SMBus Wake Status
+ Method (_L07, 0)
+ {
+
+ }
+
+ // COM1/COM2 (RI)
+ Method (_L08, 0)
+ {
+
+ }
+
+ // PCIe
+ Method (_L09, 0)
+ {
+
+ }
+
+ // _L0A BatLow / Quick Resume
+
+ // PME
+ Method (_L0B, 0)
+ {
+
+ }
+
+ // USB3
+ Method (_L0C, 0)
+ {
+
+ }
+
+ // PME B0
+ Method (_L0D, 0)
+ {
+
+ }
+
+ // USB4
+ Method (_L0E, 0)
+ {
+
+ }
+
+ // _L10 - _L1f: GPIn
+
+ // GPI8
+ Method (_L18, 0)
+ {
+
+ }
+
+ // USB6
+ Method (_L20, 0)
+ {
+
+ }
+}
diff --git a/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl b/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl
new file mode 100644
index 0000000..b206c2b
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH9
+ */
+
+/* TODO: which slots are actually relevant? */
+If (PICM) {
+ Return (Package() {
+ // PCI Slot 1 routes ABCD
+ Package() { 0x0000ffff, 0, 0, 16},
+ Package() { 0x0000ffff, 1, 0, 17},
+ Package() { 0x0000ffff, 2, 0, 18},
+ Package() { 0x0000ffff, 3, 0, 19},
+
+ // PCI Slot 2 routes BCDA
+ Package() { 0x0001ffff, 0, 0, 17},
+ Package() { 0x0001ffff, 1, 0, 18},
+ Package() { 0x0001ffff, 2, 0, 19},
+ Package() { 0x0001ffff, 3, 0, 16},
+
+ // PCI Slot 3 routes CDAB
+ Package() { 0x0002ffff, 0, 0, 18},
+ Package() { 0x0002ffff, 1, 0, 19},
+ Package() { 0x0002ffff, 2, 0, 16},
+ Package() { 0x0002ffff, 3, 0, 17},
+
+ // PCI Slot 4 routes ABCD
+ Package() { 0x0003ffff, 0, 0, 16},
+ Package() { 0x0003ffff, 1, 0, 17},
+ Package() { 0x0003ffff, 2, 0, 18},
+ Package() { 0x0003ffff, 3, 0, 19},
+
+ // PCI Slot 5 routes ABCD
+ Package() { 0x0004ffff, 0, 0, 16},
+ Package() { 0x0004ffff, 1, 0, 17},
+ Package() { 0x0004ffff, 2, 0, 18},
+ Package() { 0x0004ffff, 3, 0, 19},
+
+ // PCI Slot 6 routes BCDA
+ Package() { 0x0005ffff, 0, 0, 17},
+ Package() { 0x0005ffff, 1, 0, 18},
+ Package() { 0x0005ffff, 2, 0, 19},
+ Package() { 0x0005ffff, 3, 0, 16},
+
+ // FIXME: what's this supposed to mean? (adopted from ich7)
+ //Package() { 0x0008ffff, 0, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ // PCI Slot 1 routes ABCD
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ // PCI Slot 2 routes BCDA
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ // PCI Slot 3 routes CDAB
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+
+ // PCI Slot 4 routes ABCD
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ // PCI Slot 5 routes ABCD
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ // PCI Slot 6 routes BCDA
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ // FIXME
+ // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
diff --git a/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl b/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl
new file mode 100644
index 0000000..2f0c927
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (LID0)
+{
+ Name(_HID, EisaId("PNP0C0D"))
+ Method(_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDC)
+ }
+}
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x18, 0x04})
+}
+
+//#include "acpi/battery.asl"
diff --git a/src/mainboard/toshiba/a300-1me/acpi/platform.asl b/src/mainboard/toshiba/a300-1me/acpi/platform.asl
new file mode 100644
index 0000000..f9adffa
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/toshiba/a300-1me/acpi/superio.asl b/src/mainboard/toshiba/a300-1me/acpi/superio.asl
new file mode 100644
index 0000000..48630b0
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/superio.asl
@@ -0,0 +1 @@
+// dummy
diff --git a/src/mainboard/toshiba/a300-1me/acpi/thermal.asl b/src/mainboard/toshiba/a300-1me/acpi/thermal.asl
new file mode 100644
index 0000000..d7f8364
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi/thermal.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ /* degree Celcius to deci-Kelvin (ACPI temperature unit) */
+ Method(C2dK, 1) {
+ Add (2732, Multiply (Arg0, 10), Local0)
+ Return (Local0)
+ }
+
+ ThermalZone (THRM)
+ {
+
+ // FIXME these could/should be read from the
+ // GNVS area, so they can be controlled by
+ // coreboot
+ Name(TC1V, 0x04)
+ Name(TC2V, 0x03)
+ Name(TSPV, 0x96)
+
+ // At which temperature should the OS start
+ // active cooling?
+ Method (_AC0, 0, Serialized)
+ {
+ Return (C2dK(120)) // Value for Rocky
+ }
+
+ // Critical shutdown temperature
+ Method (_CRT, 0, Serialized)
+ {
+ Return (C2dK(155)) // Value for Rocky
+ }
+
+ // CPU throttling start temperature
+ Method (_PSV, 0, Serialized)
+ {
+ Return (C2dK(105)) // Value for Rocky
+ }
+
+ // Get DTS Temperature
+ Method (_TMP, 0, Serialized)
+ {
+ If (\_SB.PCI0.LPCB.EC0.ALRC) {
+ Store(0, \_SB.PCI0.LPCB.EC0.ALRC)
+ Return(_AC0())
+ }
+
+ If (\_SB.PCI0.LPCB.EC0.ALRL) {
+ Store(0, THRO)
+ Store(0, \_SB.PCI0.LPCB.EC0.ALRL)
+ }
+
+ If (\_SB.PCI0.LPCB.EC0.ALRH) {
+ Store(1, THRO)
+ Store(0, \_SB.PCI0.LPCB.EC0.ALRH)
+ }
+
+ /* vendor BIOS reports 0K if TCPU >= 128 deg C ?!? */
+ Return (C2dK(\_SB.PCI0.LPCB.EC0.TCPU))
+ }
+
+
+ // Processors used for active cooling
+ Method (_PSL, 0, Serialized)
+ {
+ If (MPEN) {
+ Return (Package() {\_PR.CP00, \_PR.CP01})
+ }
+ Return (Package() {\_PR.CP00})
+ }
+
+ // TC1 value for passive cooling
+ Method (_TC1, 0, Serialized)
+ {
+ Return (TC1V)
+ }
+
+ // TC2 value for passive cooling
+ Method (_TC2, 0, Serialized)
+ {
+ Return (TC2V)
+ }
+
+ // Sampling period for passive cooling
+ Method (_TSP, 0, Serialized)
+ {
+ Return (TSPV)
+ }
+
+
+ }
+}
diff --git a/src/mainboard/toshiba/a300-1me/acpi_tables.c b/src/mainboard/toshiba/a300-1me/acpi_tables.c
new file mode 100644
index 0000000..0716d2d
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/acpi_tables.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <southbridge/intel/i82801ix/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+
+ /* Enable both COM ports */
+ //gnvs->cmap = 0x01;
+ //gnvs->cmbp = 0x01;
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* LAPIC_NMI */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 0,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 1, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+
+ return current;
+}
diff --git a/src/mainboard/toshiba/a300-1me/blc.c b/src/mainboard/toshiba/a300-1me/blc.c
new file mode 100644
index 0000000..4b6104e
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/blc.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 arthur(a)aheymans.xyz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <northbridge/intel/gm45/gm45.h>
+
+int get_blc_values(const struct blc_pwm_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/toshiba/a300-1me/board_info.txt b/src/mainboard/toshiba/a300-1me/board_info.txt
new file mode 100644
index 0000000..4ce92d3
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/board_info.txt
@@ -0,0 +1 @@
+Category: laptop
diff --git a/src/mainboard/toshiba/a300-1me/cmos.layout b/src/mainboard/toshiba/a300-1me/cmos.layout
new file mode 100644
index 0000000..d794306
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/cmos.layout
@@ -0,0 +1,119 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+# 2012 secunet Security Networks AG
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+#400 8 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 9 sata_mode
+#409 7 r 0 unused
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+928 8 h 0 boot_default
+936 1 e 8 cmos_defaults_loaded
+#937 7 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# coreboot config options: northbridge
+1000 4 e 10 gfx_uma_size
+
+#1004 20 r 0 unused
+
+# RAM initialization internal data
+1024 128 r 0 read_training_results
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 No
+8 1 Yes
+9 0 AHCI
+9 1 Compatible
+11 4 32M
+11 5 48M
+11 6 64M
+11 7 128M
+11 8 256M
+11 9 96M
+11 10 160M
+11 11 224M
+11 12 352M
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/toshiba/a300-1me/cstates.c b/src/mainboard/toshiba/a300-1me/cstates.c
new file mode 100644
index 0000000..fea9276
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/cstates.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+
+static acpi_cstate_t cst_entries[] = {
+ {
+ /* ACPI C1 / CPU C1 */
+ 1, 0x01, 1000,
+ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0, 0 }
+ },
+ {
+ /* ACPI C2 / CPU C2 */
+ 2, 0x01, 500,
+ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x10, 0 }
+ },
+};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
diff --git a/src/mainboard/toshiba/a300-1me/devicetree.cb b/src/mainboard/toshiba/a300-1me/devicetree.cb
new file mode 100644
index 0000000..5936104
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/devicetree.cb
@@ -0,0 +1,142 @@
+chip northbridge/intel/gm45
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_BGA956
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Enable Super LFM
+ register "slfm" = "1"
+
+ # Enable C5, C6
+ register "c5" = "1"
+ register "c6" = "1"
+ end
+ end
+
+ register "pci_mmio_size" = "2048"
+
+ device domain 0 on
+ subsystemid 0x1179 0xff1e inherit
+ device pci 00.0 on end # host bridge
+ device pci 01.0 on end # PEG
+ device pci 02.0 off # VGA
+ # ioapic_irq 2 INTA 0x10
+ end
+ device pci 02.1 off end # Display
+ device pci 03.0 off end # ME
+ device pci 03.1 off end # ME
+ device pci 03.2 off end # ME
+ device pci 03.3 off end # ME
+ chip southbridge/intel/i82801ix
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ register "gpi8_routing" = "2"
+ register "gpi7_routing" = "2"
+ register "gpe0_en" = "0x01800042"
+ register "gpi1_routing" = "1"
+ register "alt_gp_smi_en" = "0x0002"
+
+ # Set AHCI mode, enable ports 1 and 2.
+ register "sata_port_map" = "0x03"
+ register "sata_clock_request" = "0"
+ register "sata_traffic_monitor" = "0"
+
+ # Set c-state support
+ register "c4onc3_enable" = "0"
+ register "c5_enable" = "1"
+ register "c6_enable" = "1"
+
+ # Set thermal throttling to 75%.
+ register "throttle_duty" = "THTL_75_0"
+
+ # Enable PCIe ports 1 and 5 as slots (Mini * PCIe).
+ # register "pcie_slot_implemented" = "0x11"
+ # Set power limits to 10 * 10^0 watts.
+ # Maybe we should set less for Mini PCIe.
+ # register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }"
+
+ device pci 19.0 off end # LAN
+ device pci 1a.0 on # UHCI
+ #ioapic_irq 2 INTA 0x10
+ end
+ device pci 1a.1 on # UHCI
+ #ioapic_irq 2 INTB 0x11
+ end
+ device pci 1a.2 on # UHCI
+ #ioapic_irq 2 INTC 0x12
+ end
+ device pci 1a.7 on # EHCI
+ #ioapic_irq 2 INTC 0x12
+ end
+ device pci 1b.0 on # HD Audio
+ #ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.0 on # PCIe Port #1
+ #ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 on # PCIe Port #5
+ #ioapic_irq 2 INTA 0x10
+ #device pci 00.0 on end # Realtek 8168B
+ end
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on # UHCI
+ #ioapic_irq 2 INTA 0x10
+ end
+ device pci 1d.1 on # UHCI
+ #ioapic_irq 2 INTB 0x11
+ end
+ device pci 1d.2 on # UHCI
+ #ioapic_irq 2 INTC 0x12
+ end
+ device pci 1d.7 on # EHCI
+ #ioapic_irq 2 INTA 0x10
+ end
+ device pci 1e.0 on # PCI
+ #device pci 03.0 on # TI Cardbus
+ #ioapic_irq 2 INTA 0x10
+ #end
+ #device pci 03.1 on # TI Cardbus
+ #ioapic_irq 2 INTB 0x11
+ #end
+ #device pci 03.2 off end # TI FireWire OHC
+ #device pci 03.3 off end # unconnected FlashMedia
+ #device pci 03.4 off end # unconnected SD-Card
+ end
+ device pci 1f.0 on # LPC bridge
+ #chip drivers/generic/ioapic
+ #register "have_isa_interrupts" = "1"
+ #register "irq_on_fsb" = "1"
+ #register "enable_virtual_wire" = "1"
+ #register "base" = "(void *)0xfec00000"
+ #device ioapic 2 on end
+ #end
+
+ # FIXME: WPCE775 support
+ end
+ device pci 1f.2 on # SATA/IDE 1
+ #ioapic_irq 2 INTB 0x11
+ end
+ device pci 1f.3 on # SMBus
+ #ioapic_irq 2 INTC 0x12
+ end
+ device pci 1f.5 off end # SATA/IDE 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/toshiba/a300-1me/dsdt.asl b/src/mainboard/toshiba/a300-1me/dsdt.asl
new file mode 100644
index 0000000..cf2479a
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801ix/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ //#include "acpi/mainboard.asl"
+
+ #include <cpu/intel/speedstep/acpi/cpu.asl>
+
+ // Thermal Zone
+ //#include "acpi/thermal.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/gm45/acpi/gm45.asl>
+ #include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801ix/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/toshiba/a300-1me/fadt.c b/src/mainboard/toshiba/a300-1me/fadt.c
new file mode 100644
index 0000000..f2b8559
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/fadt.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+#include <version.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = get_acpi_table_revision(FADT);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = asl_revision;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->reserved = 0x00;
+ fadt->preferred_pm_profile = PM_MOBILE;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2; /* Upper word is reserved and
+ Linux complains about 32 bit. */
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 0x39;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x32;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = 0x06;
+
+ fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */
+ fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */
+ /* then FIRMWARE_CTRL must be zero. */
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 0;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and
+ Linux complains about 32 bit. */
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 0;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 0;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/toshiba/a300-1me/gpio.c b/src/mainboard/toshiba/a300-1me/gpio.c
new file mode 100644
index 0000000..92454cb
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/gpio.c
@@ -0,0 +1,208 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_NATIVE,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio2 = GPIO_LEVEL_HIGH,
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio4 = GPIO_LEVEL_HIGH,
+ .gpio5 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio11 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio13 = GPIO_LEVEL_HIGH,
+ .gpio14 = GPIO_LEVEL_HIGH,
+ .gpio17 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio19 = GPIO_LEVEL_LOW,
+ .gpio20 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+ .gpio29 = GPIO_LEVEL_LOW,
+ .gpio30 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio6 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_NATIVE,
+ .gpio34 = GPIO_MODE_NATIVE,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_NATIVE,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+ .gpio44 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_HIGH,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio47 = GPIO_LEVEL_HIGH,
+ .gpio48 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/toshiba/a300-1me/hda_verb.c b/src/mainboard/toshiba/a300-1me/hda_verb.c
new file mode 100644
index 0000000..63f37b5
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/hda_verb.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */
+ 0x43528986, /* Subsystem ID */
+ 0x0000000c, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x11), S/PDIF-OUT2: not connected */
+ AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
+ /* Pin Complex (NID 0x14), LINE_OUT (port D): Speakers */
+ AZALIA_PIN_CFG(0, 0x14, 0x99130110),
+ /* Pin Complex (NID 0x15), HP_OUT (port A): Head phones */
+ AZALIA_PIN_CFG(0, 0x15, 0x0121411f),
+ /* Pin Complex (NID 0x16), MONO-OUT: not connected */
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ /* Pin Complex (NID 0x18), MIC1 (port B): Microphone */
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19920),
+ /* Pin Complex (NID 0x19), MIC2 (port F): not connected */
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ /* Pin Complex (NID 0x1a), LINE1 (port C): Line-In */
+ AZALIA_PIN_CFG(0, 0x1a, 0x01813121),
+ /* Pin Complex (NID 0x1b), LINE2 (port E): MDC */
+ AZALIA_PIN_CFG(0, 0x1b, 0x9983012f),
+ /* Pin Complex (NID 0x1c), CD_IN */
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ /* Pin Complex (NID 0x1d), PCBEEP */
+ AZALIA_PIN_CFG(0, 0x1d, 0x4014022d),
+ /* Pin Complex (NID 0x1e), S/PDIF-OUT: not connected */
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ /* Pin Complex (NID 0x1f), S/PDIF-IN: not connected */
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0)
+};
+
+const u32 pc_beep_verbs[] = {
+ //0x00170500, /* power up codec */
+ //0x01470500, /* power up speakers */
+ //0x01470100, /* select lout1 (input 0x0) for speakers */
+ //0x01470740, /* enable speakers output */
+ //0x00b37517, /* unmute beep (mixer's input 0x5), set amp 0dB */
+ //0x00c37100, /* unmute mixer in lout1 (lout1 input 0x1) */
+ //0x00c3b015, /* set lout1 output volume -15dB */
+ //0x0143b000, /* unmute speakers */
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/toshiba/a300-1me/mainboard.c b/src/mainboard/toshiba/a300-1me/mainboard.c
new file mode 100644
index 0000000..eb1ae23
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/mainboard.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/keyboard.h>
+#include <ec/acpi/ec.h>
+
+static void ec_setup(void)
+{
+ /* Thermal limits? Values are from ectool's RAM dump. */
+ //ec_write(0xd1, 0x57); /* CPUH */
+ //ec_write(0xd2, 0xc9); /* CPUL */
+ //ec_write(0xd4, 0x64); /* SYSH */
+ //ec_write(0xd5, 0xc9); /* SYSL */
+
+ //send_ec_command(0x04); /* Set_SMI_Enable */
+ //send_ec_command(0xab); /* Set_ACPI_Disable */
+ //send_ec_command(0xac); /* Clr_SYS_Flag? well, why not? */
+ //send_ec_command(0xad); /* Set_Thml_Value */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ ec_setup();
+ /* LCD panel type is SIO GPIO40-43.
+ It's controlled by a DIP switch but was always
+ set to 4 while only values of 5 and 6 worked. */
+ //install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, (inb(0x60f) & 0x0f) + 1);
+
+ /* We have no driver for the embedded controller since the firmware
+ does most of the job. Hence, initialize keyboards here. */
+ pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/toshiba/a300-1me/romstage.c b/src/mainboard/toshiba/a300-1me/romstage.c
new file mode 100644
index 0000000..dc2b900
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/romstage.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include <device/pci_ops.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <northbridge/intel/gm45/gm45.h>
+
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+void mb_setup_lpc(void)
+{
+ /* Configure serial IRQs.*/
+ pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
+ /* Map COMa on 0x3f8, COMb on 0x2f8. */
+ pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
+ /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */
+ pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
+}
+
+void mb_setup_superio(void)
+{
+ // #FIXME: WPCE775 support
+}
+
+void get_mb_spd_addrmap(u8 *spd_addrmap)
+{
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x52;
+}
diff --git a/src/mainboard/toshiba/a300-1me/smistuff.c b/src/mainboard/toshiba/a300-1me/smistuff.c
new file mode 100644
index 0000000..72f1d35
--- /dev/null
+++ b/src/mainboard/toshiba/a300-1me/smistuff.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/i82801ix/nvs.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <ec/acpi/ec.h>
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << 1)) {
+ printk(BIOS_DEBUG, "EC/SMI\n");
+ /* TODO */
+ }
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ send_ec_command(0x05); /* Set_SMI_Disable */
+ send_ec_command(0xaa); /* Set_ACPI_Enable */
+ break;
+
+ case APM_CNT_ACPI_DISABLE:
+ send_ec_command(0x04); /* Set_SMI_Enable */
+ send_ec_command(0xab); /* Set_ACPI_Disable */
+ break;
+ }
+ return 0;
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/34786
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d
Gerrit-Change-Number: 34786
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
3
6
Change in coreboot[master]: arch/x86: Move stack with CAR_GLOBAL_MIGRATION
by Kyösti Mälkki (Code Review) 24 May '20
by Kyösti Mälkki (Code Review) 24 May '20
24 May '20
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34882 )
Change subject: arch/x86: Move stack with CAR_GLOBAL_MIGRATION
......................................................................
arch/x86: Move stack with CAR_GLOBAL_MIGRATION
With the combination of CAR_GLOBAL_MIGRATION=n and
POSTCAR_STAGE=n it is expected that ramstage decompression
will run in romstage. Due the way MAYBE_STATIC was defined
the scratchpad of ulzman() would remain on the stack.
This would conflict with the small allocation made for the
stack when we have C_ENVIRONMENT_BOOTBLOCK=y.
Expand the definition of MAYBE_STATIC to cover the cases that
have zero-initialisation or no initialisation. These can be
located in .bss. As the large stack requirement now only
applies to CAR_GLOBAL_MIGRATION=y case, stack location within
CAR region can be based on that instead.
Change-Id: I58d50c6f8f922c9e8664698d77836cac2c13b126
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/arch/x86/car.ld
M src/cpu/Kconfig
M src/cpu/intel/socket_FCBGA559/Kconfig
M src/cpu/intel/socket_mPGA604/Kconfig
M src/device/device_const.c
M src/include/stddef.h
M src/lib/lzma.c
M src/lib/timestamp.c
M src/northbridge/intel/haswell/Kconfig
M src/security/tpm/tspi/log.c
M src/soc/amd/picasso/Kconfig
M src/soc/amd/stoneyridge/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/broadwell/Kconfig
14 files changed, 20 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34882/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 5351fc7..6911505 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -40,7 +40,7 @@
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(CAR_GLOBAL_MIGRATION)
_car_stack_start = .;
. += CONFIG_DCACHE_BSP_STACK_SIZE;
_car_stack_end = .;
@@ -91,7 +91,7 @@
_car_global_end = .;
_car_relocatable_data_end = .;
-#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(CAR_GLOBAL_MIGRATION)
_car_stack_start = .;
_car_stack_end = _car_region_end;
#endif
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 3c0bf89..7982569 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -21,7 +21,12 @@
hex
config DCACHE_BSP_STACK_SIZE
+ depends on !CAR_GLOBAL_MIGRATION
hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage by bootblock and
+ other pre-ram stages.
config SMP
bool
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index d3af4ca..b1b310d 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -21,11 +21,4 @@
hex
default 0x4000
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
- help
- The amount of anticipated stack usage in CAR by bootblock and
- other stages.
-
endif
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 1453f99..65ac777 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -28,8 +28,4 @@
hex
default 0x4000
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
-
endif # CPU_INTEL_SOCKET_MPGA604
diff --git a/src/device/device_const.c b/src/device/device_const.c
index c472aea..ef16d4b 100644
--- a/src/device/device_const.c
+++ b/src/device/device_const.c
@@ -204,7 +204,7 @@
DEVTREE_CONST struct bus *pci_root_bus(void)
{
DEVTREE_CONST struct device *pci_domain;
- MAYBE_STATIC DEVTREE_CONST struct bus *pci_root = NULL;
+ DECLARE_MAYBE_STATIC_ZERO(DEVTREE_CONST struct bus *pci_root);
if (pci_root)
return pci_root;
diff --git a/src/include/stddef.h b/src/include/stddef.h
index 7cae2e6..26b9ef6 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -42,6 +42,14 @@
#define MAYBE_STATIC static
#endif
+#if defined(__PRE_RAM__) && CONFIG(CAR_GLOBAL_MIGRATION)
+#define MAYBE_STATIC_NOINIT
+#define DECLARE_MAYBE_STATIC_ZERO(x) x = 0
+#else
+#define MAYBE_STATIC_NOINIT static
+#define DECLARE_MAYBE_STATIC_ZERO(x) static x
+#endif
+
#ifndef __ROMCC__
/* Provide a pointer to address 0 that thwarts any "accessing this is
* undefined behaviour and do whatever" trickery in compilers.
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index eecbb26..7700380 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -26,7 +26,7 @@
int res;
CLzmaDecoderState state;
SizeT mallocneeds;
- MAYBE_STATIC unsigned char scratchpad[15980];
+ MAYBE_STATIC_NOINIT unsigned char scratchpad[15980];
const unsigned char *cp;
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 1319b86..931da3f 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -128,7 +128,7 @@
static struct timestamp_table *timestamp_table_get(void)
{
- MAYBE_STATIC struct timestamp_table *ts_table = NULL;
+ DECLARE_MAYBE_STATIC_ZERO(struct timestamp_table *ts_table);
struct timestamp_cache *ts_cache;
if (ts_table != NULL)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index aad2674..847cc69 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -70,13 +70,6 @@
help
The amount of cache-as-ram region required by the reference code.
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
- help
- The amount of anticipated stack usage in CAR by bootblock and
- other stages.
-
config HAVE_MRC
bool "Add a System Agent binary"
help
diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c
index 4019962..a513860 100644
--- a/src/security/tpm/tspi/log.c
+++ b/src/security/tpm/tspi/log.c
@@ -26,7 +26,7 @@
static struct tcpa_table *tcpa_cbmem_init(void)
{
- MAYBE_STATIC struct tcpa_table *tclt = NULL;
+ DECLARE_MAYBE_STATIC_ZERO(struct tcpa_table *tclt);
if (tclt)
return tclt;
@@ -47,7 +47,7 @@
static struct tcpa_table *tcpa_log_init(void)
{
- MAYBE_STATIC struct tcpa_table *tclt = NULL;
+ DECLARE_MAYBE_STATIC_ZERO(struct tcpa_table *tclt);
/* We are dealing here with pre CBMEM environment.
* If cbmem isn't available use CAR or SRAM */
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 26b2ec4..9f2bc06 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -87,7 +87,6 @@
default 0x10000
config DCACHE_BSP_STACK_SIZE
- depends on C_ENVIRONMENT_BOOTBLOCK
hex
default 0x4000
help
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f1d08c0..b494166 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -103,7 +103,6 @@
default 0x10000
config DCACHE_BSP_STACK_SIZE
- depends on C_ENVIRONMENT_BOOTBLOCK
hex
default 0x4000
help
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 5d6438f..7b41f0c 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -50,13 +50,6 @@
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select C_ENVIRONMENT_BOOTBLOCK
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
- help
- The amount of anticipated stack usage in CAR by bootblock and
- other stages.
-
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x8000
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5856ef1..dc4dd44 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -119,13 +119,6 @@
help
The amount of cache-as-ram region required by the reference code.
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
- help
- The amount of anticipated stack usage in CAR by bootblock and
- other stages.
-
config HAVE_MRC
bool "Add a Memory Reference Code binary"
help
--
To view, visit https://review.coreboot.org/c/coreboot/+/34882
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I58d50c6f8f922c9e8664698d77836cac2c13b126
Gerrit-Change-Number: 34882
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
6
20
Change in ...coreboot[master]: src/mainboard: Add dell/inspiron_n5110
by Angel Pons (Code Review) 23 May '20
by Angel Pons (Code Review) 23 May '20
23 May '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30996
Change subject: src/mainboard: Add dell/inspiron_n5110
......................................................................
src/mainboard: Add dell/inspiron_n5110
Run autoport and clean up. It has Nvidia Optimus, a NPCE795 EC, a PCIe
xHCI controller and who knows what else. The 4MB flash is shared with
the EC, apparently.
Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/inspiron_n5110/Kconfig
A src/mainboard/dell/inspiron_n5110/Kconfig.name
A src/mainboard/dell/inspiron_n5110/Makefile.inc
A src/mainboard/dell/inspiron_n5110/acpi/ec.asl
A src/mainboard/dell/inspiron_n5110/acpi/platform.asl
A src/mainboard/dell/inspiron_n5110/acpi/superio.asl
A src/mainboard/dell/inspiron_n5110/acpi_tables.c
A src/mainboard/dell/inspiron_n5110/board_info.txt
A src/mainboard/dell/inspiron_n5110/devicetree.cb
A src/mainboard/dell/inspiron_n5110/dsdt.asl
A src/mainboard/dell/inspiron_n5110/gma-mainboard.ads
A src/mainboard/dell/inspiron_n5110/gpio.c
A src/mainboard/dell/inspiron_n5110/hda_verb.c
A src/mainboard/dell/inspiron_n5110/mainboard.c
A src/mainboard/dell/inspiron_n5110/romstage.c
17 files changed, 685 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30996/1
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100644
index 0000000..298c62b
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_DELL
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/dell/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/dell/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Dell Inc."
+
+endif # VENDOR_DELL
diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name
new file mode 100644
index 0000000..3d2fefd
--- /dev/null
+++ b/src/mainboard/dell/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_DELL
+ bool "Dell Inc."
diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig b/src/mainboard/dell/inspiron_n5110/Kconfig
new file mode 100644
index 0000000..1a12055
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_DELL_INSPIRON_N5110
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select CPU_INTEL_SOCKET_RPGA989
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select GFX_GMA_INTERNAL_IS_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+ select NO_UART_ON_SUPERIO
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+
+config MAINBOARD_DIR
+ string
+ default dell/inspiron_n5110
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Inspiron N5110"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0116.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0116"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x4b0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1028
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig.name b/src/mainboard/dell/inspiron_n5110/Kconfig.name
new file mode 100644
index 0000000..06334cd
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_INSPIRON_N5110
+ bool "Inspiron N5110"
diff --git a/src/mainboard/dell/inspiron_n5110/Makefile.inc b/src/mainboard/dell/inspiron_n5110/Makefile.inc
new file mode 100644
index 0000000..ea035d3
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/inspiron_n5110/acpi/ec.asl b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl
diff --git a/src/mainboard/dell/inspiron_n5110/acpi/platform.asl b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl
new file mode 100644
index 0000000..cf5d74f
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/dell/inspiron_n5110/acpi/superio.asl b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl
diff --git a/src/mainboard/dell/inspiron_n5110/acpi_tables.c b/src/mainboard/dell/inspiron_n5110/acpi_tables.c
new file mode 100644
index 0000000..7d634a0
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/acpi_tables.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/inspiron_n5110/board_info.txt b/src/mainboard/dell/inspiron_n5110/board_info.txt
new file mode 100644
index 0000000..f48c92b
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/dell/inspiron_n5110/devicetree.cb b/src/mainboard/dell/inspiron_n5110/devicetree.cb
new file mode 100644
index 0000000..be4f590
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/devicetree.cb
@@ -0,0 +1,73 @@
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x0000035e"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "3000"
+ register "gpu_panel_power_backlight_on_delay" = "3000"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "300"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1028 0x04b0 inherit
+ device pci 00.0 on end # Host bridge Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen2_dec" = "0x0004006d"
+ register "p_cnt_throttling_supported" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 1 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x21"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 on end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on end # LPC bridge PCI-LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/inspiron_n5110/dsdt.asl b/src/mainboard/dell/inspiron_n5110/dsdt.asl
new file mode 100644
index 0000000..1b0cae2
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads
new file mode 100644
index 0000000..d4a5d7d
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/inspiron_n5110/gpio.c b/src/mainboard/dell/inspiron_n5110/gpio.c
new file mode 100644
index 0000000..7926ee1
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/gpio.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_NATIVE,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio11 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio57 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio68 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/inspiron_n5110/hda_verb.c b/src/mainboard/dell/inspiron_n5110/hda_verb.c
new file mode 100644
index 0000000..a70733b
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/hda_verb.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76d1, /* Codec Vendor / Device ID: IDT */
+ 0x102804b0, /* Subsystem ID */
+
+ 0x00000007, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x102804b0),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f2),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30160),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/inspiron_n5110/mainboard.c b/src/mainboard/dell/inspiron_n5110/mainboard.c
new file mode 100644
index 0000000..02fe3a5
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/mainboard.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/inspiron_n5110/romstage.c b/src/mainboard/dell/inspiron_n5110/romstage.c
new file mode 100644
index 0000000..fd2f79f
--- /dev/null
+++ b/src/mainboard/dell/inspiron_n5110/romstage.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004006d);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+ { 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+/* FIXME: Assumed completely. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30996
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9
Gerrit-Change-Number: 30996
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
1
1
Change in coreboot[master]: [WIP] nb/intel/x4x/raminit: Do cosmetic fixes
by Angel Pons (Code Review) 23 May '20
by Angel Pons (Code Review) 23 May '20
23 May '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35156 )
Change subject: [WIP] nb/intel/x4x/raminit: Do cosmetic fixes
......................................................................
[WIP] nb/intel/x4x/raminit: Do cosmetic fixes
This is mostly line reflowing to make use of the increased line length
limit of 96 characters.
Ideally, this should be tested to ensure behavior was not modified.
Change-Id: Ie04ec4e493fc2c45e25521869c2f4e5b5a8d26cc
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/x4x/dq_dqs.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/rcven.c
4 files changed, 258 insertions(+), 449 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/35156/1
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index ed372b5..f671f62 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -23,8 +23,7 @@
#include "x4x.h"
#include "iomap.h"
-static void print_dll_setting(const struct dll_setting *dll_setting,
- u8 default_verbose)
+static void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose)
{
u8 debug_level = default_verbose ? BIOS_DEBUG : RAM_DEBUG;
@@ -71,15 +70,13 @@
if (dq_dqs_setting->tap < limit.tap0) {
dq_dqs_setting->db_en = 1;
dq_dqs_setting->db_sel = 1;
- } else if ((dq_dqs_setting->tap == limit.tap0)
- && (dq_dqs_setting->pi < limit.pi0)) {
+ } else if ((dq_dqs_setting->tap == limit.tap0) && (dq_dqs_setting->pi < limit.pi0)) {
dq_dqs_setting->db_en = 1;
dq_dqs_setting->db_sel = 1;
} else if (dq_dqs_setting->tap < limit.tap1) {
dq_dqs_setting->db_en = 0;
dq_dqs_setting->db_sel = 0;
- } else if ((dq_dqs_setting->tap == limit.tap1)
- && (dq_dqs_setting->pi < limit.pi1)) {
+ } else if ((dq_dqs_setting->tap == limit.tap1) && (dq_dqs_setting->pi < limit.pi1)) {
dq_dqs_setting->db_en = 0;
dq_dqs_setting->db_sel = 0;
} else {
@@ -90,11 +87,9 @@
const static u8 max_tap[3] = {12, 10, 13};
-static int increment_dq_dqs(const struct sysinfo *s,
- struct dll_setting *dq_dqs_setting)
+static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
{
- u8 max_tap_val = max_tap[s->selected_timings.mem_clk
- - MEM_CLOCK_800MHz];
+ u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
if (dq_dqs_setting->pi < 6) {
dq_dqs_setting->pi += 1;
@@ -117,11 +112,9 @@
return CB_SUCCESS;
}
-static int decrement_dq_dqs(const struct sysinfo *s,
- struct dll_setting *dq_dqs_setting)
+static int decrement_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
{
- u8 max_tap_val = max_tap[s->selected_timings.mem_clk
- - MEM_CLOCK_800MHz];
+ u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
if (dq_dqs_setting->pi > 0) {
dq_dqs_setting->pi -= 1;
@@ -175,8 +168,7 @@
FAILING = 1
};
-static u8 test_dq_aligned(const struct sysinfo *s,
- const u8 channel)
+static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
{
u32 address;
int rank, lane;
@@ -190,17 +182,14 @@
for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) {
if ((count1 % 16) == 0)
MCHBAR32(0xf90) = 1;
- const u32 pattern =
- write_training_schedule[count1];
+ const u32 pattern = write_training_schedule[count1];
write32((u32 *)address + 8 * count1, pattern);
- write32((u32 *)address + 8 * count1 + 4,
- pattern);
+ write32((u32 *)address + 8 * count1 + 4, pattern);
}
const u32 good = write_training_schedule[count];
write32(&data[0], read32((u32 *)address + 8 * count));
- write32(&data[4],
- read32((u32 *)address + 8 * count + 4));
+ write32(&data[4], read32((u32 *)address + 8 * count + 4));
FOR_EACH_BYTELANE(lane) {
u8 expected = (good >> ((lane % 4) * 8)) & 0xff;
if (data[lane] != expected)
@@ -217,13 +206,11 @@
* This function finds either failing or succeeding writes by increasing DQ.
* When it has found a failing or succeeding setting it will increase DQ
* another 10 times to make sure the result is consistent.
- * This is probably done because lanes cannot be trained independent from
- * each other.
+ * This is probably done because lanes cannot be trained independent from each other.
*/
static int find_dq_limit(const struct sysinfo *s, const u8 channel,
struct dll_setting dq_setting[TOTAL_BYTELANES],
- u8 dq_lim[TOTAL_BYTELANES],
- const enum training_modes expected_result)
+ u8 dq_lim[TOTAL_BYTELANES], const enum training_modes expected_result)
{
int status = CB_SUCCESS;
int lane;
@@ -251,10 +238,10 @@
succes_mask &= ~(1 << lane);
}
if (status == CB_ERR) {
- printk(BIOS_CRIT, "Could not find a case of %s "
- "writes on CH%d, lane %d\n",
- expected_result == FAILING ? "failing"
- : "succeeding", channel, lane);
+ printk(BIOS_CRIT,
+ "Could not find a case of %s writes on CH%d, lane %d\n",
+ expected_result == FAILING ? "failing" : "succeeding",
+ channel, lane);
return CB_ERR;
}
}
@@ -267,7 +254,7 @@
* the DQ and the DQS signal.
* The training works this way:
* - start from the DQS delay values (DQ is always later than DQS)
- * - increment the DQ delay until a succeeding write is found on all bytelayes,
+ * - increment the DQ delay until a succeeding write is found on all bytelanes,
* on all ranks on a channel and save these values
* - again increment the DQ delay until write start to fail on all bytelanes and
* save that value
@@ -297,19 +284,15 @@
/* Start from DQS settings */
memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting));
- if (find_dq_limit(s, channel, dq_setting, dq_lower,
- SUCCEEDING)) {
- printk(BIOS_CRIT,
- "Could not find working lower limit DQ setting\n");
+ if (find_dq_limit(s, channel, dq_setting, dq_lower, SUCCEEDING)) {
+ printk(BIOS_CRIT, "Could not find working lower limit DQ setting\n");
return CB_ERR;
}
memcpy(dq_upper, dq_lower, sizeof(dq_lower));
- if (find_dq_limit(s, channel, dq_setting, dq_upper,
- FAILING)) {
- printk(BIOS_WARNING,
- "Could not find failing upper limit DQ setting\n");
+ if (find_dq_limit(s, channel, dq_setting, dq_upper, FAILING)) {
+ printk(BIOS_WARNING, "Could not find failing upper limit DQ setting\n");
return CB_ERR;
}
@@ -318,15 +301,14 @@
dq_upper[lane] -= CONSISTENCY - 1;
u8 dq_center = (dq_upper[lane] + dq_lower[lane]) / 2;
- printk(RAM_DEBUG, "Centered value for DQ DLL:"
- " ch%d, lane %d, #steps = %d\n",
+ printk(RAM_DEBUG,
+ "Centered value for DQ DLL: ch%d, lane %d, #steps = %d\n",
channel, lane, dq_center);
for (i = 0; i < dq_center; i++) {
/* Should never happen */
if (increment_dq_dqs(s, &s->dq_settings[channel][lane])
== CB_ERR)
- printk(BIOS_ERR,
- "Huh? write training overflowed!!\n");
+ printk(BIOS_ERR, "Huh? write training overflowed!!\n");
}
}
@@ -419,13 +401,10 @@
}
if (expected_result == SUCCEEDING) {
- printk(BIOS_CRIT,
- "Could not find RT DQS setting\n");
+ printk(BIOS_CRIT, "Could not find RT DQS setting\n");
return CB_ERR;
} else {
- printk(RAM_DEBUG,
- "Read succeeded over all DQS"
- " settings, continuing\n");
+ printk(RAM_DEBUG, "Read succeeded over all DQS settings, continuing\n");
return CB_SUCCESS;
}
}
@@ -437,18 +416,17 @@
* The training works this way:
* - start from the lowest possible delay (0) on all bytelanes
* - increment the DQS rx delays until a succeeding write is found on all
- * bytelayes, on all ranks on a channel and save these values
+ * bytelanes, on all ranks on a channel and save these values
* - again increment the DQS rx delay until write start to fail on all bytelanes
* and save that value
* - use the mean between the saved succeeding and failing value
* - note0: bytelanes cannot be trained independently, so the delays need to be
* adjusted and tested for all of them at the same time
* - note1: At this stage all ranks effectively use the rank0's rt_dqs settings,
- * but later on their respective settings are used (TODO where is the
- * 'switch' register??). So programming the results for all ranks at the end
- * of the training. Programming on all ranks instead of all populated ranks,
- * seems to be required, most likely because the signals can't really be generated
- * separately.
+ * but later on their respective settings are used (TODO where is the 'switch' register??)
+ * So programming the results for all ranks at the end of the training. Programming on all
+ * ranks instead of all populated ranks, seems to be required, most likely because the
+ * signals can't really be generated separately.
*/
int do_read_training(struct sysinfo *s)
{
@@ -465,8 +443,7 @@
for (loop = 0; loop < RT_LOOPS; loop++) {
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
- printk(RAM_DEBUG, "Doing DQS read training on CH%d\n",
- channel);
+ printk(RAM_DEBUG, "Doing DQS read training on CH%d\n", channel);
/* Write pattern to strobe address */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) {
@@ -480,8 +457,7 @@
memset(dqs_lower, 0, sizeof(dqs_lower));
memset(&dqs_setting, 0, sizeof(dqs_setting));
- if (rt_find_dqs_limit(s, channel, dqs_setting, dqs_lower,
- SUCCEEDING)) {
+ if (rt_find_dqs_limit(s, channel, dqs_setting, dqs_lower, SUCCEEDING)) {
printk(BIOS_CRIT,
"Could not find working lower limit DQS setting\n");
return CB_ERR;
@@ -490,8 +466,7 @@
FOR_EACH_BYTELANE(lane)
dqs_upper[lane] = dqs_lower[lane];
- if (rt_find_dqs_limit(s, channel, dqs_setting, dqs_upper,
- FAILING)) {
+ if (rt_find_dqs_limit(s, channel, dqs_setting, dqs_upper, FAILING)) {
printk(BIOS_CRIT,
"Could not find failing upper limit DQ setting\n");
return CB_ERR;
@@ -513,19 +488,16 @@
FOR_EACH_BYTELANE(lane) {
saved_dqs_center[channel][lane] /= RT_LOOPS;
while (saved_dqs_center[channel][lane]--) {
- if(rt_increment_dqs(&s->rt_dqs[channel][lane])
- == CB_ERR)
+ if (rt_increment_dqs(&s->rt_dqs[channel][lane]) == CB_ERR)
/* Should never happen */
- printk(BIOS_ERR,
- "Huh? read training overflowed!!\n");
+ printk(BIOS_ERR, "Huh? read training overflowed!!\n");
}
- /* Later on separate settings for each rank are used so program
+ /* Later on, separate settings for each rank are used, so program
all of them */
FOR_EACH_RANK_IN_CHANNEL(rank)
- rt_set_dqs(channel, lane, rank,
- &s->rt_dqs[channel][lane]);
- printk(BIOS_DEBUG, "\tlane%d: %d.%d\n",
- lane, s->rt_dqs[channel][lane].tap,
+ rt_set_dqs(channel, lane, rank, &s->rt_dqs[channel][lane]);
+ printk(BIOS_DEBUG, "\tlane%d: %d.%d\n", lane,
+ s->rt_dqs[channel][lane].tap,
s->rt_dqs[channel][lane].pi);
}
}
@@ -641,8 +613,8 @@
#define N_SAMPLES 5
-static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank,
- u8 high_found[8]) {
+static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, u8 high_found[8])
+{
u32 address = test_address(channel, rank);
int samples, lane;
@@ -652,8 +624,7 @@
write32((u32 *)address + 4, 0x12341234);
udelay(5);
FOR_EACH_BYTELANE(lane) {
- u8 dq_high = (MCHBAR8(0x561 + 0x400 * channel
- + (lane * 4)) >> 7) & 1;
+ u8 dq_high = (MCHBAR8(0x561 + 0x400 * channel + (lane * 4)) >> 7) & 1;
high_found[lane] += dq_high;
}
}
@@ -680,14 +651,12 @@
if (bytelane_ok & (1 << lane))
continue;
- printk(RAM_SPEW, "%d, %d, %02d, %d,"
- " lane%d sample: %d\n",
+ printk(RAM_SPEW, "%d, %d, %02d, %d, lane%d sample: %d\n",
dqs_setting[lane].coarse,
dqs_setting[lane].clk_delay,
dqs_setting[lane].tap,
dqs_setting[lane].pi,
- lane,
- dq_sample[lane]);
+ lane, dq_sample[lane]);
if (dq_sample[lane] > 0) {
if (decrement_dq_dqs(s, &dqs_setting[lane])) {
@@ -723,8 +692,7 @@
dqs_setting[lane].clk_delay,
dqs_setting[lane].tap,
dqs_setting[lane].pi,
- lane,
- dq_sample[lane]);
+ lane, dq_sample[lane]);
if (dq_sample[lane] == N_SAMPLES) {
bytelane_ok |= (1 << lane);
@@ -760,19 +728,18 @@
/*
* DDR3 uses flyby topology where the clock signal takes a different path
- * than the data signal, to allow for better signal intergrity.
- * Therefore the delay on the data signals needs to account for this.
- * This is done by by sampleling the the DQS write (tx) signal back over
- * the DQ signal and looking for delay values where the sample transitions
- * from high to low.
- * Here the following is done:
+ * than the data signal, to allow for better signal integrity.
+ * Therefore, the delay on the data signals needs to account for this.
+ * This is done by by sampling the the DQS write (tx) signal back over the DQ signal
+ * and looking for delay values where the sample transitions from high to low.
+ * Here, the following is done:
* - enable write levelling on the first populated rank
* - disable output on other populated ranks
* - start from safe DQS (tx) delays (other transitions can be
* found at different starting values but are generally bad)
* - loop0: decrease DQS (tx) delays until low is sampled,
* loop1: increase DQS (tx) delays until high is sampled,
- * That way we are sure to hit a low-high transition
+ * That way, we are sure to hit a low-high transition
* - put all ranks in normal mode of operation again
* - note: All ranks need to be leveled together
*/
@@ -782,7 +749,7 @@
u8 config, rank0, rank1, lane;
struct dll_setting dq_setting;
- u8 chanconfig_lut[16]={0, 6, 4, 6, 7, 3, 1, 3, 5, 2, 0, 2, 7, 3, 1, 3};
+ u8 chanconfig_lut[16] = {0, 6, 4, 6, 7, 3, 1, 3, 5, 2, 0, 2, 7, 3, 1, 3};
u8 odt_force[8][4] = { /* [Config][leveling rank] */
{0x5, 0x6, 0x5, 0x9},
@@ -801,50 +768,38 @@
printk(BIOS_DEBUG, "\tCH%d\n", ch);
config = chanconfig_lut[s->dimm_config[ch]];
- MCHBAR8(0x5d8 + 0x400 * ch) =
- MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
+ MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) &
~0x3fff) | 0x3fff;
- MCHBAR8(0x265 + 0x400 * ch) =
- MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
+ MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
/* find the first populated rank */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
break;
- /* Enable WL for the first populated rank and disable output
- for others */
+ /* Enable WL for the first populated rank and disable output for others */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1)
set_rank_write_level(s, ch, config, rank1, rank0, 1);
- MCHBAR8(0x298 + 2 + 0x400 * ch) =
- (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f)
- | odt_force[config][rank0];
- MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch)
- & ~0x7e) | 0x4e;
- MCHBAR8(0x5d9 + 0x400 * ch) =
- (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff)
- | 0x00014000;
+ MCHBAR8(0x298 + 2 + 0x400 * ch) = (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f)
+ | odt_force[config][rank0];
+
+ MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e;
+ MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
+ MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
if (increment_to_dqs_edge(s, ch, rank0))
die("Write Leveling failed!");
- MCHBAR8(0x298 + 2 + 0x400 * ch) =
- MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f;
- MCHBAR8(0x271 + 0x400 * ch) =
- (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e)
- | 0x0e;
- MCHBAR8(0x5d9 + 0x400 * ch) =
- (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04);
- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0)
- & ~0x07ffffff) | 0x00555801;
+ MCHBAR8(0x298 + 2 + 0x400 * ch) = MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f;
+ MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x0e;
+ MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04);
+ MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00555801;
/* Disable WL on the trained rank */
set_rank_write_level(s, ch, config, rank0, rank0, 0);
send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
- MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch)
- & ~0x0e) | 0x0e;
+ MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e;
MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch)
& ~0x3fff) | 0x1807;
MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
@@ -856,7 +811,7 @@
MCHBAR8(0x5dc) = (MCHBAR8(0x5dc) & ~0x80) | 0x80;
- /* Increment DQ (rx) dll setting by a standard amount past DQS,
+ /* Increment DQ (rx) dll setting by a standard amount past DQS.
This is further trained in write training. */
switch (s->selected_timings.mem_clk) {
default:
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 8013af9..32f0897 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -59,8 +59,7 @@
return spd_ddr3_calc_unique_crc(raw_spd, len);
}
-static enum cb_err verify_spds(const u8 *spd_map,
- const struct sysinfo *ctrl_cached)
+static enum cb_err verify_spds(const u8 *spd_map, const struct sysinfo *ctrl_cached)
{
int i;
u16 crc;
@@ -69,11 +68,9 @@
if (!(spd_map[i]))
continue;
int len = smbus_read_byte(spd_map[i], 0);
- if (len < 0 && ctrl_cached->dimms[i].card_type
- == RAW_CARD_UNPOPULATED)
+ if (len < 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED)
continue;
- if (len > 0 && ctrl_cached->dimms[i].card_type
- == RAW_CARD_UNPOPULATED)
+ if (len > 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED)
return CB_ERR;
if (ctrl_cached->spd_type == DDR2)
@@ -104,8 +101,7 @@
#define CTRL_MIN_TCLK_DDR2 TCK_400MHZ
-static void select_cas_dramfreq_ddr2(struct sysinfo *s,
- const struct abs_timings *saved_timings)
+static void select_cas_dramfreq_ddr2(struct sysinfo *s, const struct abs_timings *saved_timings)
{
u8 try_cas;
/* Currently only these CAS are supported */
@@ -178,8 +174,7 @@
if (!(decoded_dimm.width & (0x08 | 0x10))) {
- printk(BIOS_ERR,
- "DIMM%d Unsupported width: x%d. Disabling dimm\n",
+ printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
dimm_idx, s->dimms[dimm_idx].width);
return CB_ERR;
}
@@ -215,28 +210,20 @@
saved_timings->cas_supported &= decoded_dimm.cas_supported;
- saved_timings->min_tRAS =
- MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
- saved_timings->min_tRP =
- MAX(saved_timings->min_tRP, decoded_dimm.tRP);
- saved_timings->min_tRCD =
- MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
- saved_timings->min_tWR =
- MAX(saved_timings->min_tWR, decoded_dimm.tWR);
- saved_timings->min_tRFC =
- MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
- saved_timings->min_tWTR =
- MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
- saved_timings->min_tRRD =
- MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
- saved_timings->min_tRTP =
- MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
+ saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
+ saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP);
+ saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
+ saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR);
+ saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
+ saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
+ saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
+ saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
+
for (i = 0; i < 8; i++) {
if (!(saved_timings->cas_supported & (1 << i)))
saved_timings->min_tCLK_cas[i] = 0;
else
- saved_timings->min_tCLK_cas[i] =
- MAX(saved_timings->min_tCLK_cas[i],
+ saved_timings->min_tCLK_cas[i] = MAX(saved_timings->min_tCLK_cas[i],
decoded_dimm.cycle_time[i]);
}
@@ -257,12 +244,11 @@
*tCLK = 0;
}
-static void select_cas_dramfreq_ddr3(struct sysinfo *s,
- struct abs_timings *saved_timings)
+static void select_cas_dramfreq_ddr3(struct sysinfo *s, struct abs_timings *saved_timings)
{
/*
* various constraints must be fulfilled:
- * CAS * tCK < 20ns == 160MTB
+ * CAS * tCK < 20ns == 160MTB
* tCK_max >= tCK >= tCK_min
* CAS >= roundup(tAA_min/tCK)
* CAS supported
@@ -304,9 +290,8 @@
min_tCLK = MAX(min_tCLK, saved_timings->min_tclk);
if (min_tCLK == 0) {
- printk(BIOS_ERR, "DRAM frequency is under lowest supported "
- "frequency (400 MHz). Increasing to 400 MHz "
- "as last resort");
+ printk(BIOS_ERR, "DRAM frequency is lower than supported frequency (400 MHz)."
+ " Increasing to 400 MHz as last resort.\n");
min_tCLK = TCK_400MHZ;
}
@@ -317,10 +302,7 @@
try_CAS = DIV_ROUND_UP(saved_timings->min_tAA, min_tCLK);
printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", try_CAS, min_tCLK);
for (; try_CAS <= DDR3_MAX_CAS; try_CAS++) {
- /*
- * cas_supported is encoded like the SPD which starts
- * at CAS=4.
- */
+ /* cas_supported is encoded like the SPD which starts at CAS=4. */
if ((saved_timings->cas_supported << 4) & (1 << try_CAS))
break;
}
@@ -331,9 +313,8 @@
break;
}
/*
- * If no valid tCLK / CAS pair could be found for a tCLK
- * increase it after which it gets normalised. This means
- * that a lower frequency gets tried.
+ * If no valid tCLK / CAS pair could be found for a tCLK, increase it after
+ * which it gets normalised. This means that a lower frequency gets tried.
*/
min_tCLK++;
}
@@ -354,20 +335,22 @@
}
}
-/* With DDR3 and 533MHz mem clock and an enabled internal gfx device the display
- is not usable in non stacked mode, so select stacked mode accordingly */
+/* With DDR3 and 533MHz mem clock and an enabled internal gfx device, the display
+ is not usable in non-stacked mode, so select stacked mode accordingly */
static void workaround_stacked_mode(struct sysinfo *s)
{
u32 deven;
/* Only a problem on DDR3 */
if (s->spd_type == DDR2)
return;
+
/* Does not matter if only one channel is populated */
- if (!CHANNEL_IS_POPULATED(s->dimms, 0)
- || !CHANNEL_IS_POPULATED(s->dimms, 1))
+ if (!CHANNEL_IS_POPULATED(s->dimms, 0) || !CHANNEL_IS_POPULATED(s->dimms, 1))
return;
+
if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz)
return;
+
/* IGD0EN gets disabled if not present before this code runs */
deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN);
if (deven & IGD0EN)
@@ -394,9 +377,9 @@
s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1;
/*
* This boils down to:
- * "Except for the x16 configuration, all DDR3 devices have a
- * 1KB page size. For the x16 configuration, the page size is 2KB
- * for all densities except the 256Mb device, which has a 1KB page size."
+ * "Except for the x16 configuration, all DDR3 devices have a 1KB page size.
+ * For the x16 configuration, the page size is 2KB for all densities except
+ * the 256Mb device, which has a 1KB page size."
* Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
*/
s->dimms[dimm_idx].page_size = decoded_dimm.width *
@@ -408,28 +391,19 @@
s->dimms[dimm_idx].rows = decoded_dimm.row_bits;
s->dimms[dimm_idx].cols = decoded_dimm.col_bits;
- saved_timings->min_tRAS =
- MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
- saved_timings->min_tRP =
- MAX(saved_timings->min_tRP, decoded_dimm.tRP);
- saved_timings->min_tRCD =
- MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
- saved_timings->min_tWR =
- MAX(saved_timings->min_tWR, decoded_dimm.tWR);
- saved_timings->min_tRFC =
- MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
- saved_timings->min_tWTR =
- MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
- saved_timings->min_tRRD =
- MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
- saved_timings->min_tRTP =
- MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
- saved_timings->min_tAA =
- MAX(saved_timings->min_tAA, decoded_dimm.tAA);
+ saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
+ saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP);
+ saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
+ saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR);
+ saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
+ saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
+ saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
+ saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
+ saved_timings->min_tAA = MAX(saved_timings->min_tAA, decoded_dimm.tAA);
+
saved_timings->cas_supported &= decoded_dimm.cas_supported;
- s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd,
- raw_spd[0]);
+ s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd, raw_spd[0]);
s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored;
@@ -437,33 +411,22 @@
}
-static void select_discrete_timings(struct sysinfo *s,
- const struct abs_timings *timings)
+static void select_discrete_timings(struct sysinfo *s, const struct abs_timings *timings)
{
- s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS,
- s->selected_timings.tclk);
- s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP,
- s->selected_timings.tclk);
- s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD,
- s->selected_timings.tclk);
- s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR,
- s->selected_timings.tclk);
- s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC,
- s->selected_timings.tclk);
- s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR,
- s->selected_timings.tclk);
- s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD,
- s->selected_timings.tclk);
- s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP,
- s->selected_timings.tclk);
+ s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS, s->selected_timings.tclk);
+ s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP, s->selected_timings.tclk);
+ s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD, s->selected_timings.tclk);
+ s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR, s->selected_timings.tclk);
+ s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC, s->selected_timings.tclk);
+ s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR, s->selected_timings.tclk);
+ s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD, s->selected_timings.tclk);
+ s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP, s->selected_timings.tclk);
}
static void print_selected_timings(struct sysinfo *s)
{
printk(BIOS_DEBUG, "Selected timings:\n");
- printk(BIOS_DEBUG, "\tFSB: %dMHz\n",
- fsb_to_mhz(s->selected_timings.fsb_clk));
- printk(BIOS_DEBUG, "\tDDR: %dMHz\n",
- ddr_to_mhz(s->selected_timings.mem_clk));
+ printk(BIOS_DEBUG, "\tFSB: %dMHz\n", fsb_to_mhz(s->selected_timings.fsb_clk));
+ printk(BIOS_DEBUG, "\tDDR: %dMHz\n", ddr_to_mhz(s->selected_timings.mem_clk));
printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS);
printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS);
@@ -541,16 +504,14 @@
if (s->spd_type == DDR2){
if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) {
printk(BIOS_WARNING,
- "Encountered problems with SPD, "
- "skipping this DIMM.\n");
+ "Encountered problems with SPD, skipping this DIMM.\n");
s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
continue;
}
} else { /* DDR3 */
if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) {
printk(BIOS_WARNING,
- "Encountered problems with SPD, "
- "skipping this DIMM.\n");
+ "Encountered problems with SPD, skipping this DIMM.\n");
/* something in decoded SPD was unsupported */
s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
continue;
@@ -565,6 +526,7 @@
select_cas_dramfreq_ddr2(s, &saved_timings);
else
select_cas_dramfreq_ddr3(s, &saved_timings);
+
select_discrete_timings(s, &saved_timings);
workaround_stacked_mode(s);
}
@@ -587,11 +549,9 @@
else
die("Dual-rank x16 not supported\n");
}
- s->dimm_config[chan] |=
- dimm_config << (i % DIMMS_PER_CHANNEL) * 2;
+ s->dimm_config[chan] |= dimm_config << (i % DIMMS_PER_CHANNEL) * 2;
}
- printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan,
- s->dimm_config[chan]);
+ printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]);
}
}
@@ -604,11 +564,9 @@
if (boot_path >= 1) {
pmsts = MCHBAR32(PMSTS_MCHBAR);
if (!(pmsts & 1))
- printk(BIOS_DEBUG,
- "Channel 0 possibly not in self refresh\n");
+ printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n");
if (!(pmsts & 2))
- printk(BIOS_DEBUG,
- "Channel 1 possibly not in self refresh\n");
+ printk(BIOS_DEBUG, "Channel 1 possibly not in self refresh\n");
}
pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
@@ -646,8 +604,7 @@
memset(&s, 0, sizeof(struct sysinfo));
- cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,
- MRC_CACHE_VERSION, &rdev);
+ cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev);
if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) {
if (boot_path == BOOT_PATH_RESUME) {
@@ -665,8 +622,7 @@
/* verify MRC cache for fast boot */
if (boot_path != BOOT_PATH_RESUME && ctrl_cached) {
- /* check SPD checksum to make sure the DIMMs haven't been
- * replaced */
+ /* check SPD checksum to make sure the DIMMs haven't been replaced */
fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS;
if (!fast_boot) {
printk(BIOS_DEBUG, "SPD checksums don't match,"
@@ -698,8 +654,7 @@
/* Detect dimms per channel */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9);
- printk(BIOS_DEBUG, "Dimms per channel: %d\n",
- (reg8 & 0x10) ? 1 : 2);
+ printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2);
mchinfo_ddr2(&s);
@@ -720,8 +675,8 @@
cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);
if (!fast_boot)
- mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
- &s, sizeof(s));
+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &s, sizeof(s));
+
if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) {
/* Failed S3 resume, reset to come up cleanly */
system_reset();
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 1e40b9c..d7152ef 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -345,8 +345,7 @@
for (rank = 0; rank < 4; rank++) {
MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane),
- (setting->db_en << (9 + lane)) |
- (setting->db_sel << lane));
+ (setting->db_en << (9 + lane)) | (setting->db_sel << lane));
MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4,
~(0x3 << (16 + lane * 2)),
@@ -354,21 +353,18 @@
MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) =
(MCHBAR8(0x400*ch + 0x520 + lane * 4) & ~0x7f) |
- (setting->pi << 4) |
- setting->tap;
+ (setting->pi << 4) | setting->tap;
}
}
void dqset(u8 ch, u8 lane, const struct dll_setting *setting)
{
int rank;
- MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)),
- setting->coarse << (lane * 4));
+ MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)), setting->coarse << (lane * 4));
for (rank = 0; rank < 4; rank++) {
MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane),
- (setting->db_en << (9 + lane)) |
- (setting->db_sel << lane));
+ (setting->db_en << (9 + lane)) | (setting->db_sel << lane));
MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4,
~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane));
@@ -378,8 +374,7 @@
}
}
-void rt_set_dqs(u8 channel, u8 lane, u8 rank,
- struct rt_dqs_setting *dqs_setting)
+void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting)
{
u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4);
u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4);
@@ -519,29 +514,24 @@
/* tWL - x ?? */
MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4);
MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas);
- MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00,
- (adjusted_cas + 9) << 8);
+ MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00, (adjusted_cas + 9) << 8);
reg16 = (s->selected_timings.tRAS << 11) |
((twl + 4 + s->selected_timings.tWR) << 6) |
((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1;
MCHBAR16(0x400*i + 0x250) = reg16;
- reg32 = (bankmod << 21) |
- (s->selected_timings.tRRD << 17) |
+ reg32 = (bankmod << 21) | (s->selected_timings.tRRD << 17) |
(s->selected_timings.tRP << 13) |
- ((s->selected_timings.tRP + trpmod) << 9) |
- s->selected_timings.tRFC;
+ ((s->selected_timings.tRP + trpmod) << 9) | s->selected_timings.tRFC;
if (bankmod == 0) {
reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1;
if (s->spd_type == DDR2)
reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk
- - MEM_CLOCK_667MHz][reg8][pagemod]
- << 22;
+ - MEM_CLOCK_667MHz][reg8][pagemod] << 22;
else
reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk
- - MEM_CLOCK_800MHz][reg8][pagemod]
- << 22;
+ - MEM_CLOCK_800MHz][reg8][pagemod] << 22;
}
MCHBAR32(0x400*i + 0x252) = reg32;
@@ -557,9 +547,9 @@
MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe,
(s->spd_type == DDR2 ? 100 : 256) << 1);
+
MCHBAR8(0x400*i + 0x264) = 0xff;
- MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f,
- s->selected_timings.tRAS);
+ MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f, s->selected_timings.tRAS);
MCHBAR16(0x400*i + 0x244) = 0x2310;
switch (s->selected_timings.mem_clk) {
@@ -671,8 +661,7 @@
if (s->spd_type == DDR3) {
MCHBAR8(0x114) = 0x42;
reg16 = (512 - MAX(5, s->selected_timings.tRFC + 10000
- / ddr_to_ps[s->selected_timings.mem_clk]))
- / 2;
+ / ddr_to_ps[s->selected_timings.mem_clk])) / 2;
reg16 &= 0x1ff;
reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9);
}
@@ -686,8 +675,7 @@
u16 reg16 = 0;
u32 reg32 = 0;
- const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04,
- 0x08, 0x10 };
+ const u8 rank2clken[8] = {0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10};
MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04);
MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8);
@@ -729,8 +717,7 @@
udelay(1); // 533ns
// ME related
- MCHBAR32_AND_OR(0x1a0, ~0x7ffffff,
- s->spd_type == DDR2 ? 0x551803 : 0x555801);
+ MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801);
MCHBAR16_AND(0x1b4, ~0x800);
if (s->spd_type == DDR2) {
@@ -761,34 +748,25 @@
if (s->spd_type == DDR2) {
if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
- printk(BIOS_DEBUG,
- "No dimms in channel %d\n", i);
+ printk(BIOS_DEBUG, "No dimms in channel %d\n", i);
reg8 = 0x3f;
} else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {
- printk(BIOS_DEBUG,
- "DimmA populated only in channel %d\n",
- i);
+ printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i);
reg8 = 0x38;
} else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {
- printk(BIOS_DEBUG,
- "DimmB populated only in channel %d\n",
- i);
+ printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i);
reg8 = 0x7;
} else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
- printk(BIOS_DEBUG,
- "Both dimms populated in channel %d\n",
- i);
+ printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i);
reg8 = 0;
} else {
die("Unhandled case\n");
}
- MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000,
- (u32)(reg8 << 24));
+ MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, (u32)(reg8 << 24));
} else { /* DDR3 */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
- MCHBAR8_AND(0x400 * i + 0x5a0 + 3,
- ~rank2clken[r + i * 4]);
+ MCHBAR8_AND(0x400 * i + 0x5a0 + 3, ~rank2clken[r + i * 4]);
}
}
@@ -811,8 +789,7 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc);
MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc);
- MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0,
- s->spd_type == DDR2 ? 0x70 : 0x60);
+ MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, s->spd_type == DDR2 ? 0x70 : 0x60);
MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff,
s->spd_type == DDR2 ? 0x5555 : 0xa955);
}
@@ -971,52 +948,42 @@
FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) {
switch (s->selected_timings.mem_clk) {
case MEM_CLOCK_667MHz:
- memcpy(s->dqs_settings[ch],
- default_ddr2_667_dqs,
+ memcpy(s->dqs_settings[ch], default_ddr2_667_dqs,
sizeof(s->dqs_settings[ch]));
- memcpy(s->dq_settings[ch],
- default_ddr2_667_dq,
+ memcpy(s->dq_settings[ch], default_ddr2_667_dq,
sizeof(s->dq_settings[ch]));
s->rt_dqs[ch][lane].tap = 7;
s->rt_dqs[ch][lane].pi = 2;
break;
case MEM_CLOCK_800MHz:
if (s->spd_type == DDR2) {
- memcpy(s->dqs_settings[ch],
- default_ddr2_800_dqs,
+ memcpy(s->dqs_settings[ch], default_ddr2_800_dqs,
sizeof(s->dqs_settings[ch]));
- memcpy(s->dq_settings[ch],
- default_ddr2_800_dq,
+ memcpy(s->dq_settings[ch], default_ddr2_800_dq,
sizeof(s->dq_settings[ch]));
s->rt_dqs[ch][lane].tap = 7;
s->rt_dqs[ch][lane].pi = 0;
} else { /* DDR3 */
- memcpy(s->dqs_settings[ch],
- default_ddr3_800_dqs[s->nmode - 1],
+ memcpy(s->dqs_settings[ch], default_ddr3_800_dqs[s->nmode - 1],
sizeof(s->dqs_settings[ch]));
- memcpy(s->dq_settings[ch],
- default_ddr3_800_dq[s->nmode - 1],
+ memcpy(s->dq_settings[ch], default_ddr3_800_dq[s->nmode - 1],
sizeof(s->dq_settings[ch]));
s->rt_dqs[ch][lane].tap = 6;
s->rt_dqs[ch][lane].pi = 3;
}
break;
case MEM_CLOCK_1066MHz:
- memcpy(s->dqs_settings[ch],
- default_ddr3_1067_dqs[s->nmode - 1],
+ memcpy(s->dqs_settings[ch], default_ddr3_1067_dqs[s->nmode - 1],
sizeof(s->dqs_settings[ch]));
- memcpy(s->dq_settings[ch],
- default_ddr3_1067_dq[s->nmode - 1],
+ memcpy(s->dq_settings[ch], default_ddr3_1067_dq[s->nmode - 1],
sizeof(s->dq_settings[ch]));
s->rt_dqs[ch][lane].tap = 5;
s->rt_dqs[ch][lane].pi = 3;
break;
case MEM_CLOCK_1333MHz:
- memcpy(s->dqs_settings[ch],
- default_ddr3_1333_dqs[s->nmode - 1],
+ memcpy(s->dqs_settings[ch], default_ddr3_1333_dqs[s->nmode - 1],
sizeof(s->dqs_settings[ch]));
- memcpy(s->dq_settings[ch],
- default_ddr3_1333_dq[s->nmode - 1],
+ memcpy(s->dq_settings[ch], default_ddr3_1333_dq[s->nmode - 1],
sizeof(s->dq_settings[ch]));
s->rt_dqs[ch][lane].tap = 7;
s->rt_dqs[ch][lane].pi = 0;
@@ -1040,8 +1007,7 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
FOR_EACH_BYTELANE(lane) {
FOR_EACH_RANK_IN_CHANNEL(rank) {
- rt_set_dqs(ch, lane, rank,
- &s->rt_dqs[ch][lane]);
+ rt_set_dqs(ch, lane, rank, &s->rt_dqs[ch][lane]);
}
dqsset(ch, lane, &s->dqs_settings[ch][lane]);
dqset(ch, lane, &s->dq_settings[ch][lane]);
@@ -1052,20 +1018,20 @@
static void prog_rcomp(struct sysinfo *s)
{
u8 i, j, k, reg8;
- const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A,
- 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D };
- const u16 ddr2_x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 };
- const u32 ddr2_x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 };
- const u32 ddr2_x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 };
- const u32 ddr2_x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 };
- const u32 ddr2_x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 };
- const u32 ddr2_x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 };
- const u32 ddr2_x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 };
- const u32 ddr2_x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 };
- const u32 ddr2_x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 };
+ const u32 ddr2_x32a[8] = {0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A,
+ 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D};
+ const u16 ddr2_x378[6] = {0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777};
+ const u32 ddr2_x382[6] = {0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303};
+ const u32 ddr2_x386[6] = {0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404};
+ const u32 ddr2_x38a[6] = {0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605};
+ const u32 ddr2_x38e[6] = {0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808};
+ const u32 ddr2_x392[6] = {0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202};
+ const u32 ddr2_x396[6] = {0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303};
+ const u32 ddr2_x39a[6] = {0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605};
+ const u32 ddr2_x39e[6] = {0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808};
const u32 ddr3_x32a[8] = {0x06060606, 0x06060606, 0x0b090807, 0x12110f0d,
- 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511};
+ 0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511};
const u16 ddr3_x378[6] = {0, 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666};
const u32 ddr3_x382[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x386[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
@@ -1080,8 +1046,8 @@
const u32 *x32a, *x382, *x386, *x38a, *x38e;
const u32 *x392, *x396, *x39a, *x39e;
- const u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c };
- u8 bit[6] = { 0, 0, 1, 1, 0, 0 };
+ const u16 addr[6] = {0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c};
+ u8 bit[6] = {0, 0, 1, 1, 0, 0};
if (s->spd_type == DDR2) {
x32a = ddr2_x32a;
@@ -1110,45 +1076,29 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
for (j = 0; j < 6; j++) {
if (j == 0) {
- MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000,
- 0xaa000);
- MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,
- 0x6666);
+ MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000, 0xaa000);
+ MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, 0x6666);
for (k = 0; k < 8; k++) {
- MCHBAR32_AND_OR(0x400*i + addr[j] +
- 0xe + (k << 2),
- ~0x3f3f3f3f, x32a[k]);
- MCHBAR32_AND_OR(0x400*i + addr[j] +
- 0x2e + (k << 2),
- ~0x3f3f3f3f, x32a[k]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe + (k << 2),
+ ~0x3f3f3f3f, x32a[k]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2e + (k << 2),
+ ~0x3f3f3f3f, x32a[k]);
}
} else {
- MCHBAR16_AND_OR(0x400*i + addr[j],
- ~0xf000, 0xa000);
- MCHBAR16_AND_OR(0x400*i + addr[j] + 4,
- ~0xffff, x378[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe,
- ~0x3f3f3f3f, x382[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12,
- ~0x3f3f3f3f, x386[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16,
- ~0x3f3f3f3f, x38a[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a,
- ~0x3f3f3f3f, x38e[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e,
- ~0x3f3f3f3f, x392[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22,
- ~0x3f3f3f3f, x396[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26,
- ~0x3f3f3f3f, x39a[j]);
- MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a,
- ~0x3f3f3f3f, x39e[j]);
+ MCHBAR16_AND_OR(0x400*i + addr[j], ~0xf000, 0xa000);
+ MCHBAR16_AND_OR(0x400*i + addr[j] + 4, ~0xffff, x378[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x0e, ~0x3f3f3f3f, x382[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, ~0x3f3f3f3f, x386[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, ~0x3f3f3f3f, x38a[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, ~0x3f3f3f3f, x38e[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, ~0x3f3f3f3f, x392[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, ~0x3f3f3f3f, x396[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, ~0x3f3f3f3f, x39a[j]);
+ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]);
}
- if (s->spd_type == DDR3 &&
- BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
- MCHBAR16_AND_OR(0x378 + 0x400 * i,
- ~0xffff, 0xcccc);
- }
+ if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i))
+ MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc);
+
MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]);
}
reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36;
@@ -1214,15 +1164,11 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
if (s->spd_type == DDR2) {
- MCHBAR16(0x400 * i + 0x298) =
- ddr2_odt[s->dimm_config[i]][1];
- MCHBAR16(0x400 * i + 0x294) =
- ddr2_odt[s->dimm_config[i]][0];
+ MCHBAR16(0x400 * i + 0x298) = ddr2_odt[s->dimm_config[i]][1];
+ MCHBAR16(0x400 * i + 0x294) = ddr2_odt[s->dimm_config[i]][0];
} else {
- MCHBAR16(0x400 * i + 0x298) =
- ddr3_odt[s->dimm_config[i]][1];
- MCHBAR16(0x400 * i + 0x294) =
- ddr3_odt[s->dimm_config[i]][0];
+ MCHBAR16(0x400 * i + 0x298) = ddr3_odt[s->dimm_config[i]][1];
+ MCHBAR16(0x400 * i + 0x294) = ddr3_odt[s->dimm_config[i]][0];
}
u16 reg16 = MCHBAR16(0x400*i + 0x29c);
reg16 &= ~0xfff;
@@ -1275,7 +1221,7 @@
MCHBAR16(C1DRB0) = 0x0002;
MCHBAR16(C1DRB1) = 0x0004;
MCHBAR16(C1DRB2) = 0x0006;
- /* In stacked mode the last present rank on ch1 needs to have its
+ /* In stacked mode, the last present rank on ch1 needs to have its
size doubled in c1drbx */
MCHBAR16(C1DRB3) = 0x0010;
MCHBAR8_OR(0x111, STACKED_MEM);
@@ -1320,16 +1266,13 @@
u8 data8 = cmd;
u32 data32;
- if (s->spd_type == DDR3 && (r & 1)
- && s->dimms[ch * 2 + (r >> 1)].mirrored) {
+ if (s->spd_type == DDR3 && (r & 1) && s->dimms[ch * 2 + (r >> 1)].mirrored)
data8 = (u8)mirror_shift_bit(data8, 4);
- }
MCHBAR8_AND_OR(0x271, ~0x3e, data8);
MCHBAR8_AND_OR(0x671, ~0x3e, data8);
data32 = val;
- if (s->spd_type == DDR3 && (r & 1)
- && s->dimms[ch * 2 + (r >> 1)].mirrored) {
+ if (s->spd_type == DDR3 && (r & 1) && s->dimms[ch * 2 + (r >> 1)].mirrored) {
data32 = mirror_shift_bit(data32, 3);
data32 = mirror_shift_bit(data32, 5);
data32 = mirror_shift_bit(data32, 7);
@@ -1474,11 +1417,9 @@
MCHBAR32(0x400 * channel + 0x248) = reg32;
FOR_EACH_BYTELANE(lane) {
- medium |= s->rcven_t[channel].medium[lane]
- << (lane * 2);
- coarse_offset |=
- (s->rcven_t[channel].coarse_offset[lane] & 0x3)
- << (lane * 2);
+ medium |= s->rcven_t[channel].medium[lane] << (lane * 2);
+ coarse_offset |= (s->rcven_t[channel].coarse_offset[lane] & 0x3)
+ << (lane * 2);
pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4);
pi_tap &= ~0x7f;
@@ -1575,11 +1516,9 @@
}
}
- if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) ||
- ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
+ if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
MCHBAR8_OR(0x260, 1);
- if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) ||
- ONLY_DIMMB_IS_POPULATED(s->dimms, 1))
+ if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1))
MCHBAR8_OR(0x660, 1);
// DRB
@@ -1679,26 +1618,22 @@
/*
* "108h[15:0] Single Channel Offset for Ch0"
- * This is the 'limit' of the part on CH0 that cannot be matched
- * with memory on CH1. MCHBAR16(0x10a) is where the dual channel
- * memory on ch0s end and MCHBAR16(0x108) is the limit of the single
- * channel size on ch0.
+ * This is the 'limit' of the part on CH0 that cannot be matched with memory on CH1.
+ * MCHBAR16(0x10a) is where the dual channel memory on ch0s end.
+ * MCHBAR16(0x108) is the limit of the single channel size on ch0.
*/
if (s->stacked_mode && size_ch1 != 0) {
single_channel_offset = 0;
} else if (size_me == 0) {
if (size_ch0 > size_ch1)
- single_channel_offset = dual_channel_size / 2
- + single_channel_size;
+ single_channel_offset = dual_channel_size / 2 + single_channel_size;
else
single_channel_offset = dual_channel_size / 2;
} else {
if ((size_ch0 > size_ch1) && ((map & 0x7) == 4))
- single_channel_offset = dual_channel_size / 2
- + single_channel_size;
+ single_channel_offset = dual_channel_size / 2 + single_channel_size;
else
- single_channel_offset = dual_channel_size / 2
- + size_me;
+ single_channel_offset = dual_channel_size / 2 + size_me;
}
MCHBAR16(0x108) = single_channel_offset;
@@ -1712,9 +1647,8 @@
u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;
u32 mmiostart, umasizem;
u16 ggc;
- u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
- 160, 224, 352 };
- u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
+ u16 ggc2uma[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352};
+ u8 ggc2gtt[] = {0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
u8 reg8;
ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
@@ -1751,10 +1685,8 @@
pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4);
pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6);
if (reclaim) {
- pci_write_config16(PCI_DEV(0, 0, 0), 0x98,
- (u16)(reclaimbase >> 6));
- pci_write_config16(PCI_DEV(0, 0, 0), 0x9a,
- (u16)(reclaimlimit >> 6));
+ pci_write_config16(PCI_DEV(0, 0, 0), 0x98, (u16)(reclaimbase >> 6));
+ pci_write_config16(PCI_DEV(0, 0, 0), 0x9a, (u16)(reclaimlimit >> 6));
}
pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
@@ -2017,8 +1949,7 @@
MCHBAR8_OR(0x1a8, 0x4);
// Set freq
- MCHBAR32_AND_OR(0xc00, ~0x70,
- (s->selected_timings.mem_clk << 4) | (1 << 10));
+ MCHBAR32_AND_OR(0xc00, ~0x70, (s->selected_timings.mem_clk << 4) | (1 << 10));
// Overwrite freq if chipset rejects it
s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4;
@@ -2124,18 +2055,14 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
reg32 = (2 << 18);
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
- [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0]
- << 13;
+ [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] << 13;
if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz &&
- s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz &&
- ch == 1) {
+ s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && ch == 1) {
reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk]
- [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1]
- - 1) << 8;
+ [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] - 1) << 8;
} else {
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
- [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1]
- << 8;
+ [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8;
}
MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32);
MCHBAR8_AND(0x400*ch + 0x274, ~0x80);
@@ -2176,18 +2103,15 @@
volatile u32 data;
FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
for (bank = 0; bank < 4; bank++) {
- reg32 = test_address(ch, r) |
- (bank << 12);
+ reg32 = test_address(ch, r) | (bank << 12);
write32((u32 *)reg32, 0xffffffff);
data = read32((u32 *)reg32);
printk(BIOS_DEBUG, "Wrote ones,");
- printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n",
- reg32, data);
+ printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", reg32, data);
write32((u32 *)reg32, 0x00000000);
data = read32((u32 *)reg32);
printk(BIOS_DEBUG, "Wrote zeros,");
- printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n",
- reg32, data);
+ printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", reg32, data);
}
}
}
@@ -2232,11 +2156,9 @@
* and is only needed in case of ME being used.
*/
if (ME_UMA_SIZEMB != 0) {
- if (RANK_IS_POPULATED(s->dimms, 0, 0)
- || RANK_IS_POPULATED(s->dimms, 1, 0))
+ if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0))
MCHBAR8_OR(0xa2f, 1 << 0);
- if (RANK_IS_POPULATED(s->dimms, 0, 1)
- || RANK_IS_POPULATED(s->dimms, 1, 1))
+ if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1))
MCHBAR8_OR(0xa2f, 1 << 1);
MCHBAR32_OR(0xa30, 1 << 26);
}
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 36a6ebd..a1e3894 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -55,8 +55,7 @@
return (MCHBAR8(sample_offset) >> 6) & 1;
}
-static void program_timing(const struct rec_timing *timing, u8 channel,
- u8 lane)
+static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
{
u32 reg32;
u16 reg16;
@@ -135,15 +134,12 @@
return 0;
}
-static int decr_coarse_low(u8 channel, u8 lane, u32 addr,
- struct rec_timing *timing)
+static int decr_coarse_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
- printk(RAM_DEBUG,
- " Decreasing coarse until high to low transition is found\n");
+ printk(RAM_DEBUG, " Decreasing coarse until high to low transition is found\n");
while (sampledqs(addr, lane, channel) != DQS_LOW) {
if (timing->coarse == 0) {
- printk(BIOS_CRIT,
- "Couldn't find DQS-high 0 indicator, halt\n");
+ printk(BIOS_CRIT, "Couldn't find DQS-high 0 indicator, halt\n");
return -1;
}
timing->coarse--;
@@ -154,31 +150,24 @@
return 0;
}
-static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr,
- struct rec_timing *timing)
+static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
- printk(RAM_DEBUG,
- " Increasing TAP until low to high transition is found\n");
+ printk(RAM_DEBUG, " Increasing TAP until low to high transition is found\n");
/*
- * We use a do while loop since it happens that the strobe read
- * is inconsistent, with the strobe already high. The current
- * code flow results in failure later when finding the preamble,
- * at which DQS needs to be high is often not the case if TAP was
- * not increased at least once here. Work around this by incrementing
- * TAP at least once to guarantee searching for preamble start at
- * DQS high.
- * This seems to be the result of hysteresis on some settings, where
- * the DQS probe is influenced by its previous value.
+ * We use a do-while loop, since it happens that the strobe read is inconsistent, with
+ * the strobe already high. The current code flow results in failure later when finding
+ * the preamble, at which DQS needs to be high and is often not the case if TAP was not
+ * increased at least once here. Work around this by incrementing TAP at least once to
+ * guarantee searching for preamble start at DQS high. This seems to be the result of
+ * hysteresis on some settings, where the DQS probe is influenced by its previous value.
*/
if (sampledqs(addr, lane, channel) == DQS_HIGH) {
- printk(BIOS_WARNING,
- "DQS already HIGH... DQS probe is inconsistent!\n"
+ printk(BIOS_WARNING, "DQS already HIGH... DQS probe is inconsistent!\n"
"Continuing....\n");
}
do {
if (increase_tap(timing)) {
- printk(BIOS_CRIT,
- "Could not find DQS-high on fine search.\n");
+ printk(BIOS_CRIT, "Could not find DQS-high on fine search.\n");
return -1;
}
program_timing(timing, channel, lane);
@@ -189,15 +178,13 @@
return 0;
}
-static int find_dqs_low(u8 channel, u8 lane, u32 addr,
- struct rec_timing *timing)
+static int find_dqs_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
/* Look for DQS low, using quarter steps. */
printk(RAM_DEBUG, " Increasing medium until DQS LOW is found\n");
while (sampledqs(addr, lane, channel) != DQS_LOW) {
if (increase_medium(timing)) {
- printk(BIOS_CRIT,
- "Coarse > 15: DQS tuning failed, halt\n");
+ printk(BIOS_CRIT, "Coarse > 15: DQS tuning failed, halt\n");
return -1;
}
program_timing(timing, channel, lane);
@@ -206,15 +193,13 @@
timing->coarse, timing->medium);
return 0;
}
-static int find_dqs_high(u8 channel, u8 lane, u32 addr,
- struct rec_timing *timing)
+static int find_dqs_high(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
/* Look for DQS high, using quarter steps. */
printk(RAM_DEBUG, " Increasing medium until DQS HIGH is found\n");
while (sampledqs(addr, lane, channel) != DQS_HIGH) {
if (increase_medium(timing)) {
- printk(BIOS_CRIT,
- "Coarse > 16: DQS tuning failed, halt\n");
+ printk(BIOS_CRIT, "Coarse > 16: DQS tuning failed, halt\n");
return -1;
}
program_timing(timing, channel, lane);
@@ -224,8 +209,7 @@
return 0;
}
-static int find_dqs_edge_lowhigh(u8 channel, u8 lane,
- u32 addr, struct rec_timing *timing)
+static int find_dqs_edge_lowhigh(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
/* Medium search for DQS high. */
if (find_dqs_high(channel, lane, addr, timing))
@@ -241,8 +225,7 @@
return 0;
}
-static int find_preamble(u8 channel, u8 lane, u32 addr,
- struct rec_timing *timing)
+static int find_preamble(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
/* Add a quarter step */
if (increase_medium(timing))
@@ -260,8 +243,7 @@
return 0;
}
-static int calibrate_receive_enable(u8 channel, u8 lane,
- u32 addr, struct rec_timing *timing)
+static int calibrate_receive_enable(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
{
program_timing(timing, channel, lane);
/* Set receive enable bit */
@@ -308,10 +290,7 @@
{
int rank;
u8 channel, lane, reg8;
- /*
- * Using the macros below the compiler warns about this possibly being
- * unitialised.
- */
+ /* Using the macros below, the compiler warns about this possibly being unitialised. */
u32 addr = 0;
struct rec_timing timing[TOTAL_BYTELANES];
u8 mincoarse;
@@ -357,8 +336,7 @@
timing[lane].tap = 0;
timing[lane].pi = 0;
- if (calibrate_receive_enable(channel, lane, addr,
- &timing[lane]))
+ if (calibrate_receive_enable(channel, lane, addr, &timing[lane]))
die("Receive enable calibration failed\n");
if (mincoarse > timing[lane].coarse)
mincoarse = timing[lane].coarse;
@@ -372,10 +350,9 @@
reg8 = 0;
else
reg8 = timing[lane].coarse - mincoarse;
- printk(BIOS_DEBUG, "ch %d lane %d: coarse offset: %d;"
- "medium: %d; tap: %d\n",
- channel, lane, reg8, timing[lane].medium,
- timing[lane].tap);
+ printk(BIOS_DEBUG,
+ "ch %d lane %d: coarse offset: %d; medium: %d; tap: %d\n",
+ channel, lane, reg8, timing[lane].medium, timing[lane].tap);
s->rcven_t[channel].coarse_offset[lane] = reg8;
s->rcven_t[channel].medium[lane] = timing[lane].medium;
s->rcven_t[channel].tap[lane] = timing[lane].tap;
--
To view, visit https://review.coreboot.org/c/coreboot/+/35156
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie04ec4e493fc2c45e25521869c2f4e5b5a8d26cc
Gerrit-Change-Number: 35156
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
3
7
Change in coreboot[master]: _WIP_ soc/amd/picasso: Update northbridge
by Marshall Dawson (Code Review) 20 May '20
by Marshall Dawson (Code Review) 20 May '20
20 May '20
Hello Martin Roth, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34424
to review the following change.
Change subject: _WIP_ soc/amd/picasso: Update northbridge
......................................................................
_WIP_ soc/amd/picasso: Update northbridge
todo: need to update northbridge_init() to set NP regions. Waiting
on agreement for publishing NDA info in b:137781581
Family 17h devices is designed with a new internal architecture,
frequently referred to as the data fabric. Although designed to
behave somewhat like the older integrated northbridge designs,
the D18Fx definitions are completely new.
AGESA sets up most of the necessary configuration. coreboot still
enables the VGA decode if used.
Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/soc/amd/picasso/chip.c
M src/soc/amd/picasso/include/soc/northbridge.h
M src/soc/amd/picasso/include/soc/pci_devs.h
M src/soc/amd/picasso/northbridge.c
4 files changed, 89 insertions(+), 287 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34424/1
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index d94091d..f34e696 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -120,6 +120,7 @@
{
fsp_silicon_init(acpi_is_wakeup_s3());
+ northbridge_init();
southbridge_init(chip_info);
setup_bsp_ramtop();
}
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
index cb683c2..1a440aa 100644
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -20,58 +20,12 @@
#include <device/device.h>
#include <types.h>
-/* D1F1 - HDA Configuration Registers */
-#define HDA_DEV_CTRL_STATUS 0x60
-#define HDA_NO_SNOOP_EN BIT(11)
+/* D18F0 - Fabric Configuration registers */
+#define FABRIC_ID_IOMS0 9
-/* D18F0 - HT Configuration Registers */
-#define D18F0_NODE_ID 0x60
-#define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */
-# define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */
-#define HT_INIT_CONTROL 0x6c
-# define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10))
-# define HTIC_COLD_RST_DET BIT(4)
-
-/* D18F1 - Address Map Registers */
-
-/* MMIO base and limit */
-#define D18F1_MMIO_BASE0_LO 0x80
-# define MMIO_WE (1 << 1)
-# define MMIO_RE (1 << 0)
-#define D18F1_MMIO_LIMIT0_LO 0x84
-# define MMIO_NP (1 << 7)
-#define D18F1_IO_BASE0_LO 0xc0
-#define D18F1_IO_BASE1_LO 0xc8
-#define D18F1_IO_BASE2_LO 0xd0
-#define D18F1_IO_BASE3_LO 0xd8
-#define D18F1_MMIO_BASE7_LO 0xb8
-#define D18F1_MMIO_BASELIM0_HI 0x180
-#define D18F1_MMIO_BASE8_LO 0x1a0
-#define D18F1_MMIO_LIMIT8_LO 0x1a4
-#define D18F1_MMIO_BASE11_LO 0x1b8
-#define D18F1_MMIO_BASELIM8_HI 0x1c0
-#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
- ? D18F1_MMIO_BASE0_LO \
- : D18F1_MMIO_BASE8_LO \
- - 8 * sizeof(uint64_t)))
-#define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t))
-#define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + (((reg) < 8) \
- ? D18F1_MMIO_BASELIM0_HI \
- : D18F1_MMIO_BASELIM8_HI \
- - 8 * sizeof(uint32_t)))
-/* I/O base and limit */
-#define D18F1_IO_BASE0 0xc0
-# define IO_WE (1 << 1)
-# define IO_RE (1 << 0)
-#define D18F1_IO_LIMIT0 0xc4
-#define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0)
-#define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t))
-
-#define D18F1_DRAM_HOLE 0xf0
-# define DRAM_HOIST_VALID (1 << 1)
-# define DRAM_HOLE_VALID (1 << 0)
-#define D18F1_VGAEN 0xf4
-# define VGA_ADDR_ENABLE (1 << 0)
+#define D18F0_VGAEN 0x80
+#define VGA_ADDR_ENABLE BIT(0)
+#define VGA_DST_ID_SH 4
enum {
/* SMM handler area. */
@@ -98,7 +52,7 @@
int smm_subregion(int sub, void **start, size_t *size);
void domain_enable_resources(struct device *dev);
void domain_set_resources(struct device *dev);
-void fam15_finalize(void *chip_info);
+void northbridge_init(void);
void set_warm_reset_flag(void);
int is_warm_reset(void);
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index acde455..9a9c184 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -102,47 +102,36 @@
#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC)
-/* HT Configuration */
-#define HT_DEV 0x18
-#define HT_FUNC 0
-#define HT_DEVID 0x15b0
-#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)
-#define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC)
+/* Data Fabric functions */
+#define DF_DEV 0x18
-/* Address Maps */
-#define ADDR_DEV 0x18
-#define ADDR_FUNC 1
-#define ADDR_DEVID 0x15b1
-#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
-#define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC)
+#define DF_F0_DEVID 0x15e8
+#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0)
+#define SOC_DF_F0_DEVFN _SOC_DEV(DF_DEV, 0)
-/* DRAM Configuration */
-#define DCT_DEV 0x18
-#define DCT_FUNC 2
-#define DCT_DEVID 0x15b2
-#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)
-#define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC)
+#define DF_F1_DEVID 0x15e9
+#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1)
+#define SOC_DF_F1_DEVFN _SOC_DEV(DF_DEV, 1)
-/* Misc. Configuration */
-#define MISC_DEV 0x18
-#define MISC_FUNC 3
-#define MISC_DEVID 0x15b3
-#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)
-#define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC)
+#define DF_F2_DEVID 0x15ea
+#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2)
+#define SOC_DF_F2_DEVFN _SOC_DEV(DF_DEV, 2)
-/* PM Configuration */
-#define PM_DEV 0x18
-#define PM_FUNC 4
-#define PM_DEVID 0x15b4
-#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)
-#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC)
+#define DF_F3_DEVID 0x15eb
+#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3)
+#define SOC_DF_F3_DEVFN _SOC_DEV(DF_DEV, 3)
-/* Northbridge Configuration */
-#define NB_DEV 0x18
-#define NB_FUNC 5
-#define NB_DEVID 0x15b5
-#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)
-#define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC)
+#define DF_F4_DEVID 0x15ec
+#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4)
+#define SOC_DF_F4_DEVFN _SOC_DEV(DF_DEV, 4)
+
+#define DF_F5_DEVID 0x15ed
+#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5)
+#define SOC_DF_F5_DEVFN _SOC_DEV(DF_DEV, 5)
+
+#define DF_F6_DEVID 0x15ee
+#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6)
+#define SOC_DF_F6_DEVFN _SOC_DEV(DF_DEV, 6)
/* USB 3.1 */
#define XHCI0_DEV 0x0
diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c
index 2335d0d..0b30efa 100644
--- a/src/soc/amd/picasso/northbridge.c
+++ b/src/soc/amd/picasso/northbridge.c
@@ -36,128 +36,63 @@
#include <stdlib.h>
#include <string.h>
#include <arch/bert_storage.h>
+#include <fsp/util.h>
#include "chip.h"
-static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
- u32 io_min, u32 io_max)
-{
- u32 tempreg;
-
- /* io range allocation. Limit */
- tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)
- | ((io_max & 0xf0) << (12 - 4));
- pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);
- tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */
- pci_write_config32(SOC_ADDR_DEV, reg, tempreg);
-}
-
-static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
- u32 mmio_min, u32 mmio_max)
-{
- u32 tempreg;
-
- /* io range allocation. Limit */
- tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
- pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);
- tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
- pci_write_config32(SOC_ADDR_DEV, reg, tempreg);
-}
-
static void read_resources(struct device *dev)
{
- /*
- * This MMCONF resource must be reserved in the PCI domain.
- * It is not honored by the coreboot resource allocator if it is in
- * the CPU_CLUSTER.
- */
+ msr_t tom = rdmsr(TOP_MEM);
+ uint32_t mem_useable = (uintptr_t)cbmem_top();
+ int idx = 0x10;
+ const struct hob_header *hob = fsp_get_hob_list();
+ struct hob_resource *res;
+
+ /* 0x0 - 0x9ffff */
+ ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+
+ /* 0xa0000 - 0xbffff: legacy VGA */
+ mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
+
+ /* 0xc0000 - 0xfffff: Option ROM */
+ reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
+
+ /* 0x100000 (1MiB) - low top useable RAM
+ * cbmem_top() accounts for low UMA and TSEG if they are used. */
+ ram_resource(dev, idx++, (1 * MiB) / KiB,
+ (mem_useable - (1 * MiB)) / KiB);
+
+ /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */
+ reserved_ram_resource(dev, idx++, mem_useable / KiB,
+ (tom.lo - mem_useable) / KiB);
+
mmconf_resource(dev, MMIO_CONF_BASE);
-}
-static void set_resource(struct device *dev, struct resource *res, u32 nodeid)
-{
- resource_t rbase, rend;
- unsigned int reg, link_num;
- char buf[50];
-
- /* Make certain the resource has actually been set */
- if (!(res->flags & IORESOURCE_ASSIGNED))
+ if (!hob) {
+ printk(BIOS_ERR, "Error: %s incomplete becuase no HOB list was found\n",
+ __func__);
return;
+ }
- /* If I have already stored this resource don't worry about it */
- if (res->flags & IORESOURCE_STORED)
- return;
+ for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) {
- /* Only handle PCI memory and IO resources */
- if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
- return;
+ if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
+ continue;
- /* Ensure I am actually looking at a resource of function 1 */
- if ((res->index & 0xffff) < 0x1000)
- return;
+ res = (struct hob_resource *)fsp_hob_header_to_resource(hob);
- /* Get the base address */
- rbase = res->base;
-
- /* Get the limit (rounded up) */
- rend = resource_end(res);
-
- /* Get the register and link */
- reg = res->index & 0xfff; /* 4k */
- link_num = IOINDEX_LINK(res->index);
-
- if (res->flags & IORESOURCE_IO)
- set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
- else if (res->flags & IORESOURCE_MEM)
- set_mmio_addr_reg(nodeid, link_num, reg,
- (res->index >> 24), rbase >> 8, rend >> 8);
-
- res->flags |= IORESOURCE_STORED;
- snprintf(buf, sizeof(buf), " <node %x link %x>",
- nodeid, link_num);
- report_resource_stored(dev, res, buf);
-}
-
-/**
- * I tried to reuse the resource allocation code in set_resource()
- * but it is too difficult to deal with the resource allocation magic.
- */
-
-static void create_vga_resource(struct device *dev)
-{
- struct bus *link;
-
- /* find out which link the VGA card is connected,
- * we only deal with the 'first' vga card */
- for (link = dev->link_list ; link ; link = link->next)
- if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
- break;
-
- /* no VGA card installed */
- if (link == NULL)
- return;
-
- printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
- /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
- pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
-}
-
-static void set_resources(struct device *dev)
-{
- struct bus *bus;
- struct resource *res;
-
-
- /* do we need this? */
- create_vga_resource(dev);
-
- /* Set each resource we have found */
- for (res = dev->resource_list ; res ; res = res->next)
- set_resource(dev, res, 0);
-
- for (bus = dev->link_list ; bus ; bus = bus->next)
- if (bus->children)
- assign_resources(bus);
+ if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && !res->addr)
+ continue; /* 0 through TOM was set above */
+ else if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
+ ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+ else if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
+ continue;
+ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
+ reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+ else
+ printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
+ res->type);
+ }
}
unsigned long acpi_fill_mcfg(unsigned long current)
@@ -203,7 +138,6 @@
static struct device_operations northbridge_operations = {
.read_resources = read_resources,
- .set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
.write_acpi_tables = agesa_write_acpi_tables,
@@ -211,103 +145,27 @@
.ops_pci = 0,
};
-static const struct pci_driver family15_northbridge __pci_driver = {
+static const struct pci_driver family17_northbridge __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
+ .device = PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB,
};
-/*
- * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
- * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
- * MMIO to posted. Route all I/O to the southbridge.
- */
-void amd_initcpuio(void)
+void northbridge_init(void)
{
- uintptr_t topmem = bsp_topmem();
- uintptr_t base, limit;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
-
- /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
- base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
- limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
-
- /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
- base = (topmem >> 8) | MMIO_WE | MMIO_RE;
- limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
- pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
-
- /* Route all I/O downstream */
- base = 0 | IO_WE | IO_RE;
- limit = ALIGN_DOWN(0xffff, 4 * KiB);
- pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
- pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
-}
-
-void fam15_finalize(void *chip_info)
-{
- u32 value;
-
- /* disable No Snoop */
- value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);
- value &= ~HDA_NO_SNOOP_EN;
- pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);
+ /*
+ * AGESA has already programmed the NB MMIO routing, however nothing
+ * is yet marked as non-posted.
+ *
+ * TODO: Remove the settings from AGESA and allow coreboot to own
+ * everything. If not practical, consider erasing all settings and
+ * reprogram for coreboot. At that time, make the following more
+ * flexible.
+ */
}
void domain_set_resources(struct device *dev)
{
- uint64_t uma_base = get_uma_base();
- uint32_t uma_size = get_uma_size();
- uint32_t mem_useable = (uintptr_t)cbmem_top();
- msr_t tom = rdmsr(TOP_MEM);
- msr_t high_tom = rdmsr(TOP_MEM2);
- uint64_t high_mem_useable;
- int idx = 0x10;
-
- /* 0x0 -> 0x9ffff */
- ram_resource(dev, idx++, 0, 0xa0000 / KiB);
-
- /* 0xa0000 -> 0xbffff: legacy VGA */
- mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
-
- /* 0xc0000 -> 0xfffff: Option ROM */
- reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
-
- /*
- * 0x100000 (1MiB) -> low top useable RAM
- * cbmem_top() accounts for low UMA and TSEG if they are used.
- */
- ram_resource(dev, idx++, (1 * MiB) / KiB,
- (mem_useable - (1 * MiB)) / KiB);
-
- /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */
- reserved_ram_resource(dev, idx++, mem_useable / KiB,
- (tom.lo - mem_useable) / KiB);
-
- /* If there is memory above 4GiB */
- if (high_tom.hi) {
- /* 4GiB -> high top useable */
- if (uma_base >= (4ull * GiB))
- high_mem_useable = uma_base;
- else
- high_mem_useable = ((uint64_t)high_tom.lo |
- ((uint64_t)high_tom.hi << 32));
-
- ram_resource(dev, idx++, (4ull * GiB) / KiB,
- ((high_mem_useable - (4ull * GiB)) / KiB));
-
- /* High top useable RAM -> high top RAM */
- if (uma_base >= (4ull * GiB)) {
- reserved_ram_resource(dev, idx++, uma_base / KiB,
- uma_size / KiB);
- }
- }
-
assign_resources(dev->link_list);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/34424
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Gerrit-Change-Number: 34424
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
11
57
Change in ...coreboot[master]: src/cpu/x86: Check pointer processor_name_start before dereference
by John Zhao (Code Review) 20 May '20
by John Zhao (Code Review) 20 May '20
20 May '20
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33232
Change subject: src/cpu/x86: Check pointer processor_name_start before dereference
......................................................................
src/cpu/x86: Check pointer processor_name_start before dereference
Clang Static Analyzer version 8.0.0 detects the left operand of '=='
is a garbage value if pointer processor_name_start is NULL. Add sanity
check for processor_name_start before dereference.
TEST=Built and boot up to kernel.
Change-Id: I1f831a8661a4686d306b8217655942934102ea16
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/cpu/x86/name/name.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33232/1
diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c
index fc360cd..44a1cf0 100644
--- a/src/cpu/x86/name/name.c
+++ b/src/cpu/x86/name/name.c
@@ -37,6 +37,9 @@
/* Skip leading spaces. */
processor_name_start = (char *)name_as_ints;
+ if (!processor_name_start)
+ return;
+
while (*processor_name_start == ' ')
processor_name_start++;
--
To view, visit https://review.coreboot.org/c/coreboot/+/33232
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1f831a8661a4686d306b8217655942934102ea16
Gerrit-Change-Number: 33232
Gerrit-PatchSet: 1
Gerrit-Owner: John Zhao <john.zhao(a)intel.com>
Gerrit-MessageType: newchange
2
5
20 May '20
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/35021 )
Change subject: vboot: Avoid insecure data handling
......................................................................
vboot: Avoid insecure data handling
Coverity detects the overflowed value "rev" used as return value.
Cast the value "rev" to integer after strtol invocation.
BUG=CID 1401793
TEST=Built and boot up to kernel.
Signed-off-by: John Zhao <john.zhao(a)intel.com>
Change-Id: Idcb48d9a8f7c89744c66f50affb5f9acc6aa4c12
---
M futility/updater.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/vboot refs/changes/21/35021/1
diff --git a/futility/updater.c b/futility/updater.c
index ef142b8..14dd469 100644
--- a/futility/updater.c
+++ b/futility/updater.c
@@ -234,7 +234,7 @@
/* Result should be 'revN' */
if (strncmp(result, STR_REV, strlen(STR_REV)) == 0)
- rev = strtol(result + strlen(STR_REV), NULL, 0);
+ rev = (int)strtol(result + strlen(STR_REV), NULL, 0);
VB2_DEBUG("Raw data = [%s], parsed version is %d\n", result, rev);
free(result);
--
To view, visit https://review.coreboot.org/c/vboot/+/35021
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: vboot
Gerrit-Branch: master
Gerrit-Change-Id: Idcb48d9a8f7c89744c66f50affb5f9acc6aa4c12
Gerrit-Change-Number: 35021
Gerrit-PatchSet: 1
Gerrit-Owner: John Zhao <john.zhao(a)intel.com>
Gerrit-MessageType: newchange
2
2
Change in coreboot[master]: mb/asus/p8h61-m_pro: Fix integrated network
by Angel Pons (Code Review) 03 May '20
by Angel Pons (Code Review) 03 May '20
03 May '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34124 )
Change subject: mb/asus/p8h61-m_pro: Fix integrated network
......................................................................
mb/asus/p8h61-m_pro: Fix integrated network
Looks like this select makes the internal NIC not work. Not sure why,
though.
Change-Id: I92e603c86d9bfe9be9e53918e8f1477a9a1dcf99
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/asus/p8h61-m_pro/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34124/1
diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig
index e8a6f64..d3d1c67 100644
--- a/src/mainboard/asus/p8h61-m_pro/Kconfig
+++ b/src/mainboard/asus/p8h61-m_pro/Kconfig
@@ -31,7 +31,6 @@
select HAVE_CMOS_DEFAULT
select DRIVERS_ASMEDIA_ASPM_BLACKLIST
select MAINBOARD_HAS_LPC_TPM
- select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select INTEL_GMA_HAVE_VBT
--
To view, visit https://review.coreboot.org/c/coreboot/+/34124
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I92e603c86d9bfe9be9e53918e8f1477a9a1dcf99
Gerrit-Change-Number: 34124
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
1
1
Change in coreboot[master]: soc/intel/skylake: Do cosmetic fixes
by Angel Pons (Code Review) 03 May '20
by Angel Pons (Code Review) 03 May '20
03 May '20
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Do cosmetic fixes
......................................................................
soc/intel/skylake: Do cosmetic fixes
This is mostly line reflowing to make use of the increased line length
limit of 96 characters.
Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/elog.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/fspcar.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/acpi.h
M src/soc/intel/skylake/include/soc/cpu.h
M src/soc/intel/skylake/include/soc/gpio.h
M src/soc/intel/skylake/include/soc/gpio_defs.h
M src/soc/intel/skylake/include/soc/iomap.h
M src/soc/intel/skylake/include/soc/nhlt.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/irq.c
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/nhlt/nau88l25.c
M src/soc/intel/skylake/nhlt/rt5514.c
M src/soc/intel/skylake/nhlt/rt5663.c
M src/soc/intel/skylake/p2sb.c
M src/soc/intel/skylake/pmc.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/skylake/reset.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/romstage/systemagent.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/smmrelocate.c
M src/soc/intel/skylake/systemagent.c
M src/soc/intel/skylake/vr_config.c
39 files changed, 561 insertions(+), 1,015 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index ccfc7b7..649220f 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -191,8 +191,7 @@
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
#if CONFIG(EC_GOOGLE_CHROMEEC)
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+ gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
@@ -225,8 +224,7 @@
current = acpi_create_madt_lapics(current);
/* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current);
}
@@ -526,15 +524,13 @@
/* Generate processor \_PR.CPUx */
acpigen_write_processor(
- cpu_id*cores_per_package+core_id,
- pcontrol_blk, plen);
+ cpu_id*cores_per_package+core_id, pcontrol_blk, plen);
/* Generate C-state tables */
generate_c_state_entries(is_s0ix_enable);
if (config->eist_enable) {
/* Generate P-state tables */
- generate_p_state_entries(core_id,
- cores_per_package);
+ generate_p_state_entries(core_id, cores_per_package);
if (config->speed_shift_enable)
acpigen_write_CPPC_method();
}
@@ -569,8 +565,8 @@
/* Add RMRR entry */
tmp = current;
- current += acpi_create_dmar_rmrr(current, 0,
- sa_get_gsm_base(), sa_get_tolud_base() - 1);
+ current += acpi_create_dmar_rmrr(current, 0, sa_get_gsm_base(),
+ sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
}
@@ -606,8 +602,7 @@
return current;
}
-unsigned long northbridge_write_acpi_tables(struct device *const dev,
- unsigned long current,
+unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current,
struct acpi_rsdp *const rsdp)
{
const struct soc_intel_skylake_config *const config = config_of(dev);
@@ -648,12 +643,10 @@
return current;
}
-unsigned long southbridge_write_acpi_tables(struct device *device,
- unsigned long current,
+unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current,
struct acpi_rsdp *rsdp)
{
- current = acpi_write_dbg2_pci_uart(rsdp, current,
- uart_get_device(),
+ current = acpi_write_dbg2_pci_uart(rsdp, current, uart_get_device(),
ACPI_ACCESS_SIZE_DWORD_ACCESS);
current = acpi_write_hpet(device, current, rsdp);
return acpi_align_current(current);
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index e9ca2d8..2b788c6 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corporation..
+ * Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index c95a8d8..1ec9f5d 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -93,19 +93,16 @@
pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);
/*
- * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]
- * to the same value programmed in PMC PCI Offset 48h bit[31:16],
- * this has an implication of making sure the PWRMBASE to be
- * 64KB aligned.
+ * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value
+ * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure
+ * the PWRMBASE to be 64KB aligned.
*
- * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
- * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
- * implication of making sure the memory allocated to PWRMBASE to be
- * 64KB in size.
+ * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value
+ * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure
+ * the memory allocated to PWRMBASE to be 64KB in size.
*/
pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
- ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
- (PCH_PWRM_BASE_ADDRESS >> 16)));
+ ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16)));
if (CONFIG(SKYLAKE_SOC_PCH_H))
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);
else
@@ -116,10 +113,7 @@
{
uint32_t dmi_control;
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
+ /* This cycle decoding is only allowed to set when DMICTL.SRLOCK is 0. */
dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
return -1;
@@ -128,8 +122,7 @@
void pch_early_iorange_init(void)
{
- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
- LPC_IOE_EC_62_66;
+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
/* IO Decode Range */
if (CONFIG(DRIVERS_UART_8250IO))
@@ -152,19 +145,13 @@
void pch_early_init(void)
{
- /*
- * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
- * GPE0_STS, GPE0_EN registers.
- */
+ /* Enable ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, GPE0_STS, GPE0_EN registers. */
soc_config_acpibase();
- /*
- * Enabling PWRM Base for accessing
- * Global Reset Cause Register.
- */
+ /* Enable PWRM Base for accessing Global Reset Cause Register. */
soc_config_pwrmbase();
- /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+ /* Program TCO_BASE_ADDRESS and TCO Timer Halt */
tco_configure();
/* Program SMBUS_BASE_ADDRESS and Enable it */
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 1e65d9a..c7c1c5e 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -94,12 +94,9 @@
{ PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, "Kabylake-U Premium" },
{ PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, "Kabylake-Y Premium" },
{ PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, "Kabylake Super Sku" },
- { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22,
- "Kabylake-Y iHDCP 2.2 Premium" },
- { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22,
- "Kabylake-U iHDCP 2.2 Premium" },
- { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22,
- "Kabylake-U iHDCP 2.2 Base" },
+ { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium" },
+ { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, "Kabylake-U iHDCP 2.2 Premium" },
+ { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, "Kabylake-U iHDCP 2.2 Base" },
};
static struct {
@@ -181,8 +178,7 @@
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
- printk(BIOS_DEBUG,
- "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
}
@@ -269,8 +265,7 @@
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
u32 ch_conf = addr_decode_ch[i];
- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
- i, ch_conf);
+ printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
((ch_conf >> 22) & 1) ? "on" : "off");
printk(BIOS_DEBUG, " rank interleave %s\n",
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index a7d5872..3a6decd 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -100,18 +100,12 @@
sizeof(params->SerialIoDevMode));
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
- params->PortUsb20Enable[i] =
- config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] =
- config->usb2_ports[i].ocpin;
- params->Usb2AfePetxiset[i] =
- config->usb2_ports[i].pre_emp_bias;
- params->Usb2AfeTxiset[i] =
- config->usb2_ports[i].tx_bias;
- params->Usb2AfePredeemp[i] =
- config->usb2_ports[i].tx_emp_enable;
- params->Usb2AfePehalfbit[i] =
- config->usb2_ports[i].pre_emp_bit;
+ params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+ params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
+ params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+ params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
@@ -119,8 +113,7 @@
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
- params->Usb3HsioTxDeEmph[i] =
- config->usb3_ports[i].tx_de_emp;
+ params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
}
if (config->usb3_ports[i].tx_downscale_amp) {
params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
@@ -129,14 +122,12 @@
}
}
- memcpy(params->PcieRpEnable, config->PcieRpEnable,
- sizeof(params->PcieRpEnable));
+ memcpy(params->PcieRpEnable, config->PcieRpEnable, sizeof(params->PcieRpEnable));
memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
sizeof(params->PcieRpClkReqSupport));
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
- memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
- sizeof(params->PcieRpHotPlug));
+ memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug));
params->EnableLan = config->EnableLan;
params->Cio2Enable = config->Cio2Enable;
@@ -178,10 +169,8 @@
if (CONFIG_SUBSYSTEM_DEVICE_ID != 0)
params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
- params->WakeConfigWolEnableOverride =
- config->WakeConfigWolEnableOverride;
- params->WakeConfigPcieWakeFromDeepSx =
- config->WakeConfigPcieWakeFromDeepSx;
+ params->WakeConfigWolEnableOverride = config->WakeConfigWolEnableOverride;
+ params->WakeConfigPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PmConfigDeepSxPol = config->PmConfigDeepSxPol;
params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
@@ -189,14 +178,11 @@
params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert;
params->PmConfigPciClockRun = config->PmConfigPciClockRun;
params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
- params->PmConfigPwrBtnOverridePeriod =
- config->PmConfigPwrBtnOverridePeriod;
+ params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod;
params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF;
- params->SerialIrqConfigSirqMode =
- config->serirq_mode == SERIRQ_CONTINUOUS;
- params->SerialIrqConfigStartFramePulse =
- config->SerialIrqConfigStartFramePulse;
+ params->SerialIrqConfigSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
+ params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
@@ -204,11 +190,9 @@
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/*
- * To disable Heci, the Psf needs to be left unlocked
- * by FSP after end of post sequence. Based on the devicetree
- * setting, we set the appropriate PsfUnlock policy in Fsp,
- * do the changes and then lock it back in coreboot
- *
+ * To disable Heci, the Psf needs to be left unlocked by FSP after end of post
+ * sequence. Based on the devicetree setting, we set the appropriate PsfUnlock
+ * policy in Fsp, do the changes and then lock it back in coreboot.
*/
if (config->HeciEnabled == 0)
params->PsfUnlock = 1;
@@ -249,8 +233,8 @@
/* Display the parameters for SiliconInit */
printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
fsp_display_upd_value("LogoPtr", 4,
- (uint32_t)original->LogoPtr,
- (uint32_t)params->LogoPtr);
+ (uint32_t)original->LogoPtr,
+ (uint32_t)params->LogoPtr);
fsp_display_upd_value("LogoSize", 4,
(uint32_t)original->LogoSize,
(uint32_t)params->LogoSize);
@@ -266,8 +250,7 @@
fsp_display_upd_value("TurboMode", 1,
(uint32_t)original->TurboMode,
(uint32_t)params->TurboMode);
- fsp_display_upd_value("Device4Enable", 1,
- original->Device4Enable,
+ fsp_display_upd_value("Device4Enable", 1, original->Device4Enable,
params->Device4Enable);
fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0],
params->PcieRpEnable[0]);
@@ -309,130 +292,89 @@
params->PcieRpEnable[18]);
fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19],
params->PcieRpEnable[19]);
- fsp_display_upd_value("PcieRpClkReqSupport[0]", 1,
- original->PcieRpClkReqSupport[0],
+ fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, original->PcieRpClkReqSupport[0],
params->PcieRpClkReqSupport[0]);
- fsp_display_upd_value("PcieRpClkReqSupport[1]", 1,
- original->PcieRpClkReqSupport[1],
+ fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, original->PcieRpClkReqSupport[1],
params->PcieRpClkReqSupport[1]);
- fsp_display_upd_value("PcieRpClkReqSupport[2]", 1,
- original->PcieRpClkReqSupport[2],
+ fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, original->PcieRpClkReqSupport[2],
params->PcieRpClkReqSupport[2]);
- fsp_display_upd_value("PcieRpClkReqSupport[3]", 1,
- original->PcieRpClkReqSupport[3],
+ fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, original->PcieRpClkReqSupport[3],
params->PcieRpClkReqSupport[3]);
- fsp_display_upd_value("PcieRpClkReqSupport[4]", 1,
- original->PcieRpClkReqSupport[4],
+ fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, original->PcieRpClkReqSupport[4],
params->PcieRpClkReqSupport[4]);
- fsp_display_upd_value("PcieRpClkReqSupport[5]", 1,
- original->PcieRpClkReqSupport[5],
+ fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, original->PcieRpClkReqSupport[5],
params->PcieRpClkReqSupport[5]);
- fsp_display_upd_value("PcieRpClkReqSupport[6]", 1,
- original->PcieRpClkReqSupport[6],
+ fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, original->PcieRpClkReqSupport[6],
params->PcieRpClkReqSupport[6]);
- fsp_display_upd_value("PcieRpClkReqSupport[7]", 1,
- original->PcieRpClkReqSupport[7],
+ fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, original->PcieRpClkReqSupport[7],
params->PcieRpClkReqSupport[7]);
- fsp_display_upd_value("PcieRpClkReqSupport[8]", 1,
- original->PcieRpClkReqSupport[8],
+ fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, original->PcieRpClkReqSupport[8],
params->PcieRpClkReqSupport[8]);
- fsp_display_upd_value("PcieRpClkReqSupport[9]", 1,
- original->PcieRpClkReqSupport[9],
+ fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, original->PcieRpClkReqSupport[9],
params->PcieRpClkReqSupport[9]);
- fsp_display_upd_value("PcieRpClkReqSupport[10]", 1,
- original->PcieRpClkReqSupport[10],
+ fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, original->PcieRpClkReqSupport[10],
params->PcieRpClkReqSupport[10]);
- fsp_display_upd_value("PcieRpClkReqSupport[11]", 1,
- original->PcieRpClkReqSupport[11],
+ fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, original->PcieRpClkReqSupport[11],
params->PcieRpClkReqSupport[11]);
- fsp_display_upd_value("PcieRpClkReqSupport[12]", 1,
- original->PcieRpClkReqSupport[12],
+ fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, original->PcieRpClkReqSupport[12],
params->PcieRpClkReqSupport[12]);
- fsp_display_upd_value("PcieRpClkReqSupport[13]", 1,
- original->PcieRpClkReqSupport[13],
+ fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, original->PcieRpClkReqSupport[13],
params->PcieRpClkReqSupport[13]);
- fsp_display_upd_value("PcieRpClkReqSupport[14]", 1,
- original->PcieRpClkReqSupport[14],
+ fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, original->PcieRpClkReqSupport[14],
params->PcieRpClkReqSupport[14]);
- fsp_display_upd_value("PcieRpClkReqSupport[15]", 1,
- original->PcieRpClkReqSupport[15],
+ fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, original->PcieRpClkReqSupport[15],
params->PcieRpClkReqSupport[15]);
- fsp_display_upd_value("PcieRpClkReqSupport[16]", 1,
- original->PcieRpClkReqSupport[16],
+ fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, original->PcieRpClkReqSupport[16],
params->PcieRpClkReqSupport[16]);
- fsp_display_upd_value("PcieRpClkReqSupport[17]", 1,
- original->PcieRpClkReqSupport[17],
+ fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, original->PcieRpClkReqSupport[17],
params->PcieRpClkReqSupport[17]);
- fsp_display_upd_value("PcieRpClkReqSupport[18]", 1,
- original->PcieRpClkReqSupport[18],
+ fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, original->PcieRpClkReqSupport[18],
params->PcieRpClkReqSupport[18]);
- fsp_display_upd_value("PcieRpClkReqSupport[19]", 1,
- original->PcieRpClkReqSupport[19],
+ fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, original->PcieRpClkReqSupport[19],
params->PcieRpClkReqSupport[19]);
- fsp_display_upd_value("PcieRpClkReqNumber[0]", 1,
- original->PcieRpClkReqNumber[0],
+ fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, original->PcieRpClkReqNumber[0],
params->PcieRpClkReqNumber[0]);
- fsp_display_upd_value("PcieRpClkReqNumber[1]", 1,
- original->PcieRpClkReqNumber[1],
+ fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, original->PcieRpClkReqNumber[1],
params->PcieRpClkReqNumber[1]);
- fsp_display_upd_value("PcieRpClkReqNumber[2]", 1,
- original->PcieRpClkReqNumber[2],
+ fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, original->PcieRpClkReqNumber[2],
params->PcieRpClkReqNumber[2]);
- fsp_display_upd_value("PcieRpClkReqNumber[3]", 1,
- original->PcieRpClkReqNumber[3],
+ fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, original->PcieRpClkReqNumber[3],
params->PcieRpClkReqNumber[3]);
- fsp_display_upd_value("PcieRpClkReqNumber[4]", 1,
- original->PcieRpClkReqNumber[4],
+ fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, original->PcieRpClkReqNumber[4],
params->PcieRpClkReqNumber[4]);
- fsp_display_upd_value("PcieRpClkReqNumber[5]", 1,
- original->PcieRpClkReqNumber[5],
+ fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, original->PcieRpClkReqNumber[5],
params->PcieRpClkReqNumber[5]);
- fsp_display_upd_value("PcieRpClkReqNumber[6]", 1,
- original->PcieRpClkReqNumber[6],
+ fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, original->PcieRpClkReqNumber[6],
params->PcieRpClkReqNumber[6]);
- fsp_display_upd_value("PcieRpClkReqNumber[7]", 1,
- original->PcieRpClkReqNumber[7],
+ fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, original->PcieRpClkReqNumber[7],
params->PcieRpClkReqNumber[7]);
- fsp_display_upd_value("PcieRpClkReqNumber[8]", 1,
- original->PcieRpClkReqNumber[8],
+ fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, original->PcieRpClkReqNumber[8],
params->PcieRpClkReqNumber[8]);
- fsp_display_upd_value("PcieRpClkReqNumber[9]", 1,
- original->PcieRpClkReqNumber[9],
+ fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, original->PcieRpClkReqNumber[9],
params->PcieRpClkReqNumber[9]);
- fsp_display_upd_value("PcieRpClkReqNumber[10]", 1,
- original->PcieRpClkReqNumber[10],
+ fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, original->PcieRpClkReqNumber[10],
params->PcieRpClkReqNumber[10]);
- fsp_display_upd_value("PcieRpClkReqNumber[11]", 1,
- original->PcieRpClkReqNumber[11],
+ fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, original->PcieRpClkReqNumber[11],
params->PcieRpClkReqNumber[11]);
- fsp_display_upd_value("PcieRpClkReqNumber[12]", 1,
- original->PcieRpClkReqNumber[12],
+ fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, original->PcieRpClkReqNumber[12],
params->PcieRpClkReqNumber[12]);
- fsp_display_upd_value("PcieRpClkReqNumber[13]", 1,
- original->PcieRpClkReqNumber[13],
+ fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, original->PcieRpClkReqNumber[13],
params->PcieRpClkReqNumber[13]);
- fsp_display_upd_value("PcieRpClkReqNumber[14]", 1,
- original->PcieRpClkReqNumber[14],
+ fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, original->PcieRpClkReqNumber[14],
params->PcieRpClkReqNumber[14]);
- fsp_display_upd_value("PcieRpClkReqNumber[15]", 1,
- original->PcieRpClkReqNumber[15],
+ fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, original->PcieRpClkReqNumber[15],
params->PcieRpClkReqNumber[15]);
- fsp_display_upd_value("PcieRpClkReqNumber[16]", 1,
- original->PcieRpClkReqNumber[16],
+ fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, original->PcieRpClkReqNumber[16],
params->PcieRpClkReqNumber[16]);
- fsp_display_upd_value("PcieRpClkReqNumber[17]", 1,
- original->PcieRpClkReqNumber[17],
+ fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, original->PcieRpClkReqNumber[17],
params->PcieRpClkReqNumber[17]);
- fsp_display_upd_value("PcieRpClkReqNumber[18]", 1,
- original->PcieRpClkReqNumber[18],
+ fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, original->PcieRpClkReqNumber[18],
params->PcieRpClkReqNumber[18]);
- fsp_display_upd_value("PcieRpClkReqNumber[19]", 1,
- original->PcieRpClkReqNumber[19],
+ fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, original->PcieRpClkReqNumber[19],
params->PcieRpClkReqNumber[19]);
- fsp_display_upd_value("EnableLan", 1, original->EnableLan,
- params->EnableLan);
- fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable,
- params->Cio2Enable);
+
+ fsp_display_upd_value("EnableLan", 1, original->EnableLan, params->EnableLan);
+ fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, params->Cio2Enable);
fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport,
params->SataSalpSupport);
fsp_display_upd_value("SataPortsEnable[0]", 1,
@@ -467,10 +409,8 @@
original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]);
fsp_display_upd_value("SataPortsDevSlp[7]", 1,
original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]);
- fsp_display_upd_value("EnableAzalia", 1,
- original->EnableAzalia, params->EnableAzalia);
- fsp_display_upd_value("DspEnable", 1, original->DspEnable,
- params->DspEnable);
+ fsp_display_upd_value("EnableAzalia", 1, original->EnableAzalia, params->EnableAzalia);
+ fsp_display_upd_value("DspEnable", 1, original->DspEnable, params->DspEnable);
fsp_display_upd_value("IoBufferOwnership", 1,
original->IoBufferOwnership, params->IoBufferOwnership);
fsp_display_upd_value("PortUsb20Enable[0]", 1,
@@ -525,12 +465,10 @@
original->PortUsb30Enable[8], params->PortUsb30Enable[8]);
fsp_display_upd_value("PortUsb30Enable[9]", 1,
original->PortUsb30Enable[9], params->PortUsb30Enable[9]);
- fsp_display_upd_value("XdciEnable", 1, original->XdciEnable,
- params->XdciEnable);
- fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable,
- params->SsicPortEnable);
- fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable,
- params->SmbusEnable);
+ fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, params->XdciEnable);
+ fsp_display_upd_value("SsicPortEnable", 1,
+ original->SsicPortEnable, params->SsicPortEnable);
+ fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, params->SmbusEnable);
fsp_display_upd_value("SerialIoDevMode[0]", 1,
original->SerialIoDevMode[0], params->SerialIoDevMode[0]);
fsp_display_upd_value("SerialIoDevMode[1]", 1,
@@ -559,10 +497,9 @@
original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled);
fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled,
params->ScsSdCardEnabled);
- fsp_display_upd_value("IshEnable", 1, original->IshEnable,
- params->IshEnable);
- fsp_display_upd_value("ShowSpiController", 1,
- original->ShowSpiController, params->ShowSpiController);
+ fsp_display_upd_value("IshEnable", 1, original->IshEnable, params->IshEnable);
+ fsp_display_upd_value("ShowSpiController", 1, original->ShowSpiController,
+ params->ShowSpiController);
fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging,
params->HsioMessaging);
fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled,
@@ -571,45 +508,28 @@
params->EnableSata);
fsp_display_upd_value("SataMode", 1, original->SataMode,
params->SataMode);
- fsp_display_upd_value("NumOfDevIntConfig", 1,
- original->NumOfDevIntConfig,
+ fsp_display_upd_value("NumOfDevIntConfig", 1, original->NumOfDevIntConfig,
params->NumOfDevIntConfig);
- fsp_display_upd_value("PxRcConfig[PARC]", 1,
- original->PxRcConfig[PCH_PARC],
+ fsp_display_upd_value("PxRcConfig[PARC]", 1, original->PxRcConfig[PCH_PARC],
params->PxRcConfig[PCH_PARC]);
- fsp_display_upd_value("PxRcConfig[PBRC]", 1,
- original->PxRcConfig[PCH_PBRC],
+ fsp_display_upd_value("PxRcConfig[PBRC]", 1, original->PxRcConfig[PCH_PBRC],
params->PxRcConfig[PCH_PBRC]);
- fsp_display_upd_value("PxRcConfig[PCRC]", 1,
- original->PxRcConfig[PCH_PCRC],
+ fsp_display_upd_value("PxRcConfig[PCRC]", 1, original->PxRcConfig[PCH_PCRC],
params->PxRcConfig[PCH_PCRC]);
- fsp_display_upd_value("PxRcConfig[PDRC]", 1,
- original->PxRcConfig[PCH_PDRC],
+ fsp_display_upd_value("PxRcConfig[PDRC]", 1, original->PxRcConfig[PCH_PDRC],
params->PxRcConfig[PCH_PDRC]);
- fsp_display_upd_value("PxRcConfig[PERC]", 1,
- original->PxRcConfig[PCH_PERC],
+ fsp_display_upd_value("PxRcConfig[PERC]", 1, original->PxRcConfig[PCH_PERC],
params->PxRcConfig[PCH_PERC]);
- fsp_display_upd_value("PxRcConfig[PFRC]", 1,
- original->PxRcConfig[PCH_PFRC],
+ fsp_display_upd_value("PxRcConfig[PFRC]", 1, original->PxRcConfig[PCH_PFRC],
params->PxRcConfig[PCH_PFRC]);
- fsp_display_upd_value("PxRcConfig[PGRC]", 1,
- original->PxRcConfig[PCH_PGRC],
+ fsp_display_upd_value("PxRcConfig[PGRC]", 1, original->PxRcConfig[PCH_PGRC],
params->PxRcConfig[PCH_PGRC]);
- fsp_display_upd_value("PxRcConfig[PHRC]", 1,
- original->PxRcConfig[PCH_PHRC],
+ fsp_display_upd_value("PxRcConfig[PHRC]", 1, original->PxRcConfig[PCH_PHRC],
params->PxRcConfig[PCH_PHRC]);
- fsp_display_upd_value("GpioIrqRoute", 1,
- original->GpioIrqRoute,
- params->GpioIrqRoute);
- fsp_display_upd_value("SciIrqSelect", 1,
- original->SciIrqSelect,
- params->SciIrqSelect);
- fsp_display_upd_value("TcoIrqSelect", 1,
- original->TcoIrqSelect,
- params->TcoIrqSelect);
- fsp_display_upd_value("TcoIrqEnable", 1,
- original->TcoIrqEnable,
- params->TcoIrqEnable);
+ fsp_display_upd_value("GpioIrqRoute", 1, original->GpioIrqRoute, params->GpioIrqRoute);
+ fsp_display_upd_value("SciIrqSelect", 1, original->SciIrqSelect, params->SciIrqSelect);
+ fsp_display_upd_value("TcoIrqSelect", 1, original->TcoIrqSelect, params->TcoIrqSelect);
+ fsp_display_upd_value("TcoIrqEnable", 1, original->TcoIrqEnable, params->TcoIrqEnable);
fsp_display_upd_value("LockDownConfigGlobalSmi", 1,
original->LockDownConfigGlobalSmi,
params->LockDownConfigGlobalSmi);
@@ -674,190 +594,127 @@
original->SerialIrqConfigStartFramePulse,
params->SerialIrqConfigStartFramePulse);
- fsp_display_upd_value("Psi1Threshold[0]", 1,
- original->Psi1Threshold[0],
+ fsp_display_upd_value("Psi1Threshold[0]", 1, original->Psi1Threshold[0],
params->Psi1Threshold[0]);
- fsp_display_upd_value("Psi1Threshold[1]", 1,
- original->Psi1Threshold[1],
+ fsp_display_upd_value("Psi1Threshold[1]", 1, original->Psi1Threshold[1],
params->Psi1Threshold[1]);
- fsp_display_upd_value("Psi1Threshold[2]", 1,
- original->Psi1Threshold[2],
+ fsp_display_upd_value("Psi1Threshold[2]", 1, original->Psi1Threshold[2],
params->Psi1Threshold[2]);
- fsp_display_upd_value("Psi1Threshold[3]", 1,
- original->Psi1Threshold[3],
+ fsp_display_upd_value("Psi1Threshold[3]", 1, original->Psi1Threshold[3],
params->Psi1Threshold[3]);
- fsp_display_upd_value("Psi1Threshold[4]", 1,
- original->Psi1Threshold[4],
+ fsp_display_upd_value("Psi1Threshold[4]", 1, original->Psi1Threshold[4],
params->Psi1Threshold[4]);
- fsp_display_upd_value("Psi2Threshold[0]", 1,
- original->Psi2Threshold[0],
+ fsp_display_upd_value("Psi2Threshold[0]", 1, original->Psi2Threshold[0],
params->Psi2Threshold[0]);
- fsp_display_upd_value("Psi2Threshold[1]", 1,
- original->Psi2Threshold[1],
+ fsp_display_upd_value("Psi2Threshold[1]", 1, original->Psi2Threshold[1],
params->Psi2Threshold[1]);
- fsp_display_upd_value("Psi2Threshold[2]", 1,
- original->Psi2Threshold[2],
+ fsp_display_upd_value("Psi2Threshold[2]", 1, original->Psi2Threshold[2],
params->Psi2Threshold[2]);
- fsp_display_upd_value("Psi2Threshold[3]", 1,
- original->Psi2Threshold[3],
+ fsp_display_upd_value("Psi2Threshold[3]", 1, original->Psi2Threshold[3],
params->Psi2Threshold[3]);
- fsp_display_upd_value("Psi2Threshold[4]", 1,
- original->Psi2Threshold[4],
+ fsp_display_upd_value("Psi2Threshold[4]", 1, original->Psi2Threshold[4],
params->Psi2Threshold[4]);
- fsp_display_upd_value("Psi3Threshold[0]", 1,
- original->Psi3Threshold[0],
+ fsp_display_upd_value("Psi3Threshold[0]", 1, original->Psi3Threshold[0],
params->Psi3Threshold[0]);
- fsp_display_upd_value("Psi3Threshold[1]", 1,
- original->Psi3Threshold[1],
+ fsp_display_upd_value("Psi3Threshold[1]", 1, original->Psi3Threshold[1],
params->Psi3Threshold[1]);
- fsp_display_upd_value("Psi3Threshold[2]", 1,
- original->Psi3Threshold[2],
+ fsp_display_upd_value("Psi3Threshold[2]", 1, original->Psi3Threshold[2],
params->Psi3Threshold[2]);
- fsp_display_upd_value("Psi3Threshold[3]", 1,
- original->Psi3Threshold[3],
+ fsp_display_upd_value("Psi3Threshold[3]", 1, original->Psi3Threshold[3],
params->Psi3Threshold[3]);
- fsp_display_upd_value("Psi3Threshold[4]", 1,
- original->Psi3Threshold[4],
+ fsp_display_upd_value("Psi3Threshold[4]", 1, original->Psi3Threshold[4],
params->Psi3Threshold[4]);
- fsp_display_upd_value("Psi3Enable[0]", 1,
- original->Psi3Enable[0],
+ fsp_display_upd_value("Psi3Enable[0]", 1, original->Psi3Enable[0],
params->Psi3Enable[0]);
- fsp_display_upd_value("Psi3Enable[1]", 1,
- original->Psi3Enable[1],
+ fsp_display_upd_value("Psi3Enable[1]", 1, original->Psi3Enable[1],
params->Psi3Enable[1]);
- fsp_display_upd_value("Psi3Enable[2]", 1,
- original->Psi3Enable[2],
+ fsp_display_upd_value("Psi3Enable[2]", 1, original->Psi3Enable[2],
params->Psi3Enable[2]);
- fsp_display_upd_value("Psi3Enable[3]", 1,
- original->Psi3Enable[3],
+ fsp_display_upd_value("Psi3Enable[3]", 1, original->Psi3Enable[3],
params->Psi3Enable[3]);
- fsp_display_upd_value("Psi3Enable[4]", 1,
- original->Psi3Enable[4],
+ fsp_display_upd_value("Psi3Enable[4]", 1, original->Psi3Enable[4],
params->Psi3Enable[4]);
- fsp_display_upd_value("Psi4Enable[0]", 1,
- original->Psi4Enable[0],
+ fsp_display_upd_value("Psi4Enable[0]", 1, original->Psi4Enable[0],
params->Psi4Enable[0]);
- fsp_display_upd_value("Psi4Enable[1]", 1,
- original->Psi4Enable[1],
+ fsp_display_upd_value("Psi4Enable[1]", 1, original->Psi4Enable[1],
params->Psi4Enable[1]);
- fsp_display_upd_value("Psi4Enable[2]", 1,
- original->Psi4Enable[2],
+ fsp_display_upd_value("Psi4Enable[2]", 1, original->Psi4Enable[2],
params->Psi4Enable[2]);
- fsp_display_upd_value("Psi4Enable[3]", 1,
- original->Psi4Enable[3],
+ fsp_display_upd_value("Psi4Enable[3]", 1, original->Psi4Enable[3],
params->Psi4Enable[3]);
- fsp_display_upd_value("Psi4Enable[4]", 1,
- original->Psi4Enable[4],
+ fsp_display_upd_value("Psi4Enable[4]", 1, original->Psi4Enable[4],
params->Psi4Enable[4]);
- fsp_display_upd_value("ImonSlope[0]", 1,
- original->ImonSlope[0],
+ fsp_display_upd_value("ImonSlope[0]", 1, original->ImonSlope[0],
params->ImonSlope[0]);
- fsp_display_upd_value("ImonSlope[1]", 1,
- original->ImonSlope[1],
+ fsp_display_upd_value("ImonSlope[1]", 1, original->ImonSlope[1],
params->ImonSlope[1]);
- fsp_display_upd_value("ImonSlope[2]", 1,
- original->ImonSlope[2],
+ fsp_display_upd_value("ImonSlope[2]", 1, original->ImonSlope[2],
params->ImonSlope[2]);
- fsp_display_upd_value("ImonSlope[3]", 1,
- original->ImonSlope[3],
+ fsp_display_upd_value("ImonSlope[3]", 1, original->ImonSlope[3],
params->ImonSlope[3]);
- fsp_display_upd_value("ImonSlope[4]", 1,
- original->ImonSlope[4],
+ fsp_display_upd_value("ImonSlope[4]", 1, original->ImonSlope[4],
params->ImonSlope[4]);
- fsp_display_upd_value("ImonOffse[0]t", 1,
- original->ImonOffset[0],
+ fsp_display_upd_value("ImonOffse[0]t", 1, original->ImonOffset[0],
params->ImonOffset[0]);
- fsp_display_upd_value("ImonOffse[1]t", 1,
- original->ImonOffset[1],
+ fsp_display_upd_value("ImonOffse[1]t", 1, original->ImonOffset[1],
params->ImonOffset[1]);
- fsp_display_upd_value("ImonOffse[2]t", 1,
- original->ImonOffset[2],
+ fsp_display_upd_value("ImonOffse[2]t", 1, original->ImonOffset[2],
params->ImonOffset[2]);
- fsp_display_upd_value("ImonOffse[3]t", 1,
- original->ImonOffset[3],
+ fsp_display_upd_value("ImonOffse[3]t", 1, original->ImonOffset[3],
params->ImonOffset[3]);
- fsp_display_upd_value("ImonOffse[4]t", 1,
- original->ImonOffset[4],
+ fsp_display_upd_value("ImonOffse[4]t", 1, original->ImonOffset[4],
params->ImonOffset[4]);
- fsp_display_upd_value("IccMax[0]", 1,
- original->IccMax[0],
+ fsp_display_upd_value("IccMax[0]", 1, original->IccMax[0],
params->IccMax[0]);
- fsp_display_upd_value("IccMax[1]", 1,
- original->IccMax[1],
+ fsp_display_upd_value("IccMax[1]", 1, original->IccMax[1],
params->IccMax[1]);
- fsp_display_upd_value("IccMax[2]", 1,
- original->IccMax[2],
+ fsp_display_upd_value("IccMax[2]", 1, original->IccMax[2],
params->IccMax[2]);
- fsp_display_upd_value("IccMax[3]", 1,
- original->IccMax[3],
+ fsp_display_upd_value("IccMax[3]", 1, original->IccMax[3],
params->IccMax[3]);
- fsp_display_upd_value("IccMax[4]", 1,
- original->IccMax[4],
+ fsp_display_upd_value("IccMax[4]", 1, original->IccMax[4],
params->IccMax[4]);
- fsp_display_upd_value("VrVoltageLimit[0]", 1,
- original->VrVoltageLimit[0],
+ fsp_display_upd_value("VrVoltageLimit[0]", 1, original->VrVoltageLimit[0],
params->VrVoltageLimit[0]);
- fsp_display_upd_value("VrVoltageLimit[1]", 1,
- original->VrVoltageLimit[1],
+ fsp_display_upd_value("VrVoltageLimit[1]", 1, original->VrVoltageLimit[1],
params->VrVoltageLimit[1]);
- fsp_display_upd_value("VrVoltageLimit[2]", 1,
- original->VrVoltageLimit[2],
+ fsp_display_upd_value("VrVoltageLimit[2]", 1, original->VrVoltageLimit[2],
params->VrVoltageLimit[2]);
- fsp_display_upd_value("VrVoltageLimit[3]", 1,
- original->VrVoltageLimit[3],
+ fsp_display_upd_value("VrVoltageLimit[3]", 1, original->VrVoltageLimit[3],
params->VrVoltageLimit[3]);
- fsp_display_upd_value("VrVoltageLimit[4]", 1,
- original->VrVoltageLimit[4],
+ fsp_display_upd_value("VrVoltageLimit[4]", 1, original->VrVoltageLimit[4],
params->VrVoltageLimit[4]);
- fsp_display_upd_value("VrConfigEnable[0]", 1,
- original->VrConfigEnable[0],
+ fsp_display_upd_value("VrConfigEnable[0]", 1, original->VrConfigEnable[0],
params->VrConfigEnable[0]);
- fsp_display_upd_value("VrConfigEnable[1]", 1,
- original->VrConfigEnable[1],
+ fsp_display_upd_value("VrConfigEnable[1]", 1, original->VrConfigEnable[1],
params->VrConfigEnable[1]);
- fsp_display_upd_value("VrConfigEnable[2]", 1,
- original->VrConfigEnable[2],
+ fsp_display_upd_value("VrConfigEnable[2]", 1, original->VrConfigEnable[2],
params->VrConfigEnable[2]);
- fsp_display_upd_value("VrConfigEnable[3]", 1,
- original->VrConfigEnable[3],
+ fsp_display_upd_value("VrConfigEnable[3]", 1, original->VrConfigEnable[3],
params->VrConfigEnable[3]);
- fsp_display_upd_value("VrConfigEnable[4]", 1,
- original->VrConfigEnable[4],
+ fsp_display_upd_value("VrConfigEnable[4]", 1, original->VrConfigEnable[4],
params->VrConfigEnable[4]);
- fsp_display_upd_value("SerialIoI2cVoltage[0]", 1,
- original->SerialIoI2cVoltage[0],
+ fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, original->SerialIoI2cVoltage[0],
params->SerialIoI2cVoltage[0]);
- fsp_display_upd_value("SerialIoI2cVoltage[1]", 1,
- original->SerialIoI2cVoltage[1],
+ fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, original->SerialIoI2cVoltage[1],
params->SerialIoI2cVoltage[1]);
- fsp_display_upd_value("SerialIoI2cVoltage[2]", 1,
- original->SerialIoI2cVoltage[2],
+ fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, original->SerialIoI2cVoltage[2],
params->SerialIoI2cVoltage[2]);
- fsp_display_upd_value("SerialIoI2cVoltage[3]", 1,
- original->SerialIoI2cVoltage[3],
+ fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, original->SerialIoI2cVoltage[3],
params->SerialIoI2cVoltage[3]);
- fsp_display_upd_value("SerialIoI2cVoltage[4]", 1,
- original->SerialIoI2cVoltage[4],
+ fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, original->SerialIoI2cVoltage[4],
params->SerialIoI2cVoltage[4]);
- fsp_display_upd_value("SerialIoI2cVoltage[5]", 1,
- original->SerialIoI2cVoltage[5],
+ fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, original->SerialIoI2cVoltage[5],
params->SerialIoI2cVoltage[5]);
- fsp_display_upd_value("SendVrMbxCmd", 1,
- original->SendVrMbxCmd,
- params->SendVrMbxCmd);
- fsp_display_upd_value("AcousticNoiseMitigation", 1,
- original->AcousticNoiseMitigation,
+ fsp_display_upd_value("SendVrMbxCmd", 1, original->SendVrMbxCmd, params->SendVrMbxCmd);
+ fsp_display_upd_value("AcousticNoiseMitigation", 1, original->AcousticNoiseMitigation,
params->AcousticNoiseMitigation);
- fsp_display_upd_value("SlowSlewRateForIa", 1,
- original->SlowSlewRateForIa,
+ fsp_display_upd_value("SlowSlewRateForIa", 1, original->SlowSlewRateForIa,
params->SlowSlewRateForIa);
- fsp_display_upd_value("SlowSlewRateForGt", 1,
- original->SlowSlewRateForGt,
+ fsp_display_upd_value("SlowSlewRateForGt", 1, original->SlowSlewRateForGt,
params->SlowSlewRateForGt);
- fsp_display_upd_value("SlowSlewRateForSa", 1,
- original->SlowSlewRateForSa,
+ fsp_display_upd_value("SlowSlewRateForSa", 1, original->SlowSlewRateForSa,
params->SlowSlewRateForSa);
- fsp_display_upd_value("FastPkgCRampDisable", 1,
- original->FastPkgCRampDisable,
+ fsp_display_upd_value("FastPkgCRampDisable", 1, original->FastPkgCRampDisable,
params->FastPkgCRampDisable);
}
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 1313dc1..1dbe590 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -142,8 +142,7 @@
/*
* The following fields come from FspUpdVpd.h.
- * These are configuration values that are passed to FSP during
- * MemoryInit.
+ * These are configuration values that are passed to FSP during MemoryInit.
*/
u64 PlatformMemorySize;
u8 SmramMask;
@@ -191,9 +190,8 @@
/* SATA related */
u8 EnableSata;
enum {
- /* Documentation and header files of Skylake FSP disagree on
- the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses
- these: */
+ /* Documentation and header files of Skylake FSP disagree on the values,
+ * Kaby Lake FSP (KabylakeFsp0001 on github) uses these: */
KBLFSP_SATA_MODE_AHCI = 0,
KBLFSP_SATA_MODE_RAID = 1,
} SataMode;
@@ -224,8 +222,7 @@
/*
* Pcie Root Port configuration:
- * each element of array corresponds to
- * respective PCIe root port.
+ * each element of array corresponds to respective PCIe root port.
*/
/* PEG Max Link Width */
@@ -361,8 +358,7 @@
/*
* The following fields come from fsp_vpd.h
- * These are configuration values that are passed to FSP during
- * SiliconInit.
+ * These are configuration values that are passed to FSP during SiliconInit.
*/
u32 LogoPtr;
u32 LogoSize;
@@ -446,8 +442,7 @@
*/
u8 PmConfigPciClockRun;
/*
- * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
- * 1: Enabled
+ * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled
*/
u8 PmConfigSlpStrchSusUp;
/*
@@ -481,8 +476,7 @@
/*
* VrConfig Settings for 5 domains
- * 0 = System Agent, 1 = IA Core, 2 = Ring,
- * 3 = GT unsliced, 4 = GT sliced
+ * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
/*
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 064f71e..87bf644 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -86,14 +86,11 @@
};
/*
- * If the PCIe root port at function 0 is disabled,
- * the PCIe root ports might be coalesced after FSP silicon init.
- * The below function will swap the devfn of the first enabled device
- * in devicetree and function 0 resides a pci device
- * so that it won't confuse coreboot.
+ * If the PCIe root port at function 0 is disabled, the PCIe root ports might be coalesced
+ * after FSP silicon init. The below function will swap the devfn of the first enabled device
+ * in devicetree and function 0 resides a pci device so that it won't confuse coreboot.
*/
-static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group,
- size_t pci_groups)
+static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, size_t pci_groups)
{
struct device *func0;
unsigned int devfn, devfn0;
@@ -117,18 +114,13 @@
* Then find first enabled device to replace func0
* as that port was move to func0.
*/
- for (i = 1; i < pcie_rp_group[group].func_count;
- i++, devfn += inc) {
+ for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) {
struct device *dev = pcidev_path_on_root(devfn);
if (dev == NULL || !dev->enabled)
continue;
- /*
- * Found the first enabled device in
- * a given dev number.
- */
- printk(BIOS_INFO, "PCI func %d was swapped"
- " to func 0.\n", i);
+ /* Found the first enabled device in a given dev number. */
+ printk(BIOS_INFO, "PCI func %d was swapped to func 0.\n", i);
func0->path.pci.devfn = dev->path.pci.devfn;
dev->path.pci.devfn = devfn0;
break;
@@ -160,8 +152,7 @@
pcie_update_device_tree(&pcie_table_skl_pch_h[0],
ARRAY_SIZE(pcie_table_skl_pch_h));
} else {
- printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x"
- " is not found\n", id);
+ printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x is not found\n", id);
return;
}
}
@@ -250,18 +241,12 @@
params->GraphicsConfigPtr = (u32) vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
- params->PortUsb20Enable[i] =
- config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] =
- config->usb2_ports[i].ocpin;
- params->Usb2AfePetxiset[i] =
- config->usb2_ports[i].pre_emp_bias;
- params->Usb2AfeTxiset[i] =
- config->usb2_ports[i].tx_bias;
- params->Usb2AfePredeemp[i] =
- config->usb2_ports[i].tx_emp_enable;
- params->Usb2AfePehalfbit[i] =
- config->usb2_ports[i].pre_emp_bit;
+ params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+ params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
+ params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+ params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
@@ -269,8 +254,7 @@
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
- params->Usb3HsioTxDeEmph[i] =
- config->usb3_ports[i].tx_de_emp;
+ params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
}
if (config->usb3_ports[i].tx_downscale_amp) {
params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
@@ -287,23 +271,20 @@
sizeof(params->PcieRpClkReqSupport));
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
- memcpy(params->PcieRpAdvancedErrorReporting,
- config->PcieRpAdvancedErrorReporting,
- sizeof(params->PcieRpAdvancedErrorReporting));
+ memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting,
+ sizeof(params->PcieRpAdvancedErrorReporting));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(params->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
/*
- * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
- * all the enabled PCIe root ports, invalid(0x1F) is set for
- * disabled PCIe root ports.
+ * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for all the enabled
+ * PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports.
*/
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
if (config->PcieRpClkReqSupport[i])
- params->PcieRpClkSrcNumber[i] =
- config->PcieRpClkSrcNumber[i];
+ params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i];
else
params->PcieRpClkSrcNumber[i] = 0x1F;
}
@@ -344,12 +325,9 @@
params->ScsSdCardEnabled = config->ScsSdCardEnabled;
if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) {
- params->PchScsEmmcHs400DllDataValid =
- !!config->EmmcHs400DllNeed;
- params->PchScsEmmcHs400RxStrobeDll1 =
- config->ScsEmmcHs400RxStrobeDll1;
- params->PchScsEmmcHs400TxDataDll =
- config->ScsEmmcHs400TxDataDll;
+ params->PchScsEmmcHs400DllDataValid = !!config->EmmcHs400DllNeed;
+ params->PchScsEmmcHs400RxStrobeDll1 = config->ScsEmmcHs400RxStrobeDll1;
+ params->PchScsEmmcHs400TxDataDll = config->ScsEmmcHs400TxDataDll;
}
/* If ISH is enabled, enable ISH elements */
@@ -373,9 +351,8 @@
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
tconfig->PowerLimit4 = config->PowerLimit4;
/*
- * To disable HECI, the Psf needs to be left unlocked
- * by FSP till end of post sequence. Based on the devicetree
- * setting, we set the appropriate PsfUnlock policy in FSP,
+ * To disable HECI, the Psf needs to be left unlocked by FSP till end of post sequence.
+ * Based on the devicetree setting, we set the appropriate PsfUnlock policy in FSP,
* do the changes and then lock it back in coreboot during finalize.
*/
tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
@@ -384,7 +361,7 @@
params->PchLockDownBiosLock = 0;
params->PchLockDownSpiEiss = 0;
/*
- * Skip Spi Flash Lockdown from inside FSP.
+ * Skip SPI Flash Lockdown from inside FSP.
* Making this config "0" means FSP won't set the FLOCKDN bit
* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
* So, it becomes coreboot's responsibility to set this bit
@@ -413,8 +390,7 @@
params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert;
params->PchPmLpcClockRun = config->PmConfigPciClockRun;
params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
- params->PchPmPwrBtnOverridePeriod =
- config->PmConfigPwrBtnOverridePeriod;
+ params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod;
params->PchPmPwrCycDur = config->PmConfigPwrCycDur;
/* Indicate whether platform supports Voltage Margining */
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0d49d28..c551df8 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -151,8 +151,7 @@
/* Set long term power limit to TDP */
limit.lo = 0;
- tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
- tdp : (conf->tdp_pl1_override * power_unit));
+ tdp_pl1 = ((conf->tdp_pl1_override == 0) ? tdp : (conf->tdp_pl1_override * power_unit));
limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
/* Set PL1 Pkg Power clamp bit */
@@ -182,10 +181,8 @@
if (conf->tdp_psyspl2) {
limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
limit.hi = 0;
- printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n",
- conf->tdp_psyspl2);
- limit.hi |= (conf->tdp_psyspl2 * power_unit) &
- PKG_POWER_LIMIT_MASK;
+ printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", conf->tdp_psyspl2);
+ limit.hi |= (conf->tdp_psyspl2 * power_unit) & PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN;
@@ -196,20 +193,16 @@
if (conf->tdp_psyspl3) {
limit = rdmsr(MSR_PL3_CONTROL);
limit.lo = 0;
- printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
- conf->tdp_psyspl3);
- limit.lo |= (conf->tdp_psyspl3 * power_unit) &
- PKG_POWER_LIMIT_MASK;
+ printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", conf->tdp_psyspl3);
+ limit.lo |= (conf->tdp_psyspl3 * power_unit) & PKG_POWER_LIMIT_MASK;
/* Enable PsysPl3 */
limit.lo |= PKG_POWER_LIMIT_EN;
/* set PsysPl3 time window */
limit.lo |= (conf->tdp_psyspl3_time &
- PKG_POWER_LIMIT_TIME_MASK) <<
- PKG_POWER_LIMIT_TIME_SHIFT;
+ PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
/* set PsysPl3 duty cycle */
limit.lo |= (conf->tdp_psyspl3_dutycycle &
- PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
- PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
+ PKG_POWER_LIMIT_DUTYCYCLE_MASK) << PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
wrmsr(MSR_PL3_CONTROL, limit);
}
@@ -217,10 +210,8 @@
if (conf->tdp_pl4) {
limit = rdmsr(MSR_VR_CURRENT_CONFIG);
limit.lo = 0;
- printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
- conf->tdp_pl4);
- limit.lo |= (conf->tdp_pl4 * power_unit) &
- PKG_POWER_LIMIT_MASK;
+ printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", conf->tdp_pl4);
+ limit.lo |= (conf->tdp_pl4 * power_unit) & PKG_POWER_LIMIT_MASK;
wrmsr(MSR_VR_CURRENT_CONFIG, limit);
}
@@ -382,20 +373,17 @@
/* C-state Interrupt Response Latency Control 3 - package C8 */
msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS |
- C_STATE_LATENCY_CONTROL_3_LIMIT;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */
msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS |
- C_STATE_LATENCY_CONTROL_4_LIMIT;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */
msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS |
- C_STATE_LATENCY_CONTROL_5_LIMIT;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
@@ -410,8 +398,7 @@
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable*/
@@ -424,9 +411,10 @@
void soc_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
- /* TODO(adurbin): This should only be done on a cold boot. Also, some
- * of these banks are core vs package scope. For now every CPU clears
- * every bank. */
+ /*
+ * TODO(adurbin): This should only be done on a cold boot. Also, some of these
+ * banks are core vs package scope. For now every CPU clears every bank.
+ */
mca_configure();
/* Enable the local CPU apics */
@@ -481,10 +469,7 @@
/* Set Max Ratio */
cpu_set_max_ratio();
- /*
- * Now that all APs have been relocated as well as the BSP let SMIs
- * start flowing.
- */
+ /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */
smm_southbridge_enable(GBL_EN);
/* Lock down the SMRAM space. */
@@ -503,9 +488,8 @@
static const struct mp_ops mp_ops = {
/*
- * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
- * that are set prior to ramstage.
- * Real MTRRs programming are being done after resource allocation.
+ * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, that are set
+ * prior to ramstage. Real MTRRs programming are being done after resource allocation.
*/
.pre_mp_init = soc_fsp_load,
.get_cpu_count = get_cpu_count,
@@ -545,8 +529,7 @@
if (msr2.lo && (current_patch_id == new_patch_id - 1))
return 0;
else
- return (msr1.lo & PRMRR_SUPPORTED) &&
- (current_patch_id == new_patch_id - 1);
+ return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
}
void cpu_lock_sgx_memory(void)
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index 47d6137..2bf9c52 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -52,19 +52,13 @@
#define PME_STS_BIT (1 << 15)
#ifdef __SIMPLE_DEVICE__
-static void pch_log_add_elog_event(const struct pme_status_info *info,
- pci_devfn_t dev)
+static void pch_log_add_elog_event(const struct pme_status_info *info, pci_devfn_t dev)
#else
-static void pch_log_add_elog_event(const struct pme_status_info *info,
- struct device *dev)
+static void pch_log_add_elog_event(const struct pme_status_info *info, struct device *dev)
#endif
{
- /*
- * If wake source is XHCI, check for detailed wake source events on
- * USB2/3 ports.
- */
- if ((info->dev == PCH_DEV_XHCI) &&
- pch_xhci_update_wake_event(soc_get_xhci_usb_info()))
+ /* If wake source is XHCI, check for detailed wake source events on USB2/3 ports. */
+ if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(soc_get_xhci_usb_info()))
return;
elog_add_event_wake(info->elog_event, 0);
@@ -105,11 +99,10 @@
}
/*
- * If device is still not found, but the wake source is internal PME,
- * try probing XHCI ports to see if any of the USB2/3 ports indicate
- * that it was the wake source. This path would be taken in case of GSMI
- * logging with S0ix where the pci_pm_resume_noirq runs and clears the
- * PME_STS_BIT in controller register.
+ * If device is still not found, but the wake source is internal PME, try probing XHCI
+ * ports to see if any of the USB2/3 ports indicate that it was the wake source. This
+ * path would be taken in case of GSMI logging with S0ix where the pci_pm_resume_noirq
+ * runs and clears the PME_STS_BIT in controller register.
*/
if (!dev_found)
dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info());
@@ -155,10 +148,7 @@
if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT))
continue;
- /*
- * Linux kernel uses PME STS bit information. So do not clear
- * this bit.
- */
+ /* Linux kernel uses PME STS bit information. So do not clear this bit. */
pch_log_add_elog_event(&pme_status_info[i], dev);
}
}
@@ -234,8 +224,7 @@
}
/* TCO Timeout */
- if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
+ if (ps->prev_sleep_state != ACPI_S3 && ps->tco2_sts & TCO_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
@@ -253,11 +242,9 @@
/* ACPI Wake Event */
if (ps->prev_sleep_state != ACPI_S0) {
if (deep_sx)
- elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE,
- ps->prev_sleep_state);
+ elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, ps->prev_sleep_state);
else
- elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- ps->prev_sleep_state);
+ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
}
}
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 8afaf4d..633c347 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -79,8 +79,7 @@
config = config_of(dev);
/*
- * Set low maximum temp value used for dynamic thermal sensor
- * shutdown consideration.
+ * Set low maximum temp value used for dynamic thermal sensor shutdown consideration.
*
* If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
* thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c
index a4c3726..b5d5e33 100644
--- a/src/soc/intel/skylake/fspcar.c
+++ b/src/soc/intel/skylake/fspcar.c
@@ -23,12 +23,9 @@
.Reserved = {0},
},
.FsptCoreUpd = {
- .MicrocodeRegionBase =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
- .MicrocodeRegionSize =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
- .CodeRegionBase =
- (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
+ .MicrocodeRegionBase = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
+ .MicrocodeRegionSize = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
},
};
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 67edeae..3a211ac 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -176,17 +176,14 @@
return routes;
}
-uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
- int dw_reg, uint32_t reg_val)
+uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val)
{
if (CONFIG(SKYLAKE_SOC_PCH_H))
return reg_val;
- /*
- * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4
- * ~ GPP_F11.
- */
+
+ /* For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 ~ GPP_F11. */
if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1)
reg_val = reg_val & ~(PAD_CFG1_TOL_1V8);
- return reg_val;
+ return reg_val;
}
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index c06893e..fae6469 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -63,11 +63,10 @@
write32(base + PCH_PP_DIVISOR, reg32);
/* So far all devices seem to use the PCH PWM function.
- The CPU PWM registers are all zero after reset. */
+ The CPU PWM registers are all zero after reset. */
if (conf->gpu_pch_backlight_pwm_hz) {
- /* Reference clock is 24MHz. We can choose either a 16
- or a 128 step increment. Use 16 if we would have less
- than 100 steps otherwise. */
+ /* Reference clock is 24MHz. We can choose either a 16 or a 128 step increment.
+ * Use 16 if we would have less than 100 steps otherwise. */
const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
unsigned int pwm_increment, pwm_period;
u32 south_chicken1;
@@ -82,15 +81,12 @@
}
write32(base + SOUTH_CHICKEN1, south_chicken1);
- pwm_period = 24 * 1000 * 1000 / pwm_increment
- / conf->gpu_pch_backlight_pwm_hz;
+ pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
/* Start with a 50% duty cycle. */
- write32(base + BLC_PWM_PCH_CTL2,
- pwm_period << 16 | pwm_period / 2);
+ write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
write32(base + BLC_PWM_PCH_CTL1,
- !!conf->gpu_pch_backlight_polarity << 29 |
- BLM_PCH_PWM_ENABLE);
+ !!conf->gpu_pch_backlight_polarity << 29 | BLM_PCH_PWM_ENABLE);
}
}
@@ -101,9 +97,8 @@
graphics_setup_panel(dev);
/*
- * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
- * This will allow the kernel to use 4-lane eDP links properly
- * if the VBIOS or GOP driver does not execute.
+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. This will allow the
+ * kernel to use 4-lane eDP links properly if the VBIOS or GOP driver does not execute.
*/
ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
@@ -117,12 +112,9 @@
pci_write_config32(dev, PCI_COMMAND, reg32);
/*
- * GFX PEIM module inside FSP binary is taking care of graphics
- * initialization based on RUN_FSP_GOP Kconfig option and input
- * VBT file.
- *
- * In case of non-FSP solution, SoC need to select another
- * Kconfig to perform GFX initialization.
+ * GFX PEIM module inside FSP binary is taking care of graphics initialization based on
+ * RUN_FSP_GOP Kconfig option and input VBT file. In case of non-FSP solution, SoC need
+ * to select another Kconfig to perform GFX initialization.
*/
if (CONFIG(RUN_FSP_GOP)) {
/* nothing to do */
@@ -159,8 +151,8 @@
/* FIXME: Add platform specific mailbox initialization */
}
-uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
- uintptr_t current, struct acpi_rsdp *rsdp)
+uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current,
+ struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
index c39c066..f883ee5 100644
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ b/src/soc/intel/skylake/include/soc/acpi.h
@@ -30,9 +30,9 @@
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_mainboard_gnvs(global_nvs_t *gnvs);
void southbridge_inject_dsdt(struct device *device);
-unsigned long southbridge_write_acpi_tables(struct device *device,
- unsigned long current, struct acpi_rsdp *rsdp);
-unsigned long northbridge_write_acpi_tables(struct device *,
- unsigned long current, struct acpi_rsdp *);
+unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current,
+ struct acpi_rsdp *rsdp);
+unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long current,
+ struct acpi_rsdp *rsdp);
#endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 0681f78..7455999 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -42,8 +42,7 @@
/* Common Timer Copy (CTC) frequency - 24MHz. */
#define CTC_FREQ 24000000
-#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
- (((1 << ((base)*5)) * (limit)) / 1000)
+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) (((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10))
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 13a0a7a..3bfaba5 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -18,8 +18,8 @@
#define _SOC_GPIO_H_
#include <soc/gpio_defs.h>
-#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in
- soc/gpio_defs.h */
+/* intelblocks/gpio.h depends on definitions in soc/gpio_defs.h */
+#include <intelblocks/gpio.h>
#define CROS_GPIO_DEVICE_NAME "INT344B:00"
#endif
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 321d3c2..e012e3a 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -35,10 +35,8 @@
#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
#define NUM_GPI_STATUS_REGS \
- ((NUM_GPIO_COM0_GPI_REGS) +\
- (NUM_GPIO_COM1_GPI_REGS) +\
- (NUM_GPIO_COM3_GPI_REGS) +\
- (NUM_GPIO_COM2_GPI_REGS))
+ ((NUM_GPIO_COM0_GPI_REGS) + (NUM_GPIO_COM1_GPI_REGS) +\
+ (NUM_GPIO_COM3_GPI_REGS) + (NUM_GPIO_COM2_GPI_REGS))
/*
* IOxAPIC IRQs for the GPIOs
@@ -220,9 +218,9 @@
/* Register defines. */
#define GPIO_MISCCFG 0x10
-#define GPIO_DRIVER_IRQ_ROUTE_MASK 8
-#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0
-#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
+#define GPIO_DRIVER_IRQ_ROUTE_MASK 8
+#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0
+#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
#define HOSTSW_OWN_REG_0 0xd0
#define PAD_CFG_BASE 0x400
#define GPI_INT_STS_0 0x100
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index c73d766..f1220de 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -22,8 +22,8 @@
/*
* Memory-mapped I/O registers.
*/
-#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
-#define PCH_PRESERVED_BASE_SIZE 0x02000000
+#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
+#define PCH_PRESERVED_BASE_SIZE 0x02000000
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h
index a25e5ac..82de495 100644
--- a/src/soc/intel/skylake/include/soc/nhlt.h
+++ b/src/soc/intel/skylake/include/soc/nhlt.h
@@ -43,8 +43,8 @@
int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels);
/*
- * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0
- * on error.
+ * Add nau88l25 headset codec on provided SSP link.
+ * Return 0 on succes, < 0 on error.
*/
int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink);
@@ -72,8 +72,8 @@
int nhlt_soc_add_rt5514(struct nhlt *nhlt, int hwlink, int num_channels);
/*
- * Add rt5663 headset codec on provided SSP link. Return 0 on success, < 0
- * on error.
+ * Add rt5663 headset codec on provided SSP link.
+ * Return 0 on success, < 0 on error.
*/
int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink);
@@ -84,8 +84,8 @@
int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink);
/*
- * Add da7219 headset codec on provided SSP link. Return 0 on success, < 0
- * on error.
+ * Add da7219 headset codec on provided SSP link.
+ * Return 0 on success, < 0 on error.
*/
int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink);
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 615edac..a220d8c 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -145,8 +145,7 @@
* - on microcontroller writes (io 0x62/0x66)
* - on TCO events
*/
-#define ENABLE_SMI_PARAMS \
- (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
#define ETR 0xac
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 88ce9e3..96faace 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -30,9 +30,8 @@
msr_t smrr_base;
msr_t smrr_mask;
/*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
+ * The smm_save_state_in_msrs field indicates if SMM save state locations live in MSRs.
+ * This indicates to the CPUs how to adjust the SMMBASE and IEDBASE
*/
int smm_save_state_in_msrs;
};
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index aebbbdf..2fa6f9f 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -27,15 +27,10 @@
struct vr_config {
- /*
- * The below settings will take effect when this is set to 1
- * for that domain.
- */
+ /* The below settings will take effect when this is set to 1 for that domain. */
int vr_config_enable;
- /* Power State X current cutoff in 1/4 Amp increments
- * Range is 0-128A
- */
+ /* Power State X current cutoff in 1/4 Amp increments Range is 0-128A */
int psi1threshold;
int psi2threshold;
int psi3threshold;
@@ -45,8 +40,8 @@
int psi4enable;
/*
- * Imon slope correction. Specified in 1/100 increment
- * values. Range is 0-200. 125 = 1.25
+ * Imon slope correction. Specified in 1/100 increment values.
+ * Range is 0-200. 125 = 1.25
*/
int imon_slope;
@@ -72,8 +67,7 @@
#if CONFIG(PLATFORM_USES_FSP1_1)
/* VrConfig Settings for 5 domains
- * 0 = System Agent, 1 = IA Core, 2 = Ring,
- * 3 = GT unsliced, 4 = GT sliced
+ * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
*/
enum vr_domain {
VR_SYSTEM_AGENT,
@@ -85,8 +79,7 @@
};
#else
/* VrConfig Settings for 4 domains
- * 0 = System Agent, 1 = IA Core,
- * 2 = GT unsliced, 3 = GT sliced
+ * 0 = System Agent, 1 = IA Core, 2 = GT unsliced, 3 = GT sliced
*/
enum vr_domain {
VR_SYSTEM_AGENT,
@@ -97,6 +90,5 @@
};
#endif
-void fill_vr_domain_config(void *params,
- int domain, const struct vr_config *cfg);
+void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg);
#endif
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index ddaffda..8ce0f78 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -24,198 +24,143 @@
#include <string.h>
static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
- /*
- * cAVS(Audio, Voice, Speech), INTA is default, programmed in
- * PciCfgSpace 3Dh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
- PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ),
- /*
- * SMBus Controller, no default value, programmed in
- * PciCfgSpace 3Dh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
- PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ),
+ /* cAVS(Audio, Voice, Speech), INTA is default, programmed in PciCfgSpace 3Dh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ),
+
+ /* SMBus Controller, no default value, programmed in PciCfgSpace 3Dh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ),
+
/* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
- PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ),
+
/* TraceHub, INTA is default, RO register */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
- PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A,
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A,
TRACE_HUB_INTA_IRQ),
- /*
- * SerialIo: UART #0, INTA is default,
- * programmed in PCR[SERIALIO] + PCICFGCTRL[7]
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ),
- /*
- * SerialIo: UART #1, INTA is default,
- * programmed in PCR[SERIALIO] + PCICFGCTRL[8]
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ),
- /*
- * SerialIo: SPI #0, INTA is default,
- * programmed in PCR[SERIALIO] + PCICFGCTRL[10]
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ),
- /*
- * SerialIo: SPI #1, INTA is default,
- * programmed in PCR[SERIALIO] + PCICFGCTRL[11]
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ),
+
+ /* SerialIo: UART #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[7] */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART0), int_A,
+ LPSS_UART0_IRQ),
+
+ /* SerialIo: UART #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[8] */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART1), int_B,
+ LPSS_UART1_IRQ),
+
+ /* SerialIo: SPI #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[10] */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI0), int_C,
+ LPSS_SPI0_IRQ),
+
+ /* SerialIo: SPI #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[11] */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI1), int_D,
+ LPSS_SPI1_IRQ),
+
/* SCS: eMMC (SKL PCH-LP Only) */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ),
+
/* SCS: SDIO (SKL PCH-LP Only) */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ),
+
/* SCS: SDCard (SKL PCH-LP Only) */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
- PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ),
- /* PCI Express Port, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
- PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ),
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
- PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ),
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
- PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ),
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
- PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ),
- /*
- * PCI Express Port 1, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ),
- /*
- * PCI Express Port 2, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ),
- /*
- * PCI Express Port 3, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ),
- /*
- * PCI Express Port 4, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ),
- /*
- * PCI Express Port 5, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ),
- /*
- * PCI Express Port 6, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ),
- /*
- * PCI Express Port 7, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ),
- /*
- * PCI Express Port 8, INT is default,
- * programmed in PciCfgSpace + FCh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
- PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ),
+
+ /* PCI Express Port, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ),
+
+ /* PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ),
+
+ /* PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ),
+
+ /* PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ),
+
+ /* PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ),
+
+ /* PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ),
+
+ /* PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ),
+
+ /* PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ),
+
+ /* PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ),
+
/*
* SerialIo UART Controller #2, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[9]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
- PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ),
/*
* SerialIo UART Controller #5, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[6]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
- PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ),
/*
* SerialIo UART Controller #4, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[5]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
- PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ),
- /*
- * SATA Controller, INTA is default,
- * programmed in PciCfgSpace + 3Dh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA,
- PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ),
+
+ /* SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ),
+
/* CSME: HECI #1 */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
- PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ),
+
/* CSME: HECI #2 */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
- PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ),
+
/* CSME: IDE-Redirection (IDE-R) */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
- PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ),
+
/* CSME: Keyboard and Text (KT) Redirection */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
- PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ),
+
/* CSME: HECI #3 */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE,
- PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ),
+
/*
* SerialIo I2C Controller #0, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[1]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
- PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ),
/*
* SerialIo I2C Controller #1, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[2]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
- PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ),
/*
* SerialIo I2C Controller #2, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[3]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
- PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ),
/*
* SerialIo I2C Controller #3, INTA is default,
* programmed in PCR[SERIALIO] + PCICFGCTRL[4]
*/
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
- PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ),
- /*
- * USB 3.0 xHCI Controller, no default value,
- * programmed in PciCfgSpace 3Dh
- */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
- PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ),
+
+ /* USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh */
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ),
+
/* USB Device Controller (OTG) */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
- PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ),
+
/* Thermal Subsystem */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
- PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ),
+
/* Camera IO Host Controller */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
- PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ),
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ),
+
/* Integrated Sensor Hub */
- DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH,
- PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
+ DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
};
void soc_irq_settings(FSP_SIL_UPD *params)
@@ -229,9 +174,8 @@
/* Get Device Int Count */
intdeventry = ARRAY_SIZE(devintconfig);
/* update irq table */
- memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)
- (params->DevIntConfigPtr), devintconfig, intdeventry *
- sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
+ memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr),
+ devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
params->NumOfDevIntConfig = intdeventry;
/* PxRC to IRQ programming */
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index f7aa584..b838c5c 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -93,38 +93,22 @@
/* HFSTS2[27:24] Power Management Event */
static const char *const me_pmevent_values[] = {
- [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =
- "Clean Moff->Mx wake",
- [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =
- "Moff->Mx wake after an error",
- [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] =
- "Clean global reset",
- [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] =
- "Global reset after an error",
- [ME_HFS2_PMEVENT_CLEAN_ME_RESET] =
- "Clean Intel ME reset",
- [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] =
- "Intel ME reset due to exception",
- [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] =
- "Pseudo-global reset",
- [ME_HFS2_PMEVENT_CM0_CM3] =
- "CM0->CM3",
- [ME_HFS2_PMEVENT_CM3_CM0] =
- "CM3->CM0",
- [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] =
- "Non-power cycle reset",
- [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] =
- "Power cycle reset through M3",
- [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] =
- "Power cycle reset through Moff",
- [ME_HFS2_PMEVENT_CMX_CMOFF] =
- "Cx/Mx->Cx/Moff",
- [ME_HFS2_PMEVENT_CM0_CM0PG] =
- "CM0->CM0PG",
- [ME_HFS2_PMEVENT_CM3_CM3PG] =
- "CM3->CM3PG",
- [ME_HFS2_PMEVENT_CM0PG_CM0] =
- "CM0PG->CM0"
+ [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake",
+ [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error",
+ [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset",
+ [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error",
+ [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset",
+ [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception",
+ [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset",
+ [ME_HFS2_PMEVENT_CM0_CM3] = "CM0->CM3",
+ [ME_HFS2_PMEVENT_CM3_CM0] = "CM3->CM0",
+ [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset",
+ [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3",
+ [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff",
+ [ME_HFS2_PMEVENT_CMX_CMOFF] = "Cx/Mx->Cx/Moff",
+ [ME_HFS2_PMEVENT_CM0_CM0PG] = "CM0->CM0PG",
+ [ME_HFS2_PMEVENT_CM3_CM3PG] = "CM3->CM3PG",
+ [ME_HFS2_PMEVENT_CM0PG_CM0] = "CM0PG->CM0"
};
@@ -136,70 +120,41 @@
/* Progress Code 1 states */
static const char *const me_progress_bup_values[] = {
- [ME_HFS2_STATE_BUP_INIT] =
- "Initialization starts",
- [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =
- "Disable the host wake event",
- [ME_HFS2_STATE_BUP_CG_ENABLE] =
- "Enabling CG for cset",
- [ME_HFS2_STATE_BUP_PM_HND_EN] =
- "Enabling PM handshaking",
- [ME_HFS2_STATE_BUP_FLOW_DET] =
- "Flow determination start process",
- [ME_HFS2_STATE_BUP_PMC_PATCHING] =
- "PMC Patching process",
- [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] =
- "Get VSCC params",
- [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] =
- "Set VSCC params",
+ [ME_HFS2_STATE_BUP_INIT] = "Initialization starts",
+ [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event",
+ [ME_HFS2_STATE_BUP_CG_ENABLE] = "Enabling CG for cset",
+ [ME_HFS2_STATE_BUP_PM_HND_EN] = "Enabling PM handshaking",
+ [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process",
+ [ME_HFS2_STATE_BUP_PMC_PATCHING] = "PMC Patching process",
+ [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = "Get VSCC params",
+ [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = "Set VSCC params",
[ME_HFS2_STATE_BUP_VSCC_ERR] =
- "Error reading/matching the VSCC table in the descriptor",
- [ME_HFS2_STATE_BUP_EFSS_INIT] =
- "Initialize EFFS",
- [ME_HFS2_STATE_BUP_CHECK_STRAP] =
- "Check to see if straps say ME DISABLED",
- [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] =
- "Timeout waiting for PWROK",
- [ME_HFS2_STATE_BUP_STRAP_DIS] =
- "EFFS says ME disabled",
+ "Error reading/matching the VSCC table in the descriptor",
+ [ME_HFS2_STATE_BUP_EFSS_INIT] = "Initialize EFFS",
+ [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED",
+ [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK",
+ [ME_HFS2_STATE_BUP_STRAP_DIS] = "EFFS says ME disabled",
[ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] =
- "Possibly handle BUP manufacturing override strap",
- [ME_HFS2_STATE_BUP_M3] =
- "Bringup in M3",
- [ME_HFS2_STATE_BUP_M0] =
- "Bringup in M0",
- [ME_HFS2_STATE_BUP_FLOW_DET_ERR] =
- "Flow detection error",
- [ME_HFS2_STATE_BUP_M3_CLK_ERR] =
- "M3 clock switching error",
+ "Possibly handle BUP manufacturing override strap",
+ [ME_HFS2_STATE_BUP_M3] = "Bringup in M3",
+ [ME_HFS2_STATE_BUP_M0] = "Bringup in M0",
+ [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error",
+ [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error",
[ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] =
- "Host error - CPU reset timeout, DID timeout, memory missing",
- [ME_HFS2_STATE_BUP_M3_KERN_LOAD] =
- "M3 kernel load",
- [ME_HFS2_STATE_BUP_T32_MISSING] =
- "T34 missing - cannot program ICC",
- [ME_HFS2_STATE_BUP_WAIT_DID] =
- "Waiting for DID BIOS message",
- [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] =
- "Waiting for DID BIOS message failure",
- [ME_HFS2_STATE_BUP_DID_NO_FAIL] =
- "DID reported no error",
- [ME_HFS2_STATE_BUP_ENABLE_UMA] =
- "Enabling UMA",
- [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] =
- "Enabling UMA error",
- [ME_HFS2_STATE_BUP_SEND_DID_ACK] =
- "Sending DID Ack to BIOS",
- [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] =
- "Sending DID Ack to BIOS error",
- [ME_HFS2_STATE_BUP_M0_CLK] =
- "Switching clocks in M0",
- [ME_HFS2_STATE_BUP_M0_CLK_ERR] =
- "Switching clocks in M0 error",
- [ME_HFS2_STATE_BUP_TEMP_DIS] =
- "ME in temp disable",
- [ME_HFS2_STATE_BUP_M0_KERN_LOAD] =
- "M0 kernel load",
+ "Host error - CPU reset timeout, DID timeout, memory missing",
+ [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load",
+ [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC",
+ [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message",
+ [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure",
+ [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error",
+ [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA",
+ [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error",
+ [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS",
+ [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error",
+ [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0",
+ [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error",
+ [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable",
+ [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load",
};
static void print_me_version(void *unused)
@@ -258,8 +213,7 @@
*/
heci_reset();
- if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD,
- HECI_MKHI_ADD))
+ if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, HECI_MKHI_ADD))
goto failed;
if (!heci_receive(&resp, &resp_size))
@@ -293,18 +247,14 @@
hfs3.data = me_read_config32(PCI_ME_HFSTS3);
hfs6.data = me_read_config32(PCI_ME_HFSTS6);
- printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n",
- hfs.data);
- printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n",
- hfs2.data);
- printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n",
- hfs3.data);
+ printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", hfs.data);
+ printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", hfs2.data);
+ printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", hfs3.data);
printk(BIOS_DEBUG, "ME: Host Firmware Status Register 4 : 0x%08X\n",
me_read_config32(PCI_ME_HFSTS4));
printk(BIOS_DEBUG, "ME: Host Firmware Status Register 5 : 0x%08X\n",
me_read_config32(PCI_ME_HFSTS5));
- printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n",
- hfs6.data);
+ printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", hfs6.data);
/* Check Current States */
printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n",
hfs.fields.fpt_bad ? "BAD" : "OK");
@@ -344,12 +294,10 @@
printk(BIOS_DEBUG, "ME: Progress Phase State : ");
switch (hfs2.fields.progress_code) {
case ME_HFS2_PHASE_ROM: /* ROM Phase */
- if (hfs2.fields.current_state
- < ARRAY_SIZE(me_progress_rom_values)
+ if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_rom_values)
&& me_progress_rom_values[hfs2.fields.current_state])
printk(BIOS_DEBUG, "%s",
- me_progress_rom_values[
- hfs2.fields.current_state]);
+ me_progress_rom_values[hfs2.fields.current_state]);
else
printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
break;
@@ -359,12 +307,10 @@
break;
case ME_HFS2_PHASE_BUP: /* Bringup Phase */
- if (hfs2.fields.current_state
- < ARRAY_SIZE(me_progress_bup_values)
+ if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_bup_values)
&& me_progress_bup_values[hfs2.fields.current_state])
printk(BIOS_DEBUG, "%s",
- me_progress_bup_values[
- hfs2.fields.current_state]);
+ me_progress_bup_values[hfs2.fields.current_state]);
else
printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
break;
@@ -417,8 +363,7 @@
printk(BIOS_DEBUG, "Corporate\n");
break;
default:
- printk(BIOS_DEBUG, "Unknown (0x%x)\n",
- hfs3.fields.fw_sku);
+ printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3.fields.fw_sku);
}
}
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 4c3c58a..acd5e92 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -40,8 +40,7 @@
static bool is_ptt_enable(void)
{
- if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==
- PTT_PRESENT)
+ if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == PTT_PRESENT)
return true;
return false;
@@ -80,8 +79,7 @@
}
/* Calculate PRMRR size based on user input PRMRR size and alignment */
-static size_t get_prmrr_size(uintptr_t dram_base,
- const struct soc_intel_skylake_config *config)
+static size_t get_prmrr_size(uintptr_t dram_base, const struct soc_intel_skylake_config *config)
{
uintptr_t prmrr_base = dram_base;
size_t prmrr_size;
@@ -95,12 +93,10 @@
return 0;
/*
- * PRMRR Sizes that are > 1MB and < 32MB are
- * not supported and will fail out.
+ * PRMRR Sizes that are > 1MB and < 32MB are not supported and will fail out.
*/
if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))
- die("PRMRR Sizes that are > 1MB and < 32MB are not"
- "supported!\n");
+ die("PRMRR Sizes that are > 1MB and < 32MB are not supported!\n");
prmrr_base -= prmrr_size;
if (prmrr_size >= 32*MiB)
diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c
index dd91435..7dd82fa 100644
--- a/src/soc/intel/skylake/nhlt/nau88l25.c
+++ b/src/soc/intel/skylake/nhlt/nau88l25.c
@@ -15,8 +15,7 @@
#include <soc/nhlt.h>
-/* The same DSP firmware settings are used for both the capture and
- * render endpoints. */
+/* The same DSP firmware settings are used for both the capture and render endpoints. */
static const struct nhlt_format_config nau88l25_formats[] = {
/* 48 KHz 24-bits per sample. */
{
diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c
index 9c48c7b..5be881c 100644
--- a/src/soc/intel/skylake/nhlt/rt5514.c
+++ b/src/soc/intel/skylake/nhlt/rt5514.c
@@ -53,8 +53,7 @@
{
switch (num_channels) {
case 4:
- return nhlt_add_ssp_endpoints(nhlt, hwlink,
- rt5514_4ch_descriptors,
+ return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5514_4ch_descriptors,
ARRAY_SIZE(rt5514_4ch_descriptors));
default:
return -1;
diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c
index c5a3f53..a308265 100644
--- a/src/soc/intel/skylake/nhlt/rt5663.c
+++ b/src/soc/intel/skylake/nhlt/rt5663.c
@@ -16,8 +16,7 @@
#include <soc/nhlt.h>
/*
- * The same DSP firmware settings are used for both the capture and
- * render endpoints.
+ * The same DSP firmware settings are used for both the capture and render endpoints.
*/
static const struct nhlt_format_config rt5663_formats[] = {
/* 48 KHz 24-bits per sample. */
diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c
index c1e9118..f118b38 100644
--- a/src/soc/intel/skylake/p2sb.c
+++ b/src/soc/intel/skylake/p2sb.c
@@ -31,14 +31,13 @@
* Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband
* access for MIPI controller.
*/
- mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) |
- (1 << 16) | (1 << 10) | (1 << 1);
+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | (1 << 16) |
+ (1 << 10) | (1 << 1);
ep_mask[P2SB_EP_MASK_5_REG] = mask;
/*
- * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband
- * access for XHCI controller.
+ * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband access for XHCI controller.
*/
mask = (1 << 6) | (1 << 5);
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index ffe0605..65075ea 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -48,8 +48,7 @@
}
/*
- * Set which power state system will be after reapplying
- * the power (from G3 State)
+ * Set which power state system will be after reapplying the power (from G3 State)
*/
void pmc_soc_set_afterg3_en(const bool on)
{
@@ -84,10 +83,8 @@
static const struct reg_script pch_pmc_misc_init_script[] = {
/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
- REG_PCI_RMW16(GEN_PMCON_B,
- ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK),
- S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS |
- DIS_SLP_X_STRCH_SUS_UP),
+ REG_PCI_RMW16(GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK),
+ S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP),
/* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
REG_SCRIPT_END
@@ -107,8 +104,7 @@
uint32_t reg;
uint8_t *pmcbase = pmc_mmio_regs();
- printk(BIOS_DEBUG, "%sabling Deep S%c\n",
- enable ? "En" : "Dis", sx + '0');
+ printk(BIOS_DEBUG, "%sabling Deep S%c\n", enable ? "En" : "Dis", sx + '0');
reg = read32(pmcbase + offset);
if (enable)
reg |= mask;
@@ -168,12 +164,10 @@
static void pm1_enable_pwrbtn_smi(void *unused)
{
/*
- * Enable power button SMI only before jumping to payload. This ensures
- * that:
+ * Enable power button SMI only before jumping to payload. This ensures that:
* 1. Power button SMI is enabled only after coreboot is done.
- * 2. On resume path, power button SMI is not enabled and thus avoids
- * any shutdowns because of power button presses due to power button
- * press in resume path.
+ * 2. On resume path, power button SMI is not enabled and thus avoids any shutdowns
+ * because of power button presses due to power button press in resume path.
*/
pmc_update_pm1_enable(PWRBTN_EN);
}
@@ -181,10 +175,9 @@
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
/*
- * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in
- * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable
- * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE#
- * pin.
+ * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in deep_sx_config.
+ * If WAKE# pin is not enabled, then PCI Express Wake Disable bit needs to be set
+ * in PM1_EN to avoid unnecessary wakes caused by WAKE# pin.
*/
static void pm1_handle_wake_pin(void *unused)
{
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 90f1b03..ee3c74d 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -212,22 +212,18 @@
}
/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
- int prev_sleep_state)
+int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
{
/*
- * Check for any power failure to determine if this a wake from
- * S5 because the PCH does not set the WAK_STS bit when waking
- * from a true G3 state.
+ * Check for any power failure to determine if this a wake from S5 because
+ * the PCH does not set the WAK_STS bit when waking from a true G3 state.
*/
- if (!(ps->pm1_sts & WAK_STS) &&
- (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
+ if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
prev_sleep_state = ACPI_S5;
/*
- * If waking from S3 determine if deep S3 is enabled. If not,
- * need to check both deep sleep well and normal suspend well.
- * Otherwise just check deep sleep well.
+ * If waking from S3 determine if deep S3 is enabled. If not, need to check both
+ * deep sleep well and normal suspend well. Otherwise just check deep sleep well.
*/
if (prev_sleep_state == ACPI_S3) {
/* PWR_FLR represents deep sleep power well loss. */
@@ -250,8 +246,7 @@
ps->tco1_sts = tco_read_reg(TCO1_STS);
ps->tco2_sts = tco_read_reg(TCO2_STS);
- printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
- ps->tco1_sts, ps->tco2_sts);
+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
@@ -260,8 +255,7 @@
ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
- ps->gen_pmcon_a, ps->gen_pmcon_b);
+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
ps->gblrst_cause[0], ps->gblrst_cause[1]);
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index ff1a959..a87ce47 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -24,14 +24,12 @@
static void do_force_global_reset(void)
{
/*
- * BIOS should ensure it does a global reset
- * to reset both host and Intel ME by setting
- * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
+ * BIOS should ensure it does a global reset to reset both host and
+ * Intel ME by setting PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
*/
pmc_global_reset_enable(true);
- /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
- * to global reset platform */
+ /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port to global reset platform */
do_full_reset();
}
@@ -39,7 +37,7 @@
{
if (send_global_reset() != 0) {
/* If ME unable to reset platform then
- * force global reset using PMC CF9GR register*/
+ * force global reset using PMC CF9GR register */
do_force_global_reset();
}
}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 2d0de2f..e1e3ad0 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -51,8 +51,7 @@
}
/* UPD parameters to be initialized before MemoryInit */
-void soc_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *upd)
+void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd)
{
const struct soc_intel_skylake_config *config;
@@ -61,11 +60,10 @@
config = config_of_path(PCH_DEVFN_LPC);
/*
- * Set IGD stolen size to 64MB. The FBC hardware for skylake does not
- * have access to the bios_reserved range so it always assumes 8MB is
- * used and so the kernel will avoid the last 8MB of the stolen window.
- * With the default stolen size of 32MB(-8MB) there is not enough space
- * for FBC to work with a high resolution panel.
+ * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have access to
+ * the bios_reserved range so it always assumes 8MB is used and so the kernel will
+ * avoid the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB),
+ * there is not enough space for FBC to work with a high resolution panel.
*/
upd->IgdDvmt50PreAlloc = 2;
@@ -90,34 +88,25 @@
/* Boot media is memory mapped for Skylake and Kabylake (SPI). */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
- memory_cfg->MmaTestContentPtr =
- (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
- memory_cfg->MmaTestContentSize =
- region_device_sz(&mma_cfg->test_content);
- memory_cfg->MmaTestConfigPtr =
- (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
- memory_cfg->MmaTestConfigSize =
- region_device_sz(&mma_cfg->test_param);
+ memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+ memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content);
+ memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+ memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param);
memory_cfg->MrcFastBoot = 0x00;
memory_cfg->SaGv = 0x02;
}
-void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
- MEMORY_INIT_UPD *new)
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
{
/* Display the parameters for MemoryInit */
printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
- fsp_display_upd_value("PlatformMemorySize", 8,
- old->PlatformMemorySize, new->PlatformMemorySize);
- fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00,
- new->MemorySpdPtr00);
- fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01,
- new->MemorySpdPtr01);
- fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10,
- new->MemorySpdPtr10);
- fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11,
- new->MemorySpdPtr11);
+ fsp_display_upd_value("PlatformMemorySize", 8, old->PlatformMemorySize,
+ new->PlatformMemorySize);
+ fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, new->MemorySpdPtr00);
+ fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, new->MemorySpdPtr01);
+ fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, new->MemorySpdPtr10);
+ fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, new->MemorySpdPtr11);
fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen,
new->MemorySpdDataLen);
fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0],
@@ -208,46 +197,32 @@
new->RcompResistor[1]);
fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2],
new->RcompResistor[2]);
- fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0],
- new->RcompTarget[0]);
- fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1],
- new->RcompTarget[1]);
- fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2],
- new->RcompTarget[2]);
- fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3],
- new->RcompTarget[3]);
- fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4],
- new->RcompTarget[4]);
- fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig,
- new->CaVrefConfig);
+ fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], new->RcompTarget[0]);
+ fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], new->RcompTarget[1]);
+ fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], new->RcompTarget[2]);
+ fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], new->RcompTarget[3]);
+ fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], new->RcompTarget[4]);
+ fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, new->CaVrefConfig);
fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask);
- fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot,
- new->MrcFastBoot);
+ fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, new->MrcFastBoot);
fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize);
fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize);
fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize);
- fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub,
- new->EnableTraceHub);
+ fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub);
fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc,
new->IgdDvmt50PreAlloc);
- fsp_display_upd_value("InternalGfx", 1, old->InternalGfx,
- new->InternalGfx);
- fsp_display_upd_value("ApertureSize", 1, old->ApertureSize,
- new->ApertureSize);
+ fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, new->InternalGfx);
+ fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, new->ApertureSize);
fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
fsp_display_upd_value("RMT", 1, old->RMT, new->RMT);
- fsp_display_upd_value("FspCarBase", 1, old->FspCarBase,
- new->FspCarBase);
- fsp_display_upd_value("FspCarSize", 1, old->FspCarSize,
- new->FspCarSize);
+ fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, new->FspCarBase);
+ fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, new->FspCarSize);
}
/* SOC initialization after RAM is enabled. */
void soc_after_ram_init(struct romstage_params *params)
{
- /* Set the DISB as soon as possible after DRAM
- * init and MRC cache is saved.
- */
+ /* Set the DISB as soon as possible after DRAM init and MRC cache is saved. */
pmc_set_disb();
}
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index ecd1428..c517d1f 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -60,22 +60,16 @@
struct dimm_info *dest_dimm;
struct memory_info *mem_info;
const MEMORY_INFO_DATA_HOB *memory_info_hob;
- const uint8_t smbios_memory_info_guid[16] =
- FSP_SMBIOS_MEMORY_INFO_GUID;
+ const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID;
/* Locate the memory info HOB, presence validated by raminit */
- memory_info_hob =
- fsp_find_extension_hob_by_guid(smbios_memory_info_guid,
- &hob_size);
+ memory_info_hob = fsp_find_extension_hob_by_guid(smbios_memory_info_guid, &hob_size);
if (memory_info_hob == NULL || hob_size == 0) {
printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
return;
}
- /*
- * Allocate CBMEM area for DIMM information used to populate SMBIOS
- * table 17
- */
+ /* Allocate CBMEM area for DIMM information used to populate SMBIOS table 17 */
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
if (mem_info == NULL) {
printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
@@ -165,8 +159,7 @@
m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
-static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
- FSP_M_TEST_CONFIG *m_t_cfg,
+static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, FSP_M_TEST_CONFIG *m_t_cfg,
const struct soc_intel_skylake_config *config)
{
const struct device *dev;
@@ -177,8 +170,7 @@
* device pci 01.0 on end # enable PEG0 root port
* device pci 01.1 off end # do not configure PEG1
*
- * If PEG port is not defined in the device tree, it will be disabled
- * in FSP
+ * If PEG port is not defined in the device tree, it will be disabled in FSP
*/
dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */
if (!dev || !dev->enabled)
@@ -239,7 +231,7 @@
m_cfg->PrmrrSize = config->PrmrrSize;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
- mask |= (1<<i);
+ mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
@@ -269,12 +261,11 @@
} else {
m_cfg->InternalGfx = 1;
/*
- * Set IGD stolen size to 64MB. The FBC hardware for skylake
- * does not have access to the bios_reserved range so it always
- * assumes 8MB is used and so the kernel will avoid the last
- * 8MB of the stolen window. With the default stolen size of
- * 32MB(-8MB) there is not enough space for FBC to work with
- * a high resolution panel
+ * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have
+ * access to the bios_reserved range so it always assumes 8MB is used and so
+ * the kernel will avoid the last 8MB of the stolen window. With the default
+ * stolen size of 32MB(-8MB) there is not enough space for FBC to work with
+ * a high resolution panel.
*/
m_cfg->IgdDvmt50PreAlloc = 2;
}
@@ -324,14 +315,10 @@
/* Boot media is memory mapped for Skylake and Kabylake (SPI). */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
- memory_cfg->MmaTestContentPtr =
- (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
- memory_cfg->MmaTestContentSize =
- region_device_sz(&mma_cfg->test_content);
- memory_cfg->MmaTestConfigPtr =
- (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
- memory_cfg->MmaTestConfigSize =
- region_device_sz(&mma_cfg->test_param);
+ memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+ memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content);
+ memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+ memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param);
memory_cfg->MrcFastBoot = 0x00;
memory_cfg->SaGv = 0x02;
}
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 9b7ea24..48884ec 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -33,8 +33,7 @@
if (config->ignore_vtd)
return;
- const bool vtd_capable =
- !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE);
+ const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE);
if (!vtd_capable)
return;
@@ -58,11 +57,9 @@
};
/* Set Fixed MMIO address into PCI configuration space */
- sa_set_pci_bar(soc_fixed_pci_resources,
- ARRAY_SIZE(soc_fixed_pci_resources));
+ sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources));
/* Set Fixed MMIO address into MCH base address */
- sa_set_mch_bar(soc_fixed_mch_resources,
- ARRAY_SIZE(soc_fixed_mch_resources));
+ sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources));
systemagent_vtd_init();
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 2e93075..b4f16e9 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -27,19 +27,15 @@
void smihandler_soc_check_illegal_access(uint32_t tco_sts)
{
- if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
+ if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status()))
return;
/*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
+ * BWE is RW, so the SMI was caused by a write to BWE, not by a write to the BIOS
*
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
+ * This is the place where we notice someone is trying to tinker with the BIOS.
+ * We are trying to be nice and just ignore it. A more resolute answer would be
+ * to power down the box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
fast_spi_enable_wp();
@@ -48,8 +44,7 @@
/* SMI handlers that should be serviced in SCI mode too. */
uint32_t smihandler_soc_get_sci_mask(void)
{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
+ uint32_t sci_mask = SMI_HANDLER_SCI_EN(APM_STS_BIT) |
SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
return sci_mask;
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index e1779d1..f92d3f4 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -46,23 +46,20 @@
wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
-static void update_save_state(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase,
+static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase,
struct smm_relocation_params *relo_params)
{
u32 smbase;
u32 iedbase;
/*
- * The relocated handler runs with all CPUs concurrently. Therefore
- * stagger the entry points adjusting SMBASE downwards by save state
- * size * CPU num.
+ * The relocated handler runs with all CPUs concurrently. Therefore stagger
+ * the entry points adjusting SMBASE downwards by save state size * CPU num.
*/
smbase = staggered_smbase;
iedbase = relo_params->ied_base;
- printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
- smbase, iedbase);
+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", smbase, iedbase);
/*
* All threads need to set IEDBASE and SMBASE to the relocated
@@ -93,8 +90,7 @@
} else {
em64t101_smm_state_save_area_t *save_state;
- save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
- sizeof(*save_state));
+ save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
save_state->smbase = smbase;
save_state->iedbase = iedbase;
@@ -120,12 +116,10 @@
}
/*
- * The relocation work is actually performed in SMM context, but the code
- * resides in the ramstage module. This occurs by trampolining from the default
- * SMRAM entry point to here.
+ * The relocation work is actually performed in SMM context, but the code resides in the
+ * ramstage module. This occurs by trampolining from the default SMRAM entry point to here.
*/
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase)
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
{
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
@@ -133,18 +127,15 @@
printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
/*
- * Determine if the processor supports saving state in MSRs. If so,
- * enable it before the non-BSPs run so that SMM relocation can occur
- * in parallel in the non-BSP CPUs.
+ * Determine if the processor supports saving state in MSRs. If so, enable it before
+ * the non-BSPs run so that SMM relocation can occur in parallel in the non-BSP CPUs.
*/
if (cpu == 0) {
/*
- * If smm_save_state_in_msrs is 1 then that means this is the
- * 2nd time through the relocation handler for the BSP.
- * Parallel SMM handler relocation is taking place. However,
- * it is desired to access other CPUs save state in the real
- * SMM handler. Therefore, disable the SMM save state in MSRs
- * feature.
+ * If smm_save_state_in_msrs is 1 then that means this is the 2nd time through
+ * the relocation handler for the BSP. Parallel SMM handler relocation is
+ * taking place. However, it is desired to access other CPUs save state in the
+ * real SMM handler. Therefore, disable the SMM save state in MSRs feature.
*/
if (relo_params->smm_save_state_in_msrs) {
msr_t smm_feature_control;
@@ -154,10 +145,9 @@
wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
} else if (bsp_setup_msr_save_state(relo_params))
/*
- * Just return from relocation handler if MSR save
- * state is enabled. In that case the BSP will come
- * back into the relocation handler to setup the new
- * SMBASE as well disabling SMM save state in MSRs.
+ * Just return from relocation handler if MSR save state is enabled.
+ * In that case the BSP will come back into the relocation handler
+ * to setup the new SMBASE as well disabling SMM save state in MSRs.
*/
return;
}
@@ -210,8 +200,7 @@
memset(ied_base + (1 << 20), 0, (32 << 10));
}
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size)
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size)
{
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
@@ -243,10 +232,9 @@
void smm_relocate(void)
{
/*
- * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
- * shall take place. Run the relocation handler a second time on the
- * BSP to do * the final move. For APs, a relocation handler always
- * needs to be run.
+ * If smm_save_state_in_msrs is non-zero then parallel SMM relocation shall take place.
+ * Run the relocation handler a second time on the BSP to do * the final move.
+ * For APs, a relocation handler always needs to be run.
*/
if (smm_reloc_params.smm_save_state_in_msrs)
smm_initiate_relocation_parallel();
@@ -258,9 +246,8 @@
{
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/*
- * LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
+ * LOCK the SMM memory window and enable normal SMM. After running this
+ * function, only a full reset can make the SMM registers writable again.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index 410265f..825078b 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -30,23 +30,21 @@
bool soc_is_vtd_capable(void)
{
struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
- return root_dev &&
- !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
+
+ return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
}
/*
* SoC implementation
*
- * Add all known fixed memory ranges for Host Controller/Memory
- * controller.
+ * Add all known fixed memory ranges for Host Controller/Memory controller.
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
- { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
- "PCIEXBAR" },
+ { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
@@ -60,11 +58,9 @@
if (!config->ignore_vtd && soc_is_vtd_capable()) {
if (igd_dev && igd_dev->enabled)
- sa_add_fixed_mmio_resources(dev, index,
- &soc_gfxvt_mmio_descriptor, 1);
+ sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1);
- sa_add_fixed_mmio_resources(dev, index,
- &soc_vtvc0_mmio_descriptor, 1);
+ sa_add_fixed_mmio_resources(dev, index, &soc_vtvc0_mmio_descriptor, 1);
}
}
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 089dd5d..7febe24 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -295,8 +295,7 @@
}
#endif
-void fill_vr_domain_config(void *params,
- int domain, const struct vr_config *chip_cfg)
+void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg)
{
FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
const struct vr_config *cfg;
--
To view, visit https://review.coreboot.org/c/coreboot/+/35172
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22
Gerrit-Change-Number: 35172
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange
3
12