coreboot-gerrit August 2019

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Change in ...coreboot[master]: HACK sdm845: Drag in all of the binary blobs
by T.Michael Turney (Code Review) 11 Nov '20

11 Nov '20

Hello T Michael Turney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32450 to review the following change. Change subject: HACK sdm845: Drag in all of the binary blobs ...................................................................... HACK sdm845: Drag in all of the binary blobs This patch is a hack until licensing issues are resolved. There is a lot of ugliness in the Makefile.inc to allow build-bot to accept this patch without having access to the binary blobs required to run on Napali hardware. Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/sdm845/Makefile.inc 1 file changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32450/1 diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 34064a1..8c64a2f 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -73,13 +73,117 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include +SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845 + BL31_MAKEARGS += PLAT=sdm845 ifeq ($(CONFIG_QC_SDI_ENABLE),y) BL31_MAKEARGS += DEBUG=1 endif +################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(SDM845_BLOB)/QcSdi.elf +qcsdi_file := $(shell ls $(QCSDI_FILE)) +ifneq (,$(findstring $(QCSDI_FILE),$(qcsdi_file))) + QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi + $(QCSDI_CBFS)-file := $(QCSDI_FILE) + $(QCSDI_CBFS)-type := stage + $(QCSDI_CBFS)-compression := none + cbfs-files-y += $(QCSDI_CBFS) +endif +endif + +################################################################################ +QCLIB_FILE := $(SDM845_BLOB)/QcLib.elf +qclib_file := $(shell ls $(QCLIB_FILE)) +ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file))) + QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib + $(QCLIB_CBFS)-file := $(QCLIB_FILE) + $(QCLIB_CBFS)-type := stage + $(QCLIB_CBFS)-compression := none + cbfs-files-y += $(QCLIB_CBFS) +endif + +################################################################################ +PMIC_FILE := $(SDM845_BLOB)/Pmic.bin +pmic_file := $(shell ls $(PMIC_FILE)) +ifneq (,$(findstring $(PMIC_FILE),$(pmic_file))) + PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg + $(PMIC_CBFS)-file := $(PMIC_FILE) + $(PMIC_CBFS)-type := raw + $(PMIC_CBFS)-compression := none + cbfs-files-y += $(PMIC_CBFS) +endif + +################################################################################ +DCB_FILE := $(SDM845_BLOB)/6000_0200_1_dcb.bin +dcb_file := $(shell ls $(DCB_FILE)) +ifneq (,$(findstring $(DCB_FILE),$(dcb_file))) + DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb + $(DCB_CBFS)-file := $(DCB_FILE) + $(DCB_CBFS)-type := raw + $(DCB_CBFS)-compression := none + cbfs-files-y += $(DCB_CBFS) +endif + +################################################################################ +AOP_FILE := $(SDM845_BLOB)/aop.mbn +aop_file := $(shell ls $(AOP_FILE)) +ifneq (,$(findstring $(AOP_FILE),$(aop_file))) + AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop + $(AOP_CBFS)-file := $(AOP_FILE) + $(AOP_CBFS)-type := payload + $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += $(AOP_CBFS) +endif + +################################################################################ +UART_FW_FILE := $(SDM845_BLOB)/uart_fw.bin +uart_fw_file := $(shell ls $(UART_FW_FILE)) +ifneq (,$(findstring $(UART_FW_FILE),$(uart_fw_file))) + UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw + $(UART_FW_CBFS)-file := $(UART_FW_FILE) + $(UART_FW_CBFS)-type := raw + $(UART_FW_CBFS)-compression := none + cbfs-files-y += $(UART_FW_CBFS) +endif + +################################################################################ +SPI_FW_FILE := $(SDM845_BLOB)/spi_fw.bin +spi_fw_file := $(shell ls $(SPI_FW_FILE)) +ifneq (,$(findstring $(SPI_FW_FILE),$(spi_fw_file))) + SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw + $(SPI_FW_CBFS)-file := $(SPI_FW_FILE) + $(SPI_FW_CBFS)-type := raw + $(SPI_FW_CBFS)-compression := none + cbfs-files-y += $(SPI_FW_CBFS) +endif + +################################################################################ +I2C_FW_FILE := $(SDM845_BLOB)/i2c_fw.bin +i2c_fw_file := $(shell ls $(I2C_FW_FILE)) +ifneq (,$(findstring $(I2C_FW_FILE),$(i2c_fw_file))) + I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw + $(I2C_FW_CBFS)-file := $(I2C_FW_FILE) + $(I2C_FW_CBFS)-type := raw + $(I2C_FW_CBFS)-compression := none + cbfs-files-y += $(I2C_FW_CBFS) +endif + +################################################################################ +QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn +qc_sec_file := $(shell ls $(QC_SEC_FILE)) +ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf + @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +else $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a Gerrit-Change-Number: 32450 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34517 ) Change subject: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides ...................................................................... soc/intel/{cnl,icl}: Enable support to configure interrupt overrides This implementation selects SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE config. It would enable support from SOC to dynamically populate the PCI IRQ routing table based on the devices enabled from the mainboard. And pass the same to FSP to configure the IRQ entries in ITSS PIRx register. The same table can be used to generate the ACPI PIRQ mapping table. Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34517/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..0283f2c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 5dca44b..79a19ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Gerrit-Change-Number: 34517 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34349 ) Change subject: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides ...................................................................... src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/fsp_params.c 4 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34349/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4235b7a..c8dfc13 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fe5b3dd..4eef58e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -408,6 +409,11 @@ configure_gspi_cs(i, config, &params->SerialIoSpiCsPolarity[0], NULL, NULL); #endif + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2261a0..d31c8eb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ed86c27..ee45024 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -241,6 +242,12 @@ params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Gerrit-Change-Number: 34349 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/*/include: Get list of devices that needs IRQ programming
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 ) Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming ...................................................................... src/soc/intel/*/include: Get list of devices that needs IRQ programming This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices. Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..ed0d09c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/cannonlake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd02934..2973e15 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/icelake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Gerrit-Change-Number: 34348 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Fix spelling of *assumptions*
by Paul Menzel (Code Review) 19 Oct '20

19 Oct '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33742 Change subject: Documentation: Fix spelling of *assumptions* ...................................................................... Documentation: Fix spelling of *assumptions* Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/arch/x86/index.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/33742/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 0d8acf1..b4ad5c8 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -17,7 +17,7 @@ The following features enhance x86_64 support: * The CPU supports 1GiB hugepages -## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation +## Assumptions for ARCH_ROMSTAGE_X86_64 reference implementation * 0-4GiB are identity mapped as WB * Memory above 4GiB isn't accessible * pagetables reside in CAR area `_pagetables` @@ -38,7 +38,7 @@ * 0-4GiB are identity mapped as WB * page tables reside in heap -## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation +## Assumptions for ARCH_RAMSTAGE_X86_64 reference implementation * pagetable are stored in fixed size heap area, initialized by assembly code * Memory above 4GiB is not accessible -- To view, visit https://review.coreboot.org/c/coreboot/+/33742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Gerrit-Change-Number: 33742 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disa...
by Aamir Bohra (Code Review) 14 Oct '20

14 Oct '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34563 ) Change subject: soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled ...................................................................... soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34563/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7eb413c..1058443 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -384,8 +384,12 @@ */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. -- To view, visit https://review.coreboot.org/c/coreboot/+/34563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Gerrit-Change-Number: 34563 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: payloads/iPXE: Enable support for verifying images
by Felix Singer (Code Review) 12 Oct '20

12 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31087 Change subject: payloads/iPXE: Enable support for verifying images ...................................................................... payloads/iPXE: Enable support for verifying images Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31087/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..a5bf7be 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1 Gerrit-Change-Number: 31087 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: cpu/intel: Use macro instead of numbers
by HAOUAS Elyes (Code Review) 11 Oct '20

11 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31196 Change subject: cpu/intel: Use macro instead of numbers ...................................................................... cpu/intel: Use macro instead of numbers Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 7 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/1 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 7994f0b..06b37a9 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -47,9 +47,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aa77964..08abdf5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -578,9 +578,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 6068be1..97ed39d 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -199,7 +199,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ if (eist) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e443026..1c0d081 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -65,7 +65,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; // TODO Do we want Deep C4 and Dynamic L2 shrinking? wrmsr(IA32_MISC_ENABLE, msr); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 33ad1e7..c2e0364 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -338,9 +338,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 19a22f1..fbc6964 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -67,7 +67,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ msr.lo |= (1 << 26); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 4e19896..adc0265 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -70,7 +70,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ msr.lo |= (1 << 26); -- To view, visit https://review.coreboot.org/c/coreboot/+/31196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Gerrit-Change-Number: 31196 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: [TESTONLY, DONOTMERGE] nb/gm45/rcven: Fill to the brim with spam
by Angel Pons (Code Review) 10 Sep '20

10 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34865 ) Change subject: [TESTONLY, DONOTMERGE] nb/gm45/rcven: Fill to the brim with spam ...................................................................... [TESTONLY, DONOTMERGE] nb/gm45/rcven: Fill to the brim with spam Change-Id: I4de1d7fc70877c11c37549cf1d723cbdcc6b1910 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 1 file changed, 162 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/34865/1 diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 7c7f56d..0385160 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -42,6 +42,7 @@ #define CxDRT3_C_SHIFT 7 #define CxDRT3_C_MASK (0xf << CxDRT3_C_SHIFT) #define CxDRT3_C(c) ((c << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) + /* group to byte-lane mapping: (cardF X group X 2 per group) */ static const char bytelane_map[2][4][2] = { /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, @@ -51,93 +52,156 @@ #define PH_BOUND 4 #define PH_STEP 2 #define PM_BOUND 3 -#define C_BOUND 16 +#define C_BOUND 16 typedef struct { - int c; - int pre; - int ph; - int t; + int c; // Coarse + int pre; // NOT! Preamble, per bytelane additional delay to Coarse + int ph; // Phase + int t; // TAP const int t_bound; - int p; + int p; // PI const int p_bound; } rec_timing_t; + +#define RCVEN_SPEW BIOS_DEBUG + +static void print_timings(int channel, int group, rec_timing_t timings[][4]) +{ + printk(RCVEN_SPEW, "ch %d, group %d: ", channel, group); + print_timing(&timings[channel][group]); +} + +static void print_timing(rec_timing_t *const timing) +{ + printk(RCVEN_SPEW, "\t%d.%d.%d.%d.%d\n", + timing->c, + timing->pre, + timing->ph, + timing->t, + timing->p + ); +} + static void normalize_rec_timing(rec_timing_t *const timing) { + unsigned int tmp = 0; + + printk(RCVEN_SPEW, "NORMALIZE START\n"); + while (timing->p >= timing->p_bound) { + tmp++; timing->t++; timing->p -= timing->p_bound; } + printk(RCVEN_SPEW, "\tafter %u t++: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->p < 0) { + tmp++; timing->t--; timing->p += timing->p_bound; } + printk(RCVEN_SPEW, "\tafter %u t--: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->t >= timing->t_bound) { + tmp++; timing->ph += PH_STEP; timing->t -= timing->t_bound; } + printk(RCVEN_SPEW, "\tafter %u ph++: " tmp); + print_timing(timing); + tmp = 0; + while (timing->t < 0) { + tmp++; timing->ph -= PH_STEP; timing->t += timing->t_bound; } + printk(RCVEN_SPEW, "\tafter %u ph--: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->ph >= PH_BOUND) { + tmp++; timing->c++; timing->ph -= PH_BOUND; } + printk(RCVEN_SPEW, "\tafter %u c++: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->ph < 0) { + tmp++; timing->c--; timing->ph += PH_BOUND; } - if (timing->c < 0 || timing->c >= C_BOUND) - die("Timing under-/overflow during " - "receive-enable calibration.\n"); + printk(RCVEN_SPEW, "\tafter %u c--: ", tmp); + print_timing(timing); + + if (timing->c < 0) + die("Timing under during receive-enable calibration.\n"); + + else if (timing->c >= C_BOUND) + die("Timing overflow during receive-enable calibration.\n"); + + printk(RCVEN_SPEW, "NORMALIZE END\n"); } static void rec_full_backstep(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "full backstep, "); timing->c--; } static void rec_half_backstep(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "half backstep, "); timing->ph -= PH_STEP; } static void rec_quarter_step(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "quarter step, "); timing->t += (timing->t_bound) >> 1; timing->p += (timing->t_bound & 1) * (timing->p_bound >> 1); } static void rec_quarter_backstep(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "quarter backstep, "); timing->t -= (timing->t_bound) >> 1; timing->p -= (timing->t_bound & 1) * (timing->p_bound >> 1); } static void rec_smallest_step(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "pi step, "); timing->p++; } -static void program_timing(int channel, int group, - rec_timing_t timings[][4]) +static void program_timing(int channel, int group, rec_timing_t timings[][4]) { rec_timing_t *const timing = &timings[channel][group]; + printk(RCVEN_SPEW, "%s: will normalize: ", __func__); + print_timing(timing); normalize_rec_timing(timing); /* C value is per channel. */ unsigned int mchbar = CxDRT3_MCHBAR(channel); - MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | - CxDRT3_C(timing->c); + MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | CxDRT3_C(timing->c); /* All other per group. */ mchbar = CxRECy_MCHBAR(channel, group); u32 reg = MCHBAR32(mchbar); reg &= ~CxRECy_TIMING_MASK; - reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | - CxRECy_PH(timing->ph) | CxRECy_PM(timing->pre); + reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | CxRECy_PH(timing->ph); + reg |= CxRECy_PM(timing->pre); MCHBAR32(mchbar) = reg; } static int read_dqs_level(const int channel, const int lane) { + unsigned int mchbar = 0x14f0 + (channel * 0x0100); MCHBAR32(mchbar) &= ~(1 << 9); MCHBAR32(mchbar) |= (1 << 9); @@ -146,58 +210,97 @@ read32((u32 *)raminit_get_rank_addr(channel, 0)); mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); - return MCHBAR32(mchbar) & (1 << 30); + + int level = MCHBAR32(mchbar) & (1 << 30); + + printk(RCVEN_SPEW, "DQS for channel %d lane %d: %s\n", + channel, lane, (level ? "HIGH" : "LOW"); + + return level; } static void find_dqs_low(const int channel, const int group, rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); + + printk(RCVEN_SPEW, "Look for DQS low, using quarter steps.\n"); /* Look for DQS low, using quarter steps. */ while (read_dqs_level(channel, lane_map[group][0]) || read_dqs_level(channel, lane_map[group][1])) { + rec_quarter_step(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void find_dqs_high(const int channel, const int group, rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); /* Look for _any_ DQS high, using quarter steps. */ while (!read_dqs_level(channel, lane_map[group][0]) && !read_dqs_level(channel, lane_map[group][1])) { + rec_quarter_step(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void find_dqs_edge_lowhigh(const int channel, const int group, - rec_timing_t timings[][4], - const char lane_map[][2]) + rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); + + printk(RCVEN_SPEW, "Advance beyond previous high to low transition.\n"); /* Advance beyond previous high to low transition. */ timings[channel][group].t += 2; + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); + printk(RCVEN_SPEW, "Coarsely look for DQS high.\n"); /* Coarsely look for DQS high. */ find_dqs_high(channel, group, timings, lane_map); + printk(RCVEN_SPEW, "Go back.\n"); /* Go back and perform finer search. */ rec_quarter_backstep(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); + + printk(RCVEN_SPEW, "Perform finer DQS high search.\n"); while (!read_dqs_level(channel, lane_map[group][0]) || !read_dqs_level(channel, lane_map[group][1])) { + rec_smallest_step(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void find_preamble(const int channel, const int group, rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); + + printk(RCVEN_SPEW, "Look for DQS low, backstepping.\n"); /* Look for DQS low, backstepping. */ while (read_dqs_level(channel, lane_map[group][0]) || read_dqs_level(channel, lane_map[group][1])) { + rec_full_backstep(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void receive_enable_calibration(const timings_t *const timings, @@ -213,11 +316,13 @@ dimms[0].card_type == 0xf, dimms[1].card_type == 0xf, }; + printk(RCVEN_SPEW, "cardF: ch0 = %d, ch1 = %d.\n", cardF[0], cardF[1]); - const unsigned int t_bound = - (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12; - const unsigned int p_bound = - (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; + const unsigned int t_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12; + const unsigned int p_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; + + printk(RCVEN_SPEW, "TAP bound = %u\n", t_bound); + printk(RCVEN_SPEW, "PI bound = %u\n", p_bound); rec_timing_t rec_timings[2][4] = { { @@ -233,35 +338,61 @@ } }; + printk(RCVEN_SPEW, "BEGIN MAIN LOOP\n"); + int ch, group; FOR_EACH_POPULATED_CHANNEL(dimms, ch) { const char (*const map)[2] = over_bytelane_map[cardF[ch]]; + printk(RCVEN_SPEW, "Begin channel %d\n", ch); + for (group = 0; group < 4; ++group) { + printk(RCVEN_SPEW, "RUNNING ON: channel %d, group %d\n", ch, group); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(ch, group, rec_timings); + find_dqs_low(ch, group, rec_timings, map); + find_dqs_edge_lowhigh(ch, group, rec_timings, map); rec_quarter_step(&rec_timings[ch][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(ch, group, rec_timings); + find_preamble(ch, group, rec_timings, map); + find_dqs_edge_lowhigh(ch, group, rec_timings, map); + rec_half_backstep(&rec_timings[ch][group]); + + printk(RCVEN_SPEW, "Normalize in %s: " __func__); + print_timings(channel, group, rec_timings) + normalize_rec_timing(&rec_timings[ch][group]); + if (cardF[ch]) { rec_timings[ch][group].t++; + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(ch, group, rec_timings); } + printk(RCVEN_SPEW, "DONE FOR: channel %d, group %d\n", ch, group); } int c_min = C_BOUND; for (group = 0; group < 4; ++group) { if (rec_timings[ch][group].c < c_min) c_min = rec_timings[ch][group].c; } + + printk(RCVEN_SPEW, "Min coarse for channel %d: %d\n", ch, c_min); + for (group = 0; group < 4; ++group) { - rec_timings[ch][group].pre = - rec_timings[ch][group].c - c_min; - rec_timings[ch][group].c = c_min; + rec_timings[ch][group].pre = rec_timings[ch][group].c - c_min; + rec_timings[ch][group].c = c_min; + + printk(RCVEN_SPEW, "%s: program final timings\n" __func__); program_timing(ch, group, rec_timings); + printk(RAM_DEBUG, "Final timings for "); printk(BIOS_DEBUG, "group %d, ch %d: %d.%d.%d.%d.%d\n", group, ch, @@ -271,18 +402,20 @@ rec_timings[ch][group].t, rec_timings[ch][group].p); } + printk(RCVEN_SPEW, "End channel %d\n", ch); } + printk(RCVEN_SPEW, "END MAIN LOOP\n"); } void raminit_receive_enable_calibration(const timings_t *const timings, const dimminfo_t *const dimms) { + printk(RCVEN_SPEW, "BEGIN rcven\n"); int ch; /* Setup group to byte-lane mapping. */ FOR_EACH_POPULATED_CHANNEL(dimms, ch) { - const char (*const map)[2] = - bytelane_map[dimms[ch].card_type == 0xf]; + const char (*const map)[2] = bytelane_map[dimms[ch].card_type == 0xf]; unsigned int group; for (group = 0; group < 4; ++group) { const unsigned int mchbar = CxRECy_MCHBAR(ch, group); @@ -299,9 +432,11 @@ MCHBAR32(0x14f0) = (MCHBAR32(0x14f0) & ~(3 << 9)) | (1 << 9); MCHBAR32(0x15f0) = (MCHBAR32(0x15f0) & ~(3 << 9)) | (1 << 9); + printk(RCVEN_SPEW, "Start calibration\n"); receive_enable_calibration(timings, dimms); MCHBAR32(0x12a4) &= ~(1 << 31); MCHBAR32(0x13a4) &= ~(1 << 31); + printk(RCVEN_SPEW, "FINISH rcven\n"); raminit_reset_readwrite_pointers(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4de1d7fc70877c11c37549cf1d723cbdcc6b1910 Gerrit-Change-Number: 34865 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in ...coreboot[master]: postcar_loader: Use size_t
by Patrick Rudolph (Code Review) 08 Sep '20

08 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32375 Change subject: postcar_loader: Use size_t ...................................................................... postcar_loader: Use size_t To make it easier to pop arguments from stack use size_t instead of int. This is a noop on x86_32. Change-Id: I226f79eaea425229eb2e3d9b9a312c9bf47d3b6a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar_loader.c 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32375/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 61b17a6..1cdf2db 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -310,8 +310,8 @@ struct postcar_frame { uintptr_t stack; uint32_t upper_mask; - int max_var_mtrrs; - int num_var_mtrrs; + size_t max_var_mtrrs; + size_t num_var_mtrrs; }; /* diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d62487e..a043f1b 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -25,13 +25,13 @@ #include <stage_cache.h> #include <timestamp.h> -static inline void stack_push(struct postcar_frame *pcf, uint32_t val) -{ - uint32_t *ptr; - - pcf->stack -= sizeof(val); - ptr = (void *)pcf->stack; - *ptr = val; +#define stack_push(pcf, val) \ +{ \ + typeof(val) *ptr; \ + \ + pcf->stack -= sizeof(val); \ + ptr = (void *)pcf->stack; \ + *ptr = val; \ } static void postcar_frame_prepare(struct postcar_frame *pcf) @@ -74,7 +74,7 @@ uint32_t mtrr_size; if (pcf->num_var_mtrrs >= pcf->max_var_mtrrs) { - printk(BIOS_ERR, "No more variable MTRRs: %d\n", + printk(BIOS_ERR, "No more variable MTRRs: %zd\n", pcf->max_var_mtrrs); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I226f79eaea425229eb2e3d9b9a312c9bf47d3b6a Gerrit-Change-Number: 32375 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019