Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review) 04 Jun '21
by Abdullah Zafar (Code Review) 04 Jun '21
04 Jun '21
Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231
Change subject: Add KASAN stubs to coreboot.
......................................................................
Add KASAN stubs to coreboot.
Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN.
Remove lint errors and warnings from kasan.c.
Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com>
Changes to be committed:
modified: src/Kconfig
modified: src/lib/Makefile.inc
new file: src/lib/kasan.c
Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577
---
M src/Kconfig
M src/lib/Makefile.inc
A src/lib/kasan.c
3 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1
diff --git a/src/Kconfig b/src/Kconfig
index 62b3818..96e746e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -219,6 +219,15 @@
coverage information in CBMEM for extraction from user space.
If unsure, say N.
+config KASAN
+ bool "Kernel Address sanitizer support"
+ default y
+ help
+ Instrument the code with checks for UAF and OOB erros. If unsure,
+ say N because it adds a small performance penalty and may abort
+ on code that happens to work in spite of the UB.
+
+
config UBSAN
bool "Undefined behavior sanitizer support"
default n
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 1350152..88afaaa 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -19,6 +19,12 @@
CFLAGS_ramstage += -fsanitize=undefined
endif
+ifeq ($(CONFIG_KASAN),y)
+ramstage-y += kasan.c
+CFLAGS_ramstage += -fsanitize=kernel-address
+endif
+
+
decompressor-y += decompressor.c
$(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4
$(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4
@@ -83,7 +89,7 @@
romstage-y += memrange.c
romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
-romstage-y += ramtest.c
+romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
ramstage-y += region_file.c
romstage-y += region_file.c
diff --git a/src/lib/kasan.c b/src/lib/kasan.c
new file mode 100644
index 0000000..3f482e9
--- /dev/null
+++ b/src/lib/kasan.c
@@ -0,0 +1,29 @@
+#include <stddef.h>
+
+/*
+ *Empty stubs for required by gcc to add compiler code
+ */
+void __asan_handle_no_return(void);
+void __asan_load1_noabort(unsigned long addr);
+void __asan_store1_noabort(unsigned long addr);
+void __asan_load2_noabort(unsigned long addr);
+void __asan_store2_noabort(unsigned long addr);
+void __asan_load4_noabort(unsigned long addr);
+void __asan_store4_noabort(unsigned long addr);
+void __asan_load8_noabort(unsigned long addr);
+void __asan_store8_noabort(unsigned long addr);
+void __asan_loadN_noabort(unsigned long addr, size_t x);
+void __asan_storeN_noabort(unsigned long addr, size_t x);
+
+
+void __asan_handle_no_return(void) { }
+void __asan_load1_noabort(unsigned long addr) { }
+void __asan_store1_noabort(unsigned long addr) { }
+void __asan_load2_noabort(unsigned long addr) { }
+void __asan_store2_noabort(unsigned long addr) { }
+void __asan_load4_noabort(unsigned long addr) { }
+void __asan_store4_noabort(unsigned long addr) { }
+void __asan_store8_noabort(unsigned long addr) { }
+void __asan_load8_noabort(unsigned long addr) { }
+void __asan_loadN_noabort(unsigned long addr, size_t i) { }
+void __asan_storeN_noabort(unsigned long addr, size_t i) { }
--
To view, visit https://review.coreboot.org/c/coreboot/+/32231
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577
Gerrit-Change-Number: 32231
Gerrit-PatchSet: 1
Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com>
Gerrit-MessageType: newchange
5
18
Change in coreboot[master]: soc/intel: Add Cascade Lake SP support
by Maxim Polyakov (Code Review) 17 May '21
by Maxim Polyakov (Code Review) 17 May '21
17 May '21
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support
......................................................................
soc/intel: Add Cascade Lake SP support
Adds Xeon Cascade Lake processor CPUIDs and Sky Lake-E DMI3 Host Bridge
PCI Id
Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/skylake/bootblock/report_platform.c
5 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index ac70d8c..2727a6f 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3176,6 +3176,7 @@
#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f
#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918
#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f
+#define PCI_DEVICE_ID_INTEL_SKL_ID_E 0x2020
#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904
#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c
#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index e0cee17..6a6ae17 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -56,11 +56,15 @@
{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },
{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 },
{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 },
+ { X86_VENDOR_INTEL, CPUID_SKYLAKE_HMU0 },
{ X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 },
{ X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 },
{ X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0 },
{ X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 },
{ X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 },
+ { X86_VENDOR_INTEL, CPUID_CASCADELAKE_A0 },
+ { X86_VENDOR_INTEL, CPUID_CASCADELAKE_BLR0 },
+ { X86_VENDOR_INTEL, CPUID_CASCADELAKE_BLR1 },
{ X86_VENDOR_INTEL, CPUID_CANNONLAKE_A0 },
{ X86_VENDOR_INTEL, CPUID_CANNONLAKE_B0 },
{ X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0 },
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index 5ef7641..cf04659 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -21,6 +21,10 @@
/* Supported CPUIDs for different SOCs */
#define CPUID_SKYLAKE_C0 0x406e2
#define CPUID_SKYLAKE_D0 0x406e3
+#define CPUID_SKYLAKE_HMU0 0x50654
+#define CPUID_CASCADELAKE_A0 0x50655
+#define CPUID_CASCADELAKE_BLR0 0x50656
+#define CPUID_CASCADELAKE_BLR1 0x50657
#define CPUID_SKYLAKE_HQ0 0x506e1
#define CPUID_SKYLAKE_HR0 0x506e3
#define CPUID_KABYLAKE_G0 0x406e8
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index b7964e6..30ff7c9 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -349,6 +349,7 @@
PCI_DEVICE_ID_INTEL_KBL_ID_S,
PCI_DEVICE_ID_INTEL_SKL_ID_H_EM,
PCI_DEVICE_ID_INTEL_SKL_ID_DT,
+ PCI_DEVICE_ID_INTEL_SKL_ID_E,
PCI_DEVICE_ID_INTEL_KBL_ID_U,
PCI_DEVICE_ID_INTEL_KBL_ID_Y,
PCI_DEVICE_ID_INTEL_KBL_ID_H,
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 279273f..f717678 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -41,6 +41,10 @@
{ CPUID_KABYLAKE_Y0, "Kabylake Y0" },
{ CPUID_KABYLAKE_HA0, "Kabylake H A0" },
{ CPUID_KABYLAKE_HB0, "Kabylake H B0" },
+ { CPUID_SKYLAKE_HMU0, "Skylake H0/M0/U0" },
+ { CPUID_CASCADELAKE_A0, "Cascade Lake A0" },
+ { CPUID_CASCADELAKE_BLR0, "Cascade Lake B0/L0/R0" },
+ { CPUID_CASCADELAKE_BLR1, "Cascade Lake B1/L1/R1" },
};
static struct {
@@ -56,6 +60,7 @@
{ PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" },
{ PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" },
{ PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" },
+ { PCI_DEVICE_ID_INTEL_SKL_ID_E, "Sky Lake-E" },
{ PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" },
{ PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"},
{ PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" },
--
To view, visit https://review.coreboot.org/c/coreboot/+/35126
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d
Gerrit-Change-Number: 35126
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
4
14
07 Apr '21
Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33582
Change subject: libpayload: nvme driver
......................................................................
libpayload: nvme driver
Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M payloads/libpayload/drivers/Makefile.inc
M payloads/libpayload/drivers/storage/Kconfig
A payloads/libpayload/drivers/storage/nvme.c
M payloads/libpayload/drivers/storage/storage.c
A payloads/libpayload/include/storage/nvme.h
M payloads/libpayload/include/storage/storage.h
M payloads/libpayload/include/x86/arch/io.h
A payloads/libpayload/sample/nvme_test.c
8 files changed, 429 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33582/1
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index 40e587c..676dbd3 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -77,6 +77,7 @@
libc-$(CONFIG_LP_STORAGE) += storage/storage.c
libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c
libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci_common.c
+libc-$(CONFIG_LP_STORAGE_NVME) += storage/nvme.c
ifeq ($(CONFIG_LP_STORAGE_ATA),y)
libc-$(CONFIG_LP_STORAGE_ATA) += storage/ata.c
libc-$(CONFIG_LP_STORAGE_ATA) += storage/ahci_ata.c
diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig
index 04e9a29..3eabf6a 100644
--- a/payloads/libpayload/drivers/storage/Kconfig
+++ b/payloads/libpayload/drivers/storage/Kconfig
@@ -57,3 +57,10 @@
help
If this option is selected only AHCI controllers which are known
to work will be used.
+
+config STORAGE_NVME
+ bool "Support for NVMe devices"
+ depends on STORAGE && PCI
+ default y
+ help
+ Select this option if you want support for NVMe devices
diff --git a/payloads/libpayload/drivers/storage/nvme.c b/payloads/libpayload/drivers/storage/nvme.c
new file mode 100644
index 0000000..871759d
--- /dev/null
+++ b/payloads/libpayload/drivers/storage/nvme.c
@@ -0,0 +1,331 @@
+#include <libpayload.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <pci.h>
+#include <pci/pci.h>
+#include <storage/nvme.h>
+#include <storage/storage.h>
+
+#define PCI_CLASS_CODE_NVME 0x0108
+
+// NVME Controller Configuration
+#define NVME_CC_EN (1 << 0)
+#define NVME_CC_CSS (0 << 4)
+#define NVME_CC_MPS (0 << 7)
+#define NVME_CC_AMS (0 << 11)
+#define NVME_CC_SHN (0 << 14)
+#define NVME_CC_IOSQES (6 << 16)
+#define NVME_CC_IOCQES (4 << 20)
+
+#define NVME_QUEUE_SIZE 2
+#define NVME_SQ_ENTRY_SIZE 64
+#define NVME_CQ_ENTRY_SIZE 16
+
+struct nvme_s_queue_entry {
+ uint32_t dw[16];
+};
+
+struct nvme_c_queue_entry {
+ uint32_t dw[4];
+};
+
+enum nvme_queue {
+ NVME_ADMIN_QUEUE = 0,
+ NVME_IO_QUEUE = 2,
+ ads = 0,
+ adc = 1,
+ ios = 2,
+ ioc = 3,
+};
+
+static storage_poll_t nvme_poll(struct storage_dev *dev);
+static void nvme_detach_device(struct storage_dev *dev);
+static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf);
+
+static int create_admin_queues(struct nvme_dev *nvme);
+static int create_io_submission_queue(struct nvme_dev *nvme);
+static int create_io_completion_queue(struct nvme_dev *nvme);
+static void delete_admin_queues(struct nvme_dev *nvme);
+static void delete_io_submission_queue(struct nvme_dev *nvme);
+static void delete_io_completion_queue(struct nvme_dev *nvme);
+static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd);
+static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count);
+
+
+static storage_poll_t nvme_poll(struct storage_dev *dev)
+{
+ return POLL_MEDIUM_PRESENT;
+}
+
+static void nvme_detach_device(struct storage_dev *dev)
+{
+ //nvme_free(dev->driver_struct);
+ // FIXME remove from list
+}
+
+static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf)
+{
+ void *buffer = memalign(0x1000, count * 512);
+ if (!buffer)
+ return 0;
+
+ for (int i = 0; i < count; i++) {
+ if (read((struct nvme_dev*)dev, buffer+(i*512), start + i, 1)) {
+ free(buffer);
+ return 0;
+ }
+ }
+
+ memcpy(buf, buffer, count * 512);
+ free(buffer);
+ return count;
+}
+
+static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count)
+{
+ if (count == 0)
+ return -1;
+
+ struct nvme_s_queue_entry e = {
+ .dw[0] = 0x02,
+ .dw[1] = 0x1,
+ .dw[6] = virt_to_phys(buffer),
+ .dw[10] = base,
+ .dw[11] = base >> 32,
+ .dw[12] = count - 1,
+ };
+ return nvme_cmd(nvme, ios, &e);
+}
+
+static void delete_io_submission_queue(struct nvme_dev *nvme)
+{
+ // TODO
+}
+
+static int create_io_submission_queue(struct nvme_dev *nvme)
+{
+ void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!sq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for io submission queue.\n");
+ return -1;
+ }
+ memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+
+ struct nvme_s_queue_entry e = {
+ .dw[0] = 0x01,
+ .dw[6] = virt_to_phys(sq_buffer),
+ .dw[10] = (NVME_QUEUE_SIZE << 16) | ios >> 1,
+ .dw[11] = (1 << 16) | 1,
+ };
+
+ int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
+ if (res) {
+ printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
+ free(sq_buffer);
+ return res;
+ }
+
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ nvme->queue[ios].base = sq_buffer;
+ nvme->queue[ios].bell = nvme->config + 0x1000 + (ios * (4 << cap_dstrd));
+ nvme->queue[ios].idx = 0;
+ return 0;
+}
+
+static void delete_io_completion_queue(struct nvme_dev *nvme)
+{
+ // TODO
+}
+
+static int create_io_completion_queue(struct nvme_dev *nvme)
+{
+ void *const cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!cq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for io competion queue.\n");
+ return -1;
+ }
+ memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+
+ const struct nvme_s_queue_entry e = {
+ .dw[0] = 0x05,
+ .dw[6] = virt_to_phys(cq_buffer),
+ .dw[10] = (NVME_QUEUE_SIZE << 16) | ioc >> 1,
+ .dw[11] = 1,
+ };
+
+ int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
+ if (res) {
+ printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
+ free(cq_buffer);
+ return res;
+ }
+
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ nvme->queue[ioc].base = cq_buffer;
+ nvme->queue[ioc].bell = nvme->config + 0x1000 + (ioc * (4 << cap_dstrd));
+ nvme->queue[ioc].idx = 0;
+ nvme->queue[ioc].round = 0;
+
+ return 0;
+}
+
+static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd)
+{
+ int sq = q, cq = q+1;
+
+ void *s_entry = nvme->queue[sq].base + (nvme->queue[sq].idx * NVME_SQ_ENTRY_SIZE);
+ memcpy(s_entry, cmd, NVME_SQ_ENTRY_SIZE);
+ write32(nvme->queue[sq].bell, nvme->queue[sq].idx + 1);
+ nvme->queue[sq].idx = (nvme->queue[sq].idx + 1) & 1;
+
+ struct nvme_c_queue_entry *c_entry = nvme->queue[cq].base + (nvme->queue[cq].idx * NVME_CQ_ENTRY_SIZE);
+ while (((c_entry->dw[3] >> 16 ) & 0x1) == nvme->queue[cq].round)
+ ; // FIXME timeout
+ write32(nvme->queue[cq].bell, nvme->queue[cq].idx + 1);
+ nvme->queue[cq].idx = (nvme->queue[cq].idx + 1) & 1;
+ if (nvme->queue[cq].idx == 0)
+ nvme->queue[cq].round = (nvme->queue[cq].round + 1) & 1;
+ return c_entry->dw[3] >> 17;
+}
+
+static void delete_admin_queues(struct nvme_dev *nvme)
+{
+ free(nvme->queue[ads].base);
+ free(nvme->queue[adc].base);
+ // TODO clean nvme admin queue struct ???
+}
+
+static int create_admin_queues(struct nvme_dev *nvme)
+{
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ write32(nvme->config + 0x24, NVME_QUEUE_SIZE << 16 | NVME_QUEUE_SIZE);
+
+ void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!sq_buffer) {
+ printf("NVMe ERROR: faild to allocated memory for admin submission queue\n");
+ return -1;
+ }
+ memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ write64(nvme->config + 0x28, virt_to_phys(sq_buffer));
+
+ nvme->queue[ads].base = sq_buffer;
+ nvme->queue[ads].bell = nvme->config + 0x1000 + (ads * (4 << cap_dstrd));
+ nvme->queue[ads].idx = 0;
+
+ void *cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!cq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for admin completion queue\n");
+ free(cq_buffer);
+ return -1;
+ }
+ memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ write64(nvme->config + 0x30, virt_to_phys(cq_buffer));
+
+ nvme->queue[adc].base = cq_buffer;
+ nvme->queue[adc].bell = nvme->config + 0x1000 + (adc * (4 << cap_dstrd));
+ nvme->queue[adc].idx = 0;
+ nvme->queue[adc].round = 0;
+
+ return 0;
+}
+
+static void nvme_init(pcidev_t dev)
+{
+ printf("NVMe init (Device %02x:%02x.%02x)\n", PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev));
+
+ void *pci_bar0 = phys_to_virt(pci_read_config32(dev, 0x10) & ~0x3ff);
+
+ if ( !(((read64(pci_bar0) >> 37 ) & 0xff) == 0x01)) {
+ printf("NVMe ERROR: PCIe device does not support the NVMe command set\n");
+ return;
+ }
+
+ struct nvme_dev *nvme = malloc(sizeof(*nvme));
+ if (!nvme) {
+ printf("NVMe ERROR: Faild to allocate buffer for nvme driver struct\n");
+ return;
+ }
+ nvme->storage_dev.port_type = PORT_TYPE_NVME;
+ nvme->storage_dev.poll = nvme_poll;
+ nvme->storage_dev.read_blocks512 = nvme_read_blocks512;
+ nvme->storage_dev.write_blocks512 = NULL; // not implemented
+ nvme->storage_dev.detach_device = nvme_detach_device;
+ nvme->config = pci_bar0;
+
+ uint32_t cc = 0;
+ write32(nvme->config + 0x1c, 0);
+
+ int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
+ do {
+ status = read32(nvme->config + 0x1c) & 0x3;
+ if (status == 0x2) {
+ printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n");
+ goto abort;
+ }
+ if (timeout < 0) {
+ printf("NVMe ERROR: Faild to disable controller. Timeout.\n");
+ goto abort;
+ }
+ timeout -= 10;
+ mdelay(10);
+ } while (status != 0x0);
+
+ if (create_admin_queues(nvme))
+ goto abort;
+
+ cc = NVME_CC_EN | NVME_CC_CSS | NVME_CC_MPS | NVME_CC_AMS |NVME_CC_SHN
+ | NVME_CC_IOSQES | NVME_CC_IOCQES;
+ write32(nvme->config + 0x14, cc);
+
+ timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
+ do {
+ status = read32(nvme->config + 0x1c) & 0x3;
+ if (status == 0x2) {
+ printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n");
+ goto abort;
+ }
+ if (timeout < 0) {
+ printf("NVMe ERROR: Faild to disable controller. Timeout.\n");
+ goto abort;
+ }
+ timeout -= 10;
+ mdelay(10);
+ } while (status != 0x1);
+
+ uint16_t command = pci_read_config16(dev, PCI_COMMAND);
+ pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
+
+ if (create_io_completion_queue(nvme))
+ goto abort;
+ if (create_io_submission_queue(nvme))
+ goto abort;
+
+ storage_attach_device((storage_dev_t*)nvme);
+ printf("NVMe init done.\n");
+ return;
+
+abort:
+ delete_io_submission_queue(nvme);
+ delete_io_completion_queue(nvme);
+ delete_admin_queues(nvme);
+ free(nvme);
+ printf("failed\n");
+ return;
+}
+
+void nvme_initialize(void)
+{
+ int bus, dev, func;
+ uint16_t class;
+
+ for (bus = 0; bus < 256; ++bus) {
+ for (dev = 0; dev < 32; ++dev) {
+ for (func = 0; func < 8; ++func) {
+ class = pci_read_config16(PCI_DEV(bus, dev, func), 0xa);
+ if (class == PCI_CLASS_CODE_NVME)
+ nvme_init(PCI_DEV(bus, dev, func));
+ }
+ }
+ }
+}
diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c
index a7141ee..55cb60d 100644
--- a/payloads/libpayload/drivers/storage/storage.c
+++ b/payloads/libpayload/drivers/storage/storage.c
@@ -31,6 +31,9 @@
#if CONFIG(LP_STORAGE_AHCI)
# include <storage/ahci.h>
#endif
+#if CONFIG(LP_STORAGE_NVME)
+#include <storage/nvme.h>
+#endif
#include <storage/storage.h>
@@ -113,4 +116,7 @@
#if CONFIG(LP_STORAGE_AHCI)
ahci_initialize();
#endif
+#if CONFIG(LP_STORAGE_NVME)
+ nvme_initialize();
+#endif
}
diff --git a/payloads/libpayload/include/storage/nvme.h b/payloads/libpayload/include/storage/nvme.h
new file mode 100644
index 0000000..090c6d0
--- /dev/null
+++ b/payloads/libpayload/include/storage/nvme.h
@@ -0,0 +1,22 @@
+#ifndef _STORAGE_NVME_H
+#define _STORAGE_NVME_H
+
+#include <stdint.h>
+#include "storage.h"
+
+struct nvme_dev {
+ storage_dev_t storage_dev;
+
+ void *config;
+ void *admin_s_queue;
+ struct {
+ void *base;
+ uint32_t *bell;
+ uint16_t idx; // bool pos 0 or 1
+ uint16_t round; // bool round 0 or 1+0xd
+ } queue[4];
+};
+
+void nvme_initialize(void);
+
+#endif /* _STORAGE_NVME_H */
diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h
index 2dc70b0..d1f998e 100644
--- a/payloads/libpayload/include/storage/storage.h
+++ b/payloads/libpayload/include/storage/storage.h
@@ -45,6 +45,7 @@
PORT_TYPE_IDE = (1 << 0),
PORT_TYPE_SATA = (1 << 1),
PORT_TYPE_USB = (1 << 2),
+ PORT_TYPE_NVME = (1 << 3),
} storage_port_t;
typedef enum {
diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h
index c417ce0..46836d9 100644
--- a/payloads/libpayload/include/x86/arch/io.h
+++ b/payloads/libpayload/include/x86/arch/io.h
@@ -64,6 +64,11 @@
return *((volatile uint32_t *)(addr));
}
+static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr)
+{
+ return *((volatile uint64_t *)(addr));
+}
+
static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
@@ -79,6 +84,11 @@
*((volatile uint32_t *)(addr)) = value;
}
+static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value)
+{
+ *((volatile uint64_t *)(addr)) = value;
+}
+
static inline unsigned int inl(int port)
{
unsigned long val;
diff --git a/payloads/libpayload/sample/nvme_test.c b/payloads/libpayload/sample/nvme_test.c
new file mode 100644
index 0000000..d2bdf10
--- /dev/null
+++ b/payloads/libpayload/sample/nvme_test.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Example file for libpayload. */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <storage/storage.h>
+
+#define STORAGE_ID 0
+
+int main(void)
+{
+ printf("---------- TEST PROGRAM BEGIN ----------\n");
+ storage_initialize();
+
+ void *buffer = memalign(0x1000, 0x2000);
+ storage_read_blocks512(STORAGE_ID, 0, 15, buffer);
+ printf("\nbuffer content:\n");
+ //hexdump(buffer,0x2000);
+
+ printf("----------- TEST PROGRAM END -----------\n");
+ halt();
+ return 0;
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/33582
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Gerrit-Change-Number: 33582
Gerrit-PatchSet: 1
Gerrit-Owner: Thomas Heijligen <src(a)posteo.de>
Gerrit-MessageType: newchange
7
28
29 Mar '21
jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33106
Change subject: WIP: temp for dispaly conflick
......................................................................
WIP: temp for dispaly conflick
Temp
squlash patches
google/krane: Add Panel TV101WUM-NL6 support.
google/kukui: Elaborate panel support for Kukui family boards.
google/kukui: Enable config for coreboot display
mediatek/mt8183: add dsi driver for mt8183
google/kukui: Enable display on internal panel
mediatek/mt8183: Add display driver
Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d
---
D 3rdparty/blobs
M src/mainboard/google/kukui/Kconfig
M src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/display.c
A src/mainboard/google/kukui/display.h
M src/mainboard/google/kukui/mainboard.c
A src/mainboard/google/kukui/panel_krane.c
A src/mainboard/google/kukui/panel_kukui.c
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/ddp.c
A src/soc/mediatek/mt8183/dsi.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/ddp.h
A src/soc/mediatek/mt8183/include/soc/dsi.h
14 files changed, 2,372 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33106/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
deleted file mode 160000
index ca6cfcd..0000000
--- a/3rdparty/blobs
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 6831d1e..5893722 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -37,6 +37,9 @@
select EC_GOOGLE_CHROMEEC_SPI
select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
select MAINBOARD_HAS_TPM2 if VBOOT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select HAVE_LINEAR_FRAMEBUFFER
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index a0556c1..8a023a5 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -22,6 +22,9 @@
ramstage-y += boardid.c
ramstage-y += chromeos.c
+ramstage-y += display.c
+ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c
+ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c
new file mode 100644
index 0000000..c7f7f91
--- /dev/null
+++ b/src/mainboard/google/kukui/display.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static void _display_startup(struct edid *edid,
+ struct lcm_init_table *init_table,
+ u32 init_table_size)
+{
+ int ret = 0;
+ u32 mipi_dsi_flags;
+
+ if ((edid == NULL) || (init_table == NULL)) {
+ printk(BIOS_ERR, "%s: wrong parameters\n", __func__);
+ return;
+ }
+
+ mipi_dsi_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM;
+
+ edid_set_framebuffer_bits_per_pixel(edid, 32, 0);
+
+ mtk_ddp_init();
+ ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4,
+ false, edid, init_table, init_table_size);
+
+ if (ret < 0) {
+ printk(BIOS_ERR, "dsi init fail\n");
+ return;
+ }
+
+ mtk_ddp_mode_set(edid);
+
+ set_vbe_mode_info_valid(edid, (uintptr_t)0);
+}
+
+static struct edid *get_edid(struct board_display_intf *intf)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info)
+ return info->edid;
+ return NULL;
+}
+
+static struct lcm_init_table *get_panel_init_table(struct board_display_intf
+ *intf, u32 *table_size)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info) {
+ *table_size = info->table_size;
+ return info->init_table;
+ }
+
+ *table_size = 0;
+ return NULL;
+}
+
+static const char *get_panel_name(struct board_display_intf *intf)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info)
+ return info->panel_name;
+ return NULL;
+}
+
+/* Exported Functions */
+
+struct board_display_intf *get_current_display_intf(void)
+{
+ return &panel_display_intf;
+}
+
+int update_panel_info(struct board_display_intf *intf)
+{
+ int i;
+ union panel_id id = intf->get_panel_id(intf);
+
+ if (intf->is_panel_id_valid(id)) {
+ for (i = 0; i < intf->all_panel_info_size; ++i) {
+ if (id.value == intf->all_panel_info[i].disp_id.value) {
+ intf->cur_panel_info = &intf->all_panel_info[i];
+ return 0;
+ }
+ }
+ }
+ return -1;
+}
+
+void display_startup(struct board_display_intf *intf)
+{
+ struct edid *edid;
+ u32 init_table_size;
+ struct lcm_init_table *init_table;
+
+ edid = get_edid(intf);
+ init_table = get_panel_init_table(intf, &init_table_size);
+ printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n",
+ __func__, get_panel_name(intf), init_table_size);
+ _display_startup(edid, init_table, init_table_size);
+}
diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h
new file mode 100644
index 0000000..d7b8bd9
--- /dev/null
+++ b/src/mainboard/google/kukui/display.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__
+#define __MAINBOARD_GOOGLE_DISPLAY_H__
+
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+
+#define MAKE_AS_A_STRING(arg) #arg
+
+enum kukui_panel_id {
+ PANEL_KUKUI_FIRST = 0,
+ PANEL_KUKUI_INNOLUX = 0,
+ PANEL_KUKUI_P097PFG_SSD2858,
+ PANEL_KUKUI_UNKNOWN,
+ PANEL_KUKUI_COUNT,
+ PANEL_KUKUI_UNINITIALIZED
+};
+
+enum krane_panel_id {
+ PANEL_KRANE_FIRST = 0,
+ PANEL_KRANE_BOE_TV101WUM_NL6,
+ PANEL_KRANE_UNKNOWN,
+ PANEL_KRANE_COUNT,
+ PANEL_KRANE_UNINITIALIZED
+};
+
+
+union panel_id {
+ enum kukui_panel_id kukui_panel;
+ enum krane_panel_id krane_panel;
+ int value;
+};
+
+struct panel_info {
+ union panel_id disp_id; /* the ID for panel */
+ const char *panel_name; /* display panel name */
+ int voltage; /* voltage of LCM_ID */
+ struct edid *edid; /* edid info of this panel */
+ struct lcm_init_table *init_table; /* init command table */
+ u32 table_size; /* init command table size */
+};
+
+#define PANEL(_panel_id, _voltage, _edid, _init_table) \
+ { \
+ .disp_id = {_panel_id},\
+ .panel_name = MAKE_AS_A_STRING(_panel_id),\
+ .voltage = _voltage,\
+ .edid = &_edid,\
+ .init_table = _init_table,\
+ .table_size = ARRAY_SIZE(_init_table)} \
+
+
+struct board_display_intf {
+ const char *board; /* board name */
+ struct panel_info *all_panel_info; /* all supported panel info */
+ u32 all_panel_info_size; /* num of supported panel */
+ /*
+ * Runtime member
+ */
+ struct panel_info *cur_panel_info; /* detected panel info */
+ /*
+ * board related functions
+ */
+
+ union panel_id (*get_panel_id)(struct board_display_intf *intf);
+ bool (*is_panel_id_valid)(union panel_id id);
+ int (*backlight)(struct board_display_intf *intf);
+ int (*power)(struct board_display_intf *intf);
+};
+
+/*
+ * Exported functions
+ */
+
+struct board_display_intf *get_current_display_intf(void);
+int update_panel_info(struct board_display_intf *intf);
+void display_startup(struct board_display_intf *intf);
+
+
+/*
+ * Panel Interface for boards
+ */
+extern struct board_display_intf panel_display_intf;
+
+#endif
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c
index 7a31909..4e7c20b 100644
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@@ -13,8 +13,17 @@
* GNU General Public License for more details.
*/
+#include <boardid.h>
+#include <bootmode.h>
+#include <console/console.h>
+#include <delay.h>
#include <device/device.h>
#include <soc/bl31_plat_params.h>
+#include "display.h"
+#include <edid.h>
+#include <gpio.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
#include <soc/gpio.h>
#include <soc/mmu_operations.h>
#include <soc/mtcmos.h>
@@ -70,6 +79,28 @@
static void mainboard_init(struct device *dev)
{
+ struct board_display_intf *cur_disp_intf = NULL;
+
+ if (display_init_required()) {
+ printk(BIOS_INFO, "Starting display init.\n");
+
+ cur_disp_intf = get_current_display_intf();
+ if (cur_disp_intf && !update_panel_info(cur_disp_intf)) {
+ mtcmos_display_power_on();
+ mtcmos_protect_display_bus();
+
+ cur_disp_intf->backlight(cur_disp_intf);
+ cur_disp_intf->power(cur_disp_intf);
+ display_startup(cur_disp_intf);
+ } else {
+ printk(BIOS_ERR,
+ "%s: Can't find correct display interface\n",
+ __func__);
+ }
+
+ } else
+ printk(BIOS_ERR, "Skipping display init.\n");
+
configure_emmc();
configure_usb();
configure_audio();
diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c
new file mode 100644
index 0000000..b6fa9a5
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_krane.c
@@ -0,0 +1,409 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid krane_boe_tv101wum_nl6_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1200x1920@60Hz",
+ .pixel_clock = 159425,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1200, .hbl = 164, .hso = 100, .hspw = 24, .hborder = 0,
+ .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 135, .y_mm = 216,
+ },
+};
+
+struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = {
+ {INIT_DCS_CMD, 1, { 0x10 } },
+ {DELAY_CMD, 34, {} },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x52 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x88 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x8B } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x1A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x01 } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xE6, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x1C } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x33 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xCF, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xD0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDA, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE2, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x43 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } },
+ {INIT_DCS_CMD, 2, { 0xE5, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x32 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x68 } },
+ {DELAY_CMD, 10, {} },
+ {INIT_DCS_CMD, 1, { 0x11 } },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, { 0x29 } },
+ {DELAY_CMD, 20, {} },
+
+};
+
+struct panel_info krane_panel_info[] = {
+ PANEL(PANEL_KRANE_BOE_TV101WUM_NL6,
+ 74000,
+ krane_boe_tv101wum_nl6_edid,
+ boe_tv101wum_nl6_init_cmd),
+ {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+static union panel_id krane_get_panel_id(struct board_display_intf *intf)
+{
+ return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6;
+};
+
+static bool krane_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KRANE_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int krane_backlight(struct board_display_intf *intf)
+{
+ gpio_output(GPIO(PERIPHERAL_EN13), 1);
+ gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */
+
+ return 0;
+};
+
+static int krane_power(struct board_display_intf *intf)
+{
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(1500);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ mdelay(5);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ mdelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(10);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf panel_display_intf = {
+ .board = "krane",
+ .all_panel_info = krane_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(krane_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &krane_get_panel_id,
+ .is_panel_id_valid = &krane_is_panel_id_valid,
+ .backlight = &krane_backlight,
+ .power = &krane_power,
+};
diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c
new file mode 100644
index 0000000..be76aa4
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_kukui.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid kukui_innolux_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "768x1024@60Hz",
+ .pixel_clock = 56900,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0,
+ .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 120, .y_mm = 160,
+ },
+};
+
+static struct lcm_init_table lcm_init_cmd[] = {
+ {INIT_DCS_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON} },
+ {DELAY_CMD, 120, {} },
+};
+
+static struct edid kukui_p097pfg_ssd2858_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1536x2048@60Hz",
+ .pixel_clock = 211660,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1536, .hbl = 160, .hso = 140, .hspw = 10, .hborder = 0,
+ .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 147, .y_mm = 196,
+ },
+};
+
+struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = {
+ /* SSD2858 config */
+ {INIT_GENENIC_CMD, 2, {0xff, 0x00} },
+ /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
+ * 27 Mhz => 985.5 Mhz
+ */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49} },
+ /* MTXDIV=1, SYSDIV=3 (=> 4) */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03} },
+ /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1
+ * MRXEE=1
+ */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f} },
+ {INIT_GENENIC_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d} },
+ {INIT_GENENIC_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00} },
+
+ {INIT_GENENIC_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x08, 0x45} },
+ {INIT_GENENIC_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00} },
+ {INIT_GENENIC_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04} },
+ /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
+ {INIT_GENENIC_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49} },
+ {INIT_GENENIC_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00} },
+ /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08} },
+ {INIT_GENENIC_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06} },
+ /* DSI0 enable (default: probably not needed) */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f} },
+ /* DSI1 enable */
+ {INIT_GENENIC_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f} },
+
+ /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18} },
+ /* VACT= 0x800 (2048} }, VFP= 0x14, HFP=0x50 */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50} },
+ /* HACT=0x300 (768) */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00} },
+ {INIT_GENENIC_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00} },
+
+ /* Take panel out of sleep. */
+ {INIT_GENENIC_CMD, 2, {0xff, 0x01} },
+ {INIT_DCS_CMD, 1, {0x11} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x29} },
+ {DELAY_CMD, 20, {} },
+ {INIT_GENENIC_CMD, 2, {0xff, 0x00} },
+
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x11} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x29} },
+ {DELAY_CMD, 20, {} },
+};
+
+struct panel_info kukui_panel_info[] = {
+ PANEL(PANEL_KUKUI_INNOLUX,
+ 74000,
+ kukui_innolux_edid,
+ lcm_init_cmd),
+ PANEL(PANEL_KUKUI_P097PFG_SSD2858,
+ 212000,
+ kukui_p097pfg_ssd2858_edid,
+ lcm_p097pfg_ssd2858_init_cmd),
+ {{PANEL_KUKUI_UNKNOWN}, "PANEL_KUKUI_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+static union panel_id kukui_get_panel_id(struct board_display_intf *intf)
+{
+ if (board_id() < 2)
+ return (union panel_id)PANEL_KUKUI_INNOLUX;
+ else
+ return (union panel_id)PANEL_KUKUI_P097PFG_SSD2858;
+};
+
+static bool kukui_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KUKUI_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int kukui_backlight(struct board_display_intf *intf)
+{
+ gpio_output(GPIO(PERIPHERAL_EN13), 1);
+ gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */
+
+ return 0;
+};
+
+static int kukui_power(struct board_display_intf *intf)
+{
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ gpio_output(GPIO(BPI_BUS3), 0);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ gpio_output(GPIO(SIM2_SIO), 1);
+ gpio_output(GPIO(BPI_OLAT1), 1);
+ gpio_output(GPIO(SIM2_SCLK), 1);
+ mdelay(20);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ gpio_output(GPIO(BPI_BUS3), 1);
+ mdelay(20);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf panel_display_intf = {
+ .board = "kukui",
+ .all_panel_info = kukui_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(kukui_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &kukui_get_panel_id,
+ .is_panel_id_valid = &kukui_is_panel_id_valid,
+ .backlight = &kukui_backlight,
+ .power = &kukui_power,
+};
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index ce498c1..0afa335 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -42,6 +42,8 @@
ramstage-y += auxadc.c
ramstage-y += ../common/cbmem.c emi.c
+ramstage-y += ddp.c
+ramstage-y += dsi.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c
new file mode 100644
index 0000000..d845981
--- /dev/null
+++ b/src/soc/mediatek/mt8183/ddp.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <edid.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
+#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
+
+static void disp_config_main_path_connection(void)
+{
+ write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L);
+ write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0);
+ write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L);
+ write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR);
+ write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0);
+ write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+ write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+ /* Clock source from DSI0 */
+ write32(&disp_mutex->mutex[0].ctl,
+ MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+ write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
+{
+ write32(&disp_ovl[idx]->roi_size, height << 16 | width);
+ write32(&disp_ovl[idx]->roi_bgclr, color);
+}
+
+static void ovl_layer_enable(u32 idx)
+{
+ write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0));
+ write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
+
+ setbits_le32(&disp_ovl[idx]->src_con, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+ setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void rdma_start(u32 idx)
+{
+ setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN);
+}
+
+static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh)
+{
+ u32 threshold;
+ u32 reg;
+ u32 fifo_size;
+
+ clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width);
+ clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height);
+
+ /*
+ * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the
+ * FIFO pseudo size reset default of 8 KiB. Set the output threshold to
+ * 6 microseconds with 7/6 overhead to account for blanking, and with a
+ * pixel depth of 4 bytes:
+ */
+ fifo_size = RDMA_FIFO_SIZE_0 * KiB;
+
+ threshold = width * height * vrefresh * 4 * 7 / 1000000;
+
+ if (threshold > fifo_size)
+ threshold = fifo_size;
+
+ reg = RDMA_FIFO_UNDERFLOW_EN |
+ RDMA_FIFO_PSEUDO_SIZE(fifo_size) |
+ RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
+
+ write32(&disp_rdma[idx]->fifo_con, reg);
+}
+
+static void color_start(u32 width, u32 height)
+{
+ write32(&disp_color->width, width);
+ write32(&disp_color->height, height);
+ write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
+ write32(&disp_color->start, BIT(0));
+}
+
+static void aal_start(u32 width, u32 height)
+{
+ write32(&disp_aal->size, height << 16 | width);
+ write32(&disp_aal->en, PQ_EN);
+}
+
+static void ccorr_start(u32 width, u32 height)
+{
+ write32(&disp_ccorr->size, height << 16 | width);
+ write32(&disp_ccorr->cfg, PQ_RELAY_MODE);
+ write32(&disp_ccorr->en, PQ_EN);
+}
+
+static void dither_start(u32 width, u32 height)
+{
+ write32(&disp_dither->size, height << 16 | width);
+ write32(&disp_dither->cfg, PQ_RELAY_MODE);
+ write32(&disp_dither->en, PQ_EN);
+}
+
+static void gamma_start(u32 width, u32 height)
+{
+ write32(&disp_gamma->size, height << 16 | width);
+ write32(&disp_gamma->en, PQ_EN);
+}
+
+static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height)
+{
+ write32(&disp_ovl[idx]->layer[0].con, fmt << 12);
+ write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width);
+ write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF);
+
+ ovl_layer_enable(idx);
+}
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+ u32 idx = 0;
+
+ /* Setup OVL */
+ for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+ u32 color = 0;
+
+ if (idx == 0)
+ color = 0xFF0000FF;
+
+ ovl_set_roi(idx, width, height, color);
+ }
+
+ idx = 0;
+ rdma_config(idx, width, height, vrefresh);
+ color_start(width, height);
+ ccorr_start(width, height);
+ aal_start(width, height);
+ gamma_start(width, height);
+ dither_start(width, height);
+ disp_config_main_path_connection();
+ disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+ clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+ clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
+ CG_CON1_DISP_DSI0_INTERFACE);
+}
+
+static void disp_m4u_port_off(void)
+{
+ write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0);
+}
+
+void mtk_ddp_init(void)
+{
+ disp_clock_on();
+ disp_m4u_port_off();
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+ u32 fmt = OVL_INFMT_RGBA8888;
+ u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+ u32 idx = 0;
+ u32 width = edid->mode.ha;
+ u32 height = edid->mode.va;
+ u32 vrefresh = edid->mode.refresh;
+
+ main_disp_path_setup(width, height, vrefresh);
+ rdma_start(idx);
+ ovl_layer_config(idx, fmt, bpp, width, height);
+ ovl_bgclr_in_sel(idx+1);
+}
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
new file mode 100644
index 0000000..3bfada7
--- /dev/null
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -0,0 +1,485 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/mmio.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/dsi.h>
+#include <timer.h>
+
+static void dsi_write32(void *a, uint32_t v)
+{
+ write32(a, v);
+}
+
+static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v)
+{
+ clrsetbits_le32(a, m, v);
+}
+
+static void dsi_clrbits_le32(void *a, uint32_t m)
+{
+ clrbits_le32(a, m);
+}
+
+static void dsi_setbits_le32(void *a, uint32_t m)
+{
+ setbits_le32(a, m);
+}
+
+static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
+ const struct edid *edid)
+{
+ unsigned int txdiv, txdiv0, txdiv1;
+ u64 pcw;
+ int data_rate;
+ u32 bpp;
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB565:
+ bpp = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bpp = 18;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bpp = 24;
+ break;
+ }
+
+ data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes;
+
+ printk(BIOS_INFO, "data_rate: %u bps\n", data_rate);
+
+ if (data_rate >= 2000000000) {
+ txdiv = 1;
+ txdiv0 = 0;
+ txdiv1 = 0;
+ } else if (data_rate >= 1000000000) {
+ txdiv = 2;
+ txdiv0 = 1;
+ txdiv1 = 0;
+ } else if (data_rate >= 500000000) {
+ txdiv = 4;
+ txdiv0 = 2;
+ txdiv1 = 0;
+ } else if (data_rate > 250000000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ txdiv1 = 0;
+ } else if (data_rate >= 125000000) {
+ txdiv = 16;
+ txdiv0 = 4;
+ txdiv1 = 0;
+ } else {
+ printk(BIOS_ERR, "data rate (%u) must be >=50. Please check "
+ "pixel clock (%u), bpp (%u), number of lanes (%u)\n",
+ data_rate, edid->mode.pixel_clock, bpp,
+ lanes);
+ return -1;
+ }
+
+ dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10));
+
+ dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ udelay(30);
+ dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+
+ pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1));
+ pcw <<= 24;
+ pcw /= 26;
+
+ dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw);
+ dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
+ txdiv0 << 8);
+ udelay(30);
+ dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+
+ /* BG_LPF_EN / BG_CORE_EN */
+ dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180);
+ udelay(40);
+ dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0);
+
+ /* Switch OFF each Lane */
+ dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+ dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
+
+ return data_rate;
+}
+
+static void mtk_dsi_phy_timconfig(u32 data_rate,
+ struct mtk_phy_timing *phy_timing)
+{
+ u32 timcon0, timcon1, timcon2, timcon3;
+
+ timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 |
+ phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24;
+ timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 |
+ phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24;
+ timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 |
+ phy_timing->clk_hs_trail << 24;
+ timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 |
+ phy_timing->clk_hs_exit << 16;
+
+ dsi_write32(&dsi->dsi_phy_timecon0, timcon0);
+ dsi_write32(&dsi->dsi_phy_timecon1, timcon1);
+ dsi_write32(&dsi->dsi_phy_timecon2, timcon2);
+ dsi_write32(&dsi->dsi_phy_timecon3, timcon3);
+}
+
+static void mtk_dsi_reset(void)
+{
+ dsi_write32(&dsi->dsi_con_ctrl, 1);
+ dsi_write32(&dsi->dsi_con_ctrl, 0);
+}
+
+static void mtk_dsi_clk_hs_mode_enable(void)
+{
+ dsi_setbits_le32(&dsi->dsi_phy_lccon, 1);
+}
+
+static void mtk_dsi_set_mode(u32 mode_flags)
+{
+ u32 tmp_reg1 = 0;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+ tmp_reg1 = SYNC_PULSE_MODE;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+ tmp_reg1 = BURST_MODE;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ tmp_reg1 = SYNC_PULSE_MODE;
+ }
+
+ dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1);
+}
+
+static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes,
+ const struct edid *edid,
+ struct mtk_phy_timing *phy_timing)
+{
+ u32 ui, cycle_time, data_rate;
+ u32 bit_per_pixel;
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
+
+ data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes;
+
+ ui = 1000 / (data_rate / 1000) + 1U;
+ cycle_time = 8000 / (data_rate / 1000) + 1U;
+
+ phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);
+ phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time);
+ phy_timing->da_hs_zero = DIV_ROUND_UP((180 + 6 * ui), cycle_time);
+ phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time);
+
+ if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare)
+ phy_timing->da_hs_zero -= phy_timing->da_hs_prepare;
+
+ phy_timing->ta_go = 4U * phy_timing->lpx;
+ phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;
+ phy_timing->ta_get = 5U * phy_timing->lpx;
+ phy_timing->da_hs_exit = 2U * phy_timing->lpx;
+
+ phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time);
+ phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU;
+
+ phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time);
+ phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time);
+ phy_timing->clk_hs_exit = 2U * phy_timing->lpx;
+}
+
+static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
+{
+ u32 tmp_reg = 0;
+
+ switch (lanes) {
+ case 1:
+ tmp_reg = 1 << 2;
+ break;
+ case 2:
+ tmp_reg = 3 << 2;
+ break;
+ case 3:
+ tmp_reg = 7 << 2;
+ break;
+ case 4:
+ default:
+ tmp_reg = 0xf << 2;
+ break;
+ }
+
+ tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
+ tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+
+ dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg);
+}
+
+static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
+ const struct edid *edid,
+ struct mtk_phy_timing *phy_timing,
+ u32 lanes)
+{
+ u32 hsync_active_byte;
+ u32 hbp_byte;
+ u32 hfp_byte, tmp_hfp_byte;
+ u32 vbp_byte;
+ u32 vfp_byte;
+ u32 bpp;
+ u32 packet_fmt;
+ u32 hactive;
+ u32 data_phy_cycles;
+
+ if (format == MIPI_DSI_FMT_RGB565)
+ bpp = 2;
+ else
+ bpp = 3;
+
+ vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
+ edid->mode.vborder;
+ vfp_byte = edid->mode.vso - edid->mode.vborder;
+
+ dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw);
+ dsi_write32(&dsi->dsi_vbp_nl, vbp_byte);
+ dsi_write32(&dsi->dsi_vfp_nl, vfp_byte);
+ dsi_write32(&dsi->dsi_vact_nl, edid->mode.va);
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
+ edid->mode.hborder) * bpp - 10;
+ else
+ hbp_byte = (edid->mode.hbl - edid->mode.hso -
+ edid->mode.hborder) * bpp - 10;
+
+ hsync_active_byte = edid->mode.hspw * bpp - 10;
+
+ data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
+ phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2;
+
+ tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+ if (tmp_hfp_byte > data_phy_cycles * lanes + 18) {
+ hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18;
+ } else {
+ printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");
+ hfp_byte = tmp_hfp_byte;
+ }
+ } else {
+ if (tmp_hfp_byte > data_phy_cycles * lanes + 12) {
+ hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12;
+ } else {
+ printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");
+ hfp_byte = tmp_hfp_byte;
+ }
+ }
+
+ dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte);
+ dsi_write32(&dsi->dsi_hbp_wc, hbp_byte);
+ dsi_write32(&dsi->dsi_hfp_wc, hfp_byte);
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB888:
+ packet_fmt = PACKED_PS_24BIT_RGB888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ packet_fmt = LOOSELY_PS_18BIT_RGB666;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ packet_fmt = PACKED_PS_18BIT_RGB666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ packet_fmt = PACKED_PS_16BIT_RGB565;
+ break;
+ default:
+ packet_fmt = PACKED_PS_24BIT_RGB888;
+ break;
+ }
+
+ hactive = edid->mode.ha;
+ packet_fmt |= (hactive * bpp) & DSI_PS_WC;
+
+ dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt);
+ dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive);
+}
+
+static void mtk_dsi_start(void)
+{
+ dsi_clrbits_le32(&dsi->dsi_start, 1);
+ dsi_setbits_le32(&dsi->dsi_start, 1);
+}
+
+static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type)
+{
+ struct stopwatch sw;
+ u8 *tx_buf = data;
+ u8 cmdq_size;
+ u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0;
+
+ while (read32(&dsi->dsi_intsta) & (1 << 31)) {
+ printk(BIOS_ERR, "%s wait dsi no busy\n", __func__);
+ mdelay(20);
+ }
+
+ dsi_write32(&dsi->dsi_intsta, 0);
+
+ if (MTK_DSI_HOST_IS_READ(type))
+ config = BTA;
+ else
+ config = (len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+ if (len > 2) {
+ cmdq_size = 1 + (len + 3) / 4;
+ cmdq_off = 4;
+ cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+ reg_val = (len << 16) | (type << 8) | config;
+ } else {
+ cmdq_size = 1;
+ cmdq_off = 2;
+ cmdq_mask = CONFIG | DATA_ID;
+ reg_val = (type << 8) | config;
+ }
+
+ for (i = 0; i < 0x20; i = i + 4)
+ dsi_write32((void *)DSI_BASE + 0x200 + i, 0);
+
+ for (i = 0; i < len; i++) {
+ dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 +
+ ((cmdq_off + i) & (0xfffffffc)),
+ (0xff << (((i + cmdq_off) & 3) * 8)),
+ tx_buf[i] << (((i + cmdq_off) & 3) * 8));
+ }
+
+ dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val);
+ dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size);
+ mtk_dsi_start();
+
+ stopwatch_init_usecs_expire(&sw, 400);
+ do {
+ intsta_0 = read32(&dsi->dsi_intsta);
+ if (intsta_0 & CMD_DONE_INT_FLAG)
+ break;
+ udelay(4);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(intsta_0 & CMD_DONE_INT_FLAG))
+ printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n");
+}
+
+static void push_table(struct lcm_init_table *init_cmd, u32 count)
+{
+ u32 cmd, i;
+ u32 type;
+
+ for (i = 0; i < count; i++) {
+ cmd = init_cmd[i].cmd;
+
+ switch (cmd) {
+ case DELAY_CMD:
+ mdelay(init_cmd[i].len);
+ break;
+
+ case END_OF_TABLE:
+ break;
+
+ case INIT_DCS_CMD:
+ switch (init_cmd[i].len) {
+ case 0:
+ return;
+
+ case 1:
+ type = MIPI_DSI_DCS_SHORT_WRITE;
+ break;
+
+ case 2:
+ type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+ break;
+
+ default:
+ type = MIPI_DSI_DCS_LONG_WRITE;
+ break;
+ }
+ mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type);
+ break;
+
+ case INIT_GENENIC_CMD:
+ default:
+ switch (init_cmd[i].len) {
+ case 0:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
+ break;
+ case 1:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
+ break;
+ case 2:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
+ break;
+ default:
+ type = MIPI_DSI_GENERIC_LONG_WRITE;
+ break;
+ }
+ mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type);
+ break;
+ }
+ }
+}
+
+int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+ const struct edid *edid, struct lcm_init_table *init_cmd,
+ u32 count)
+{
+ int data_rate;
+ struct mtk_phy_timing phy_timing;
+
+ mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing);
+
+ data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid);
+
+ if (data_rate < 0)
+ return -1;
+
+ dsi_write32(&dsi->dsi_force_commit, 3);
+ mtk_dsi_reset();
+ mtk_dsi_phy_timconfig(data_rate, &phy_timing);
+ mtk_dsi_rxtx_control(mode_flags, lanes);
+ mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes);
+ mtk_dsi_clk_hs_mode_enable();
+ push_table(init_cmd, count);
+ mtk_dsi_set_mode(mode_flags);
+ mtk_dsi_start();
+
+ return 0;
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b9..75202dd 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -47,12 +47,27 @@
IOCFG_RT_BASE = IO_PHYS + 0x01C50000,
IOCFG_RM_BASE = IO_PHYS + 0x01D20000,
IOCFG_RB_BASE = IO_PHYS + 0x01D30000,
+ MIPITX_BASE = IO_PHYS + 0x01E50000,
IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
IOCFG_LM_BASE = IO_PHYS + 0x01E80000,
IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
SSUSB_SIF_BASE = IO_PHYS + 0x01F40300,
+ MMSYS_BASE = IO_PHYS + 0x04000000,
+ DISP_OVL0_BASE = IO_PHYS + 0x04008000,
+ DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000,
+ DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000,
+ DISP_RDMA0_BASE = IO_PHYS + 0x0400B000,
+ DISP_RDMA1_BASE = IO_PHYS + 0x0400C000,
+ DISP_COLOR0_BASE = IO_PHYS + 0x0400E000,
+ DISP_CCORR0_BASE = IO_PHYS + 0x0400F000,
+ DISP_AAL0_BASE = IO_PHYS + 0x04010000,
+ DISP_GAMMA0_BASE = IO_PHYS + 0x04011000,
+ DISP_DITHER0_BASE = IO_PHYS + 0x04012000,
+ DSI_BASE = IO_PHYS + 0x04014000,
+ DISP_MUTEX_BASE = IO_PHYS + 0x04016000,
+ SMI_LARB0 = IO_PHYS + 0x04017000,
SMI_BASE = IO_PHYS + 0x04019000,
};
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h
new file mode 100644
index 0000000..1914868
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/ddp.h
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DDP_REG_H_
+#define _DDP_REG_H_
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+ u32 reserved_0x000[64]; /* 0x000 */
+ u32 mmsys_cg_con0; /* 0x100 */
+ u32 mmsys_cg_set0; /* 0x104 */
+ u32 mmsys_cg_clr0; /* 0x108 */
+ u32 reserved_0x10C; /* 0x10C */
+ u32 mmsys_cg_con1; /* 0x110 */
+ u32 mmsys_cg_set1; /* 0x114 */
+ u32 mmsys_cg_clr1; /* 0x118 */
+ u32 reserved_0x11C[889]; /* 0x11C */
+ u32 disp_ovl0_mout_en; /* 0xF00 */
+ u32 disp_ovl0_2l_mout_en; /* 0xF04 */
+ u32 disp_ovl1_2l_mout_en; /* 0xF08 */
+ u32 disp_dither0_mout_en; /* 0xF0C */
+ u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */
+ u32 disp_path0_sel_in; /* 0xF24 */
+ u32 reserved_0xF28; /* 0xF28 */
+ u32 dsi0_sel_in; /* 0xF2C */
+ u32 dpi0_sel_in; /* 0xF30 */
+ u32 reserved_0xF34; /* 0xF34 */
+ u32 disp_ovl0_2l_sel_in; /* 0xF38 */
+ u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */
+ u32 disp_rdma0_sout_sel_in; /* 0xF50 */
+ u32 disp_rdma1_sout_sel_in; /* 0xF54 */
+ u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */
+ u32 dpi0_sel_sout_sel_in; /* 0xF64 */
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+ (void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+ Configures free-run clock gating 0
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON0_SMI_COMMON = BIT(0),
+ CG_CON0_SMI_LARB0 = BIT(1),
+ CG_CON0_GALS_COMMON0 = BIT(3),
+ CG_CON0_GALS_COMMON1 = BIT(4),
+ CG_CON0_DISP_OVL0 = BIT(20),
+ CG_CON0_DISP_OVL0_2L = BIT(21),
+ CG_CON0_DISP_OVL1_2L = BIT(22),
+ CG_CON0_DISP_RDMA0 = BIT(23),
+ CG_CON0_DISP_RDMA1 = BIT(24),
+ CG_CON0_DISP_WDMA0 = BIT(25),
+ CG_CON0_DISP_COLOR0 = BIT(26),
+ CG_CON0_DISP_CCORR0 = BIT(27),
+ CG_CON0_DISP_AAL0 = BIT(28),
+ CG_CON0_DISP_GAMMA0 = BIT(29),
+ CG_CON0_DISP_DITHER0 = BIT(30),
+ CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON |
+ CG_CON0_SMI_LARB0 |
+ CG_CON0_GALS_COMMON0 |
+ CG_CON0_GALS_COMMON1 |
+ CG_CON0_DISP_OVL0 |
+ CG_CON0_DISP_OVL0_2L |
+ CG_CON0_DISP_RDMA0 |
+ CG_CON0_DISP_COLOR0 |
+ CG_CON0_DISP_CCORR0 |
+ CG_CON0_DISP_AAL0 |
+ CG_CON0_DISP_DITHER0 |
+ CG_CON0_DISP_GAMMA0,
+ CG_CON0_ALL = 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+ Configures free-run clock gating 1
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON1_DISP_DSI0 = BIT(0),
+ CG_CON1_DISP_DSI0_INTERFACE = BIT(1),
+ CG_CON1_DISP_26M = BIT(7),
+
+ CG_CON1_ALL = 0xffffffff
+};
+
+enum {
+ OVL0_MOUT_EN_RDMA0 = BIT(0),
+ OVL0_MOUT_EN_OVL0_2L = BIT(4),
+ OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0),
+ OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4),
+ DITHER0_MOUT_EN_DISP_DSI0 = BIT(0),
+};
+
+enum {
+ DISP_PATH0_SEL_IN_OVL0 = 0,
+ DISP_PATH0_SEL_IN_OVL0_2L = 1,
+ DSI0_SEL_IN_DITHER0_MOUT = 0,
+ DSI0_SEL_IN_RDMA0 = 1,
+ RDMA0_SOUT_SEL_IN_DSI0 = 0,
+ RDMA0_SOUT_SEL_IN_COLOR = 1,
+};
+
+struct disp_mutex_regs {
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[6];
+ struct {
+ u32 en;
+ u32 dummy;
+ u32 rst;
+ u32 ctl;
+ u32 mod;
+ u32 reserved[3];
+ } mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+ MUTEX_MOD_DISP_RDMA0 = BIT(0),
+ MUTEX_MOD_DISP_RDMA1 = BIT(1),
+ MUTEX_MOD_DISP_OVL0 = BIT(9),
+ MUTEX_MOD_DISP_OVL0_2L = BIT(10),
+ MUTEX_MOD_DISP_OVL1_2L = BIT(11),
+ MUTEX_MOD_DISP_WDMA0 = BIT(12),
+ MUTEX_MOD_DISP_COLOR0 = BIT(13),
+ MUTEX_MOD_DISP_CCORR0 = BIT(14),
+ MUTEX_MOD_DISP_AAL0 = BIT(15),
+ MUTEX_MOD_DISP_GAMMA0 = BIT(16),
+ MUTEX_MOD_DISP_DITHER0 = BIT(17),
+ MUTEX_MOD_DISP_PWM0 = BIT(28),
+ MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L |
+ MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 |
+ MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 |
+ MUTEX_MOD_DISP_GAMMA0 |
+ MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+ MUTEX_SOF_SINGLE_MODE = 0,
+ MUTEX_SOF_DSI0 = 1,
+ MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ovl_regs {
+ u32 sta;
+ u32 inten;
+ u32 intsta;
+ u32 en;
+ u32 trig;
+ u32 rst;
+ u32 reserved_0x018[2];
+ u32 roi_size;
+ u32 datapath_con;
+ u32 roi_bgclr;
+ u32 src_con;
+ struct {
+ u32 con;
+ u32 srckey;
+ u32 src_size;
+ u32 offset;
+ u32 reserved0;
+ u32 pitch;
+ u32 reserved1[2];
+ } layer[4];
+ u32 reserved_0x0B0[4];
+ struct {
+ u32 ctrl;
+ u32 reserved0;
+ u32 mem_gmc_setting;
+ u32 mem_slow_con;
+ u32 fifo_ctrl;
+ u32 reserved1[3];
+ } rdma[4];
+ u32 reserved_0x140[880];
+ u32 reserved_0xF00[16];
+ u32 l0_addr;
+ u32 reserved_0xF44[7];
+ u32 l1_addr;
+ u32 reserved_0xF64[7];
+ u32 l2_addr;
+ u32 reserved_0xF84[7];
+ u32 l3_addr;
+};
+
+check_member(disp_ovl_regs, l3_addr, 0xFA0);
+static struct disp_ovl_regs *const disp_ovl[2] = {
+ (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE
+};
+
+struct disp_rdma_regs {
+ u32 int_enable;
+ u32 int_status;
+ u32 reserved0[2];
+ u32 global_con;
+ u32 size_con_0;
+ u32 size_con_1;
+ u32 target_line;
+ u32 reserved1;
+ u32 mem_con;
+ u32 reserved2;
+ u32 mem_src_pitch;
+ u32 mem_gmc_setting_0;
+ u32 mem_gmc_setting_1;
+ u32 mem_slow_con;
+ u32 mem_gmc_setting_2;
+ u32 fifo_con;
+ u32 reserved3[4];
+ u32 cf[3][3];
+ u32 cf_pre_add[3];
+ u32 cf_post_add[3];
+ u32 dummy;
+ u32 debug_out_sel;
+};
+
+enum {
+ RDMA_ENGINE_EN = BIT(0),
+ RDMA_FIFO_UNDERFLOW_EN = BIT(31),
+ RDMA_FIFO_SIZE_0 = 5, /* 5K */
+ RDMA_VREFRESH = 60, /* vrefresh 60HZ */
+ RDMA_MEM_GMC = 0x40402020,
+};
+
+check_member(disp_rdma_regs, debug_out_sel, 0x94);
+static struct disp_rdma_regs *const disp_rdma[2] = {
+ (void *)DISP_RDMA0_BASE,
+ (void *)DISP_RDMA1_BASE,
+};
+
+struct disp_color_regs {
+ u8 reserved0[1024];
+ u32 cfg_main;
+ u8 reserved1[2044];
+ u32 start;
+ u8 reserved2[76];
+ u32 width;
+ u32 height;
+};
+
+check_member(disp_color_regs, height, 0xC54);
+static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE;
+
+enum {
+ COLOR_BYPASS_ALL = BIT(7),
+ COLOR_SEQ_SEL = BIT(13),
+};
+
+struct disp_pq_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+
+enum {
+ PQ_EN = BIT(0),
+ PQ_RELAY_MODE = BIT(0),
+};
+
+static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+enum {
+ SMI_LARB_NON_SEC_CON = 0x380,
+};
+
+enum OVL_INPUT_FORMAT {
+ OVL_INFMT_RGB565 = 0,
+ OVL_INFMT_RGB888 = 1,
+ OVL_INFMT_RGBA8888 = 2,
+ OVL_INFMT_ARGB8888 = 3,
+ OVL_INFMT_UYVY = 4,
+ OVL_INFMT_YUYV = 5,
+ OVL_INFMT_UNKNOWN = 16,
+
+ OVL_COLOR_BASE = 30,
+ OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE,
+ OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE,
+ OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE,
+ OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
new file mode 100644
index 0000000..dc89668
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -0,0 +1,487 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_REG_H_
+#define _DSI_REG_H_
+
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+enum mipi_dsi_pixel_format {
+ MIPI_DSI_FMT_RGB888,
+ MIPI_DSI_FMT_RGB666,
+ MIPI_DSI_FMT_RGB666_PACKED,
+ MIPI_DSI_FMT_RGB565
+};
+
+/* video mode */
+enum {
+ MIPI_DSI_MODE_VIDEO = BIT(0),
+ /* video burst mode */
+ MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
+ /* video pulse mode */
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
+ /* enable auto vertical count mode */
+ MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
+ /* enable hsync-end packets in vsync-pulse and v-porch area */
+ MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
+ /* disable hfront-porch area */
+ MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
+ /* disable hback-porch area */
+ MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
+ /* disable hsync-active area */
+ MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
+ /* flush display FIFO on vsync pulse */
+ MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
+ /* disable EoT packets in HS mode */
+ MIPI_DSI_MODE_EOT_PACKET = BIT(9),
+ /* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+ MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
+ /* transmit data in low power */
+ MIPI_DSI_MODE_LPM = BIT(11)
+};
+
+struct dsi_regs {
+ u32 dsi_start;
+ u8 reserved0[4];
+ u32 dsi_inten;
+ u32 dsi_intsta;
+ u32 dsi_con_ctrl;
+ u32 dsi_mode_ctrl;
+ u32 dsi_txrx_ctrl;
+ u32 dsi_psctrl;
+ u32 dsi_vsa_nl;
+ u32 dsi_vbp_nl;
+ u32 dsi_vfp_nl;
+ u32 dsi_vact_nl;
+ u32 dsi_lfr_con;
+ u32 dsi_lfr_sta;
+ u32 dsi_size_con;
+ u32 dsi_vfp_early_stop;
+ u32 reserved1[4];
+ u32 dsi_hsa_wc;
+ u32 dsi_hbp_wc;
+ u32 dsi_hfp_wc;
+ u32 dsi_bllp_wc;
+ u32 dsi_cmdq_size;
+ u32 dsi_hstx_cklp_wc;
+ u8 reserved2[156];
+ u32 dsi_phy_lccon;
+ u32 dsi_phy_ld0con;
+ u8 reserved3[4];
+ u32 dsi_phy_timecon0;
+ u32 dsi_phy_timecon1;
+ u32 dsi_phy_timecon2;
+ u32 dsi_phy_timecon3;
+ u8 reserved4[16];
+ u32 dsi_vm_cmd_con;
+ u8 reserved5[92];
+ u32 dsi_force_commit;
+ u8 reserved6[108];
+ u32 dsi_cmdq0;
+};
+
+check_member(dsi_regs, dsi_phy_lccon, 0x104);
+check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
+check_member(dsi_regs, dsi_force_commit, 0x190);
+check_member(dsi_regs, dsi_cmdq0, 0x200);
+static struct dsi_regs *const dsi = (void *)DSI_BASE;
+
+#define DELAY_CMD 0
+#define END_OF_TABLE 1
+#define INIT_GENENIC_CMD 2
+#define INIT_DCS_CMD 3
+
+struct lcm_init_table {
+ u32 cmd;
+ u32 len;
+ u8 data[64];
+};
+
+struct mtk_phy_timing {
+ u8 lpx;
+ u8 da_hs_prepare;
+ u8 da_hs_zero;
+ u8 da_hs_trail;
+
+ u8 ta_go;
+ u8 ta_sure;
+ u8 ta_get;
+ u8 da_hs_exit;
+
+ u8 clk_hs_zero;
+ u8 clk_hs_trail;
+
+ u8 clk_hs_prepare;
+ u8 clk_hs_post;
+ u8 clk_hs_exit;
+};
+
+/* DSI_INTSTA */
+enum {
+ LPRX_RD_RDY_INT_FLAG = BIT(0),
+ CMD_DONE_INT_FLAG = BIT(1),
+ TE_RDY_INT_FLAG = BIT(2),
+ VM_DONE_INT_FLAG = BIT(3),
+ EXT_TE_RDY_INT_FLAG = BIT(4),
+ DSI_BUSY = BIT(31),
+};
+
+/* DSI_CON_CTRL */
+enum {
+ DSI_RESET = BIT(0),
+ DSI_EN = BIT(1),
+ DSI_DUAL = BIT(4),
+};
+
+/* DSI_MODE_CTRL */
+enum {
+ MODE = 3,
+ CMD_MODE = 0,
+ SYNC_PULSE_MODE = 1,
+ SYNC_EVENT_MODE = 2,
+ BURST_MODE = 3,
+ FRM_MODE = BIT(16),
+ MIX_MODE = BIT(17)
+};
+
+/* DSI_PSCTRL */
+enum {
+ DSI_PS_WC = 0x3fff,
+ DSI_PS_SEL = (3 << 16),
+ PACKED_PS_16BIT_RGB565 = (0 << 16),
+ LOOSELY_PS_18BIT_RGB666 = (1 << 16),
+ PACKED_PS_18BIT_RGB666 = (2 << 16),
+ PACKED_PS_24BIT_RGB888 = (3 << 16)
+};
+
+/* DSI_CMDQ_SIZE */
+enum {
+ CMDQ_SIZE = 0x3f,
+};
+
+/* DSI_PHY_LCCON */
+enum {
+ LC_HS_TX_EN = BIT(0),
+ LC_ULPM_EN = BIT(1),
+ LC_WAKEUP_EN = BIT(2)
+};
+
+/*DSI_PHY_LD0CON */
+enum {
+ LD0_RM_TRIG_EN = BIT(0),
+ LD0_ULPM_EN = BIT(1),
+ LD0_WAKEUP_EN = BIT(2)
+};
+
+enum {
+ LPX = (0xff << 0),
+ HS_PRPR = (0xff << 8),
+ HS_ZERO = (0xff << 16),
+ HS_TRAIL = (0xff << 24)
+};
+
+enum {
+ TA_GO = (0xff << 0),
+ TA_SURE = (0xff << 8),
+ TA_GET = (0xff << 16),
+ DA_HS_EXIT = (0xff << 24)
+};
+
+enum {
+ CONT_DET = (0xff << 0),
+ CLK_ZERO = (0xf << 16),
+ CLK_TRAIL = (0xff << 24)
+};
+
+enum {
+ CLK_HS_PRPR = (0xff << 0),
+ CLK_HS_POST = (0xff << 8),
+ CLK_HS_EXIT = (0xf << 16)
+};
+
+/* DSI_VM_CMD_CON */
+enum {
+ VM_CMD_EN = BIT(0),
+ TS_VFP_EN = BIT(5),
+};
+
+/* DSI_CMDQ0 */
+enum {
+ CONFIG = (0xff << 0),
+ SHORT_PACKET = 0,
+ LONG_PACKET = 2,
+ BTA = BIT(2),
+ DATA_ID = (0xff << 8),
+ DATA_0 = (0xff << 16),
+ DATA_1 = (0xff << 24),
+};
+
+#define MIPITX_LANE_CON 0x000c
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON0 0x002c
+#define MIPITX_PLL_CON1 0x0030
+#define MIPITX_PLL_CON2 0x0034
+#define MIPITX_PLL_CON3 0x0038
+#define MIPITX_PLL_CON4 0x003c
+#define MIPITX_D2_SW_CTL_EN 0x0144
+#define MIPITX_D0_SW_CTL_EN 0x0244
+#define MIPITX_CK_CKMODE_EN 0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN 0x0344
+#define MIPITX_D1_SW_CTL_EN 0x0444
+#define MIPITX_D3_SW_CTL_EN 0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+ u32 dsi_con;
+ u32 dsi_clock_lane;
+ u32 dsi_data_lane[4];
+ u8 reserved0[40];
+ u32 dsi_top_con;
+ u32 dsi_bg_con;
+ u8 reserved1[8];
+ u32 dsi_pll_con0;
+ u32 dsi_pll_con1;
+ u32 dsi_pll_con2;
+ u32 dsi_pll_con3;
+ u32 dsi_pll_chg;
+ u32 dsi_pll_top;
+ u32 dsi_pll_pwr;
+ u8 reserved2[4];
+ u32 dsi_rgs;
+ u32 dsi_gpi_en;
+ u32 dsi_gpi_pull;
+ u32 dsi_phy_sel;
+ u32 dsi_sw_ctrl_en;
+ u32 dsi_sw_ctrl_con0;
+ u32 dsi_sw_ctrl_con1;
+ u32 dsi_sw_ctrl_con2;
+ u32 dsi_dbg_con;
+ u32 dsi_dbg_out;
+ u32 dsi_apb_async_sta;
+};
+
+check_member(mipi_tx_regs, dsi_top_con, 0x40);
+check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
+
+static void *const mipi_tx = (void *)MIPITX_BASE;
+
+/* MIPITX_DSI_CON */
+enum {
+ RG_DSI_LDOCORE_EN = BIT(0),
+ RG_DSI_CKG_LDOOUT_EN = BIT(1),
+ RG_DSI_BCLK_SEL = (3 << 2),
+ RG_DSI_LD_IDX_SEL = (7 << 4),
+ RG_DSI_PHYCLK_SEL = (2 << 8),
+ RG_DSI_DSICLK_FREQ_SEL = BIT(10),
+ RG_DSI_LPTX_CLMP_EN = BIT(11)
+};
+
+/* MIPITX_DSI_CLOCK_LANE */
+enum {
+ LDOOUT_EN = BIT(0),
+ CKLANE_EN = BIT(1),
+ IPLUS1 = BIT(2),
+ LPTX_IPLUS2 = BIT(3),
+ LPTX_IMINUS = BIT(4),
+ LPCD_IPLUS = BIT(5),
+ LPCD_IMLUS = BIT(6),
+ RT_CODE = (0xf << 8)
+};
+
+/* MIPITX_DSI_TOP_CON */
+enum {
+ RG_DSI_LNT_INTR_EN = BIT(0),
+ RG_DSI_LNT_HS_BIAS_EN = BIT(1),
+ RG_DSI_LNT_IMP_CAL_EN = BIT(2),
+ RG_DSI_LNT_TESTMODE_EN = BIT(3),
+ RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
+ RG_DSI_LNT_AIO_SEL = (7 << 8),
+ RG_DSI_PAD_TIE_LOW_EN = BIT(11),
+ RG_DSI_DEBUG_INPUT_EN = BIT(12),
+ RG_DSI_PRESERVE = (7 << 13)
+};
+
+/* MIPITX_DSI_BG_CON */
+enum {
+ RG_DSI_BG_CORE_EN = BIT(0),
+ RG_DSI_BG_CKEN = BIT(1),
+ RG_DSI_BG_DIV = (0x3 << 2),
+ RG_DSI_BG_FAST_CHARGE = BIT(4),
+ RG_DSI_V12_SEL = (7 << 5),
+ RG_DSI_V10_SEL = (7 << 8),
+ RG_DSI_V072_SEL = (7 << 11),
+ RG_DSI_V04_SEL = (7 << 14),
+ RG_DSI_V032_SEL = (7 << 17),
+ RG_DSI_V02_SEL = (7 << 20),
+ rsv_23 = BIT(23),
+ RG_DSI_BG_R1_TRIM = (0xf << 24),
+ RG_DSI_BG_R2_TRIM = (0xf << 28)
+};
+
+/* MIPITX_DSI_PLL_CON0 */
+enum {
+ RG_DSI_MPPLL_PLL_EN = BIT(0),
+ RG_DSI_MPPLL_PREDIV = (3 << 1),
+ RG_DSI_MPPLL_TXDIV0 = (3 << 3),
+ RG_DSI_MPPLL_TXDIV1 = (3 << 5),
+ RG_DSI_MPPLL_POSDIV = (7 << 7),
+ RG_DSI_MPPLL_MONVC_EN = BIT(10),
+ RG_DSI_MPPLL_MONREF_EN = BIT(11),
+ RG_DSI_MPPLL_VOD_EN = BIT(12)
+};
+
+/* MIPITX_DSI_PLL_CON1 */
+enum {
+ RG_DSI_MPPLL_SDM_FRA_EN = BIT(0),
+ RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1),
+ RG_DSI_MPPLL_SDM_SSC_EN = BIT(2),
+ RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16)
+};
+
+/* MIPITX_DSI_PLL_PWR */
+enum {
+ RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
+ RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
+ RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+ MIPI_DSI_V_SYNC_START = 0x01,
+ MIPI_DSI_V_SYNC_END = 0x11,
+ MIPI_DSI_H_SYNC_START = 0x21,
+ MIPI_DSI_H_SYNC_END = 0x31,
+
+ MIPI_DSI_COLOR_MODE_OFF = 0x02,
+ MIPI_DSI_COLOR_MODE_ON = 0x12,
+ MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
+ MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
+
+ MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
+ MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
+ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
+
+ MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
+ MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
+ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
+
+ MIPI_DSI_DCS_SHORT_WRITE = 0x05,
+ MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
+
+ MIPI_DSI_DCS_READ = 0x06,
+
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
+
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
+ MIPI_DSI_NULL_PACKET = 0x09,
+ MIPI_DSI_BLANKING_PACKET = 0x19,
+ MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
+ MIPI_DSI_DCS_LONG_WRITE = 0x39,
+
+ MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
+ MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+ MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
+ MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
+ MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
+ MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+ MIPI_DCS_NOP = 0x00,
+ MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_RED_CHANNEL = 0x06,
+ MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
+ MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
+ MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
+ MIPI_DCS_GET_POWER_MODE = 0x0A,
+ MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
+ MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
+ MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
+ MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
+ MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
+ MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
+ MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
+ MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
+ MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_EXIT_INVERT_MODE = 0x20,
+ MIPI_DCS_ENTER_INVERT_MODE = 0x21,
+ MIPI_DCS_SET_GAMMA_CURVE = 0x26,
+ MIPI_DCS_SET_DISPLAY_OFF = 0x28,
+ MIPI_DCS_SET_DISPLAY_ON = 0x29,
+ MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
+ MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
+ MIPI_DCS_WRITE_MEMORY_START = 0x2C,
+ MIPI_DCS_WRITE_LUT = 0x2D,
+ MIPI_DCS_READ_MEMORY_START = 0x2E,
+ MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_SCROLL_AREA = 0x33,
+ MIPI_DCS_SET_TEAR_OFF = 0x34,
+ MIPI_DCS_SET_TEAR_ON = 0x35,
+ MIPI_DCS_SET_ADDRESS_MODE = 0x36,
+ MIPI_DCS_SET_SCROLL_START = 0x37,
+ MIPI_DCS_EXIT_IDLE_MODE = 0x38,
+ MIPI_DCS_ENTER_IDLE_MODE = 0x39,
+ MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
+ MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
+ MIPI_DCS_GET_SCANLINE = 0x45,
+ MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+};
+
+#define MTK_DSI_HOST_IS_READ(type) \
+ ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+ (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+ (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+ (type == MIPI_DSI_DCS_READ))
+
+extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+ const struct edid *edid,
+ struct lcm_init_table *init_cmd,
+ u32 count);
+
+#endif
--
To view, visit https://review.coreboot.org/c/coreboot/+/33106
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d
Gerrit-Change-Number: 33106
Gerrit-PatchSet: 1
Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-MessageType: newchange
3
6
Change in ...coreboot[master]: getac/p470: Let clang-format handle the coding style
by Patrick Georgi (Code Review) 26 Mar '21
by Patrick Georgi (Code Review) 26 Mar '21
26 Mar '21
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31652
Change subject: getac/p470: Let clang-format handle the coding style
......................................................................
getac/p470: Let clang-format handle the coding style
Also make the format mandatory for the board.
Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A .clang-format-scope
M src/mainboard/getac/p470/acpi_tables.c
M src/mainboard/getac/p470/cstates.c
M src/mainboard/getac/p470/ec_oem.c
M src/mainboard/getac/p470/ec_oem.h
M src/mainboard/getac/p470/gpio.c
M src/mainboard/getac/p470/hda_verb.c
M src/mainboard/getac/p470/irq_tables.c
M src/mainboard/getac/p470/mainboard.c
M src/mainboard/getac/p470/mainboard.h
M src/mainboard/getac/p470/mptable.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/getac/p470/smihandler.c
13 files changed, 179 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31652/1
diff --git a/.clang-format-scope b/.clang-format-scope
new file mode 100644
index 0000000..96c588c
--- /dev/null
+++ b/.clang-format-scope
@@ -0,0 +1 @@
+src/mainboard/getac
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 162c20a..460f345 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -33,7 +33,7 @@
gnvs->cmbp = 0x00;
}
-static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
+static long acpi_create_ecdt(acpi_ecdt_t *ecdt)
{
/* Attention: Make sure these match the values from
* the DSDT's ec.asl
@@ -43,7 +43,7 @@
acpi_header_t *header = &(ecdt->header);
- memset((void *) ecdt, 0, ecdt_len);
+ memset((void *)ecdt, 0, ecdt_len);
/* fill out header fields */
memcpy(header->signature, "ECDT", 4);
@@ -61,7 +61,7 @@
ecdt->ec_control.addrl = 0x66;
ecdt->ec_control.addrh = 0;
- ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */
+ ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */
ecdt->ec_data.bit_width = 8;
ecdt->ec_data.bit_offset = 0;
ecdt->ec_data.addrl = 0x62;
@@ -73,14 +73,12 @@
strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));
- header->checksum =
- acpi_checksum((void *) ecdt, ecdt_len);
+ header->checksum = acpi_checksum((void *)ecdt, ecdt_len);
return header->length;
}
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
+unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start,
acpi_rsdp_t *rsdp)
{
unsigned long current;
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
index 38b0d30..2f1f815 100644
--- a/src/mainboard/getac/p470/cstates.c
+++ b/src/mainboard/getac/p470/cstates.c
@@ -16,21 +16,21 @@
#include <southbridge/intel/i82801gx/i82801gx.h>
static acpi_cstate_t cst_entries[] = {
- {
- /* ACPI C1 / CPU C1 */
- 1, 0x01, 1000,
- { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
- },
- {
- /* ACPI C2 / CPU C2 */
- 2, 0x01, 500,
- { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
- },
- {
- /* ACPI C3 / CPU C2 */
- 2, 0x11, 250,
- { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
- },
+ {/* ACPI C1 / CPU C1 */
+ 1,
+ 0x01,
+ 1000,
+ {ACPI_ADDRESS_SPACE_FIXED, 1, 2, {1}, 0, 0}},
+ {/* ACPI C2 / CPU C2 */
+ 2,
+ 0x01,
+ 500,
+ {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
+ {/* ACPI C3 / CPU C2 */
+ 2,
+ 0x11,
+ 250,
+ {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
};
int get_cst_entries(acpi_cstate_t **entries)
diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c
index 8740167..49b7274 100644
--- a/src/mainboard/getac/p470/ec_oem.c
+++ b/src/mainboard/getac/p470/ec_oem.c
@@ -32,7 +32,7 @@
}
if (!timeout) {
printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n",
- command);
+ command);
// return -1;
}
@@ -51,8 +51,7 @@
printk(BIOS_SPEW, ".");
}
if (!timeout) {
- printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n",
- data);
+ printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", data);
// return -1;
}
@@ -112,12 +111,18 @@
{
u8 ec_sc = inb(EC_OEM_SC);
printk(BIOS_DEBUG, "Embedded Controller Status: ");
- if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT ");
- if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT ");
- if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST ");
- if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD ");
- if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF ");
- if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF ");
+ if (ec_sc & (1 << 6))
+ printk(BIOS_DEBUG, "SMI_EVT ");
+ if (ec_sc & (1 << 5))
+ printk(BIOS_DEBUG, "SCI_EVT ");
+ if (ec_sc & (1 << 4))
+ printk(BIOS_DEBUG, "BURST ");
+ if (ec_sc & (1 << 3))
+ printk(BIOS_DEBUG, "CMD ");
+ if (ec_sc & (1 << 1))
+ printk(BIOS_DEBUG, "IBF ");
+ if (ec_sc & (1 << 0))
+ printk(BIOS_DEBUG, "OBF ");
printk(BIOS_DEBUG, "\n");
return ec_sc;
diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h
index 5d56107..ba42d7e 100644
--- a/src/mainboard/getac/p470/ec_oem.h
+++ b/src/mainboard/getac/p470/ec_oem.h
@@ -17,23 +17,35 @@
#ifndef _MAINBOARD_EC_OEM_H
#define _MAINBOARD_EC_OEM_H
-#define EC_OEM_DATA 0x68
-#define EC_OEM_SC 0x6c
+#define EC_OEM_DATA 0x68
+#define EC_OEM_SC 0x6c
/* EC_SC input */
-#define EC_SMI_EVT (1 << 6) // 1: SMI event pending
-#define EC_SCI_EVT (1 << 5) // 1: SCI event pending
-#define EC_BURST (1 << 4) // controller is in burst mode
-#define EC_CMD (1 << 3) // 1: byte in data register is command
- // 0: byte in data register is data
-#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec)
-#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host)
+// 1: SMI event pending
+#define EC_SMI_EVT (1 << 6)
+
+// 1: SCI event pending
+#define EC_SCI_EVT (1 << 5)
+
+// controller is in burst mode
+#define EC_BURST (1 << 4)
+
+// 1: byte in data register is command
+// 0: byte in data register is data
+#define EC_CMD (1 << 3)
+
+// 1: input buffer full (data ready for ec)
+#define EC_IBF (1 << 1)
+
+// 1: output buffer full (data ready for host)
+#define EC_OBF (1 << 0)
+
/* EC_SC output */
-#define RD_EC 0x80 // Read Embedded Controller
-#define WR_EC 0x81 // Write Embedded Controller
-#define BE_EC 0x82 // Burst Enable Embedded Controller
-#define BD_EC 0x83 // Burst Disable Embedded Controller
-#define QR_EC 0x84 // Query Embedded Controller
+#define RD_EC 0x80 // Read Embedded Controller
+#define WR_EC 0x81 // Write Embedded Controller
+#define BE_EC 0x82 // Burst Enable Embedded Controller
+#define BD_EC 0x83 // Burst Disable Embedded Controller
+#define QR_EC 0x84 // Query Embedded Controller
int send_ec_oem_command(u8 command);
int send_ec_oem_data(u8 data);
diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c
index be52a86..2785bca 100644
--- a/src/mainboard/getac/p470/gpio.c
+++ b/src/mainboard/getac/p470/gpio.c
@@ -74,8 +74,7 @@
.gpio8 = GPIO_INVERT,
};
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio33 = GPIO_MODE_GPIO,
@@ -100,16 +99,18 @@
};
const struct pch_gpio_map mainboard_gpio_map = {
- .set1 = {
- .mode = &pch_gpio_set1_mode,
- .direction = &pch_gpio_set1_direction,
- .level = &pch_gpio_set1_level,
- .blink = &pch_gpio_set1_blink,
- .invert = &pch_gpio_set1_invert,
- },
- .set2 = {
- .mode = &pch_gpio_set2_mode,
- .direction = &pch_gpio_set2_direction,
- .level = &pch_gpio_set2_level,
- },
+ .set1 =
+ {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 =
+ {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
};
diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c
index e858a35..1ec2205 100644
--- a/src/mainboard/getac/p470/hda_verb.c
+++ b/src/mainboard/getac/p470/hda_verb.c
@@ -17,9 +17,9 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
- 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262
- 0x10714700, // Subsystem ID
- 0x0000000d, // Number of jacks
+ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262
+ 0x10714700, // Subsystem ID
+ 0x0000000d, // Number of jacks
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0000 */
AZALIA_SUBVENDOR(0x0, 0x10EC0000),
diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c
index 06d1492..fa491bf 100644
--- a/src/mainboard/getac/p470/irq_tables.c
+++ b/src/mainboard/getac/p470/irq_tables.c
@@ -17,18 +17,19 @@
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x27b0, /* Device */
- 0, /* miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xf, /* u8 checksum. */
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x27b0, /* Device */
+ 0, /* miniport */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0xf, /* u8 checksum. */
{
+ // clang-format off
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
@@ -48,8 +49,8 @@
{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
- }
-};
+ // clang-format on
+ }};
unsigned long write_pirq_routing_table(unsigned long addr)
{
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 5d271fd..0645424 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -25,7 +25,7 @@
#include "mainboard.h"
-#define MAX_LCD_BRIGHTNESS 0xd8
+#define MAX_LCD_BRIGHTNESS 0xd8
static void ec_enable(void)
{
@@ -77,7 +77,8 @@
static void mainboard_init(struct device *dev)
{
ec_enable();
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3);
}
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h
index 0e6b24c..d074960 100644
--- a/src/mainboard/getac/p470/mainboard.h
+++ b/src/mainboard/getac/p470/mainboard.h
@@ -13,6 +13,5 @@
struct acpi_rsdp;
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
+unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start,
struct acpi_rsdp *rsdp);
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index c00102d..80c33df 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -41,28 +41,42 @@
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
/* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2,
+ 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2,
+ 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2,
+ 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2,
+ 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2,
+ 0x11);
/* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2,
+ 0x10);
// riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2,
+ 0x14);
// riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2,
+ 0x15);
// riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2,
+ 0x16);
/* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2,
+ 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3f80664..a591307 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -36,18 +36,18 @@
printk(BIOS_SPEW, "\n Initializing drive bay...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
- gpios |= (1 << 0); // GPIO33 = ODD
- gpios |= (1 << 1); // GPIO34 = IDE_RST#
- outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
+ gpios |= (1 << 0); // GPIO33 = ODD
+ gpios |= (1 << 1); // GPIO34 = IDE_RST#
+ outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
- gpios &= ~(1 << 13); // ??
- outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ gpios &= ~(1 << 13); // ??
+ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
- gpios &= ~(1 << 24); // Enable LAN Power
- outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ gpios &= ~(1 << 24); // Enable LAN Power
+ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
}
static void ich7_enable_lpc(void)
@@ -61,9 +61,10 @@
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
- | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
- | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+ | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN
+ | COMA_LPC_EN);
// Enable 0x02e0 - 0x2ff
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
// Enable 0x600 - 0x6ff
@@ -93,7 +94,7 @@
{
unsigned int port = dev >> 8;
outb(reg, port);
- outb(val, port+1);
+ outb(val, port + 1);
}
static void early_superio_config(void)
@@ -103,15 +104,15 @@
dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev);
- pnp_write_register(dev, 0x02, 0x0e); // UART power
- pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
- pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
+ pnp_write_register(dev, 0x02, 0x0e); // UART power
+ pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
+ pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
- pnp_write_register(dev, 0x1e, 1); // no 32khz clock
- pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
- pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
- pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
- pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
+ pnp_write_register(dev, 0x1e, 1); // no 32khz clock
+ pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
+ pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
+ pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
+ pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
@@ -144,8 +145,8 @@
static void rcba_config(void)
{
/* Set up virtual channel 0 */
- //RCBA32(0x0014) = 0x80000001;
- //RCBA32(0x001c) = 0x03128010;
+ // RCBA32(0x0014) = 0x80000001;
+ // RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(D31IP) = 0x00042220;
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c
index 5a82044..ca95447 100644
--- a/src/mainboard/getac/p470/smihandler.c
+++ b/src/mainboard/getac/p470/smihandler.c
@@ -115,7 +115,7 @@
case 0xde:
printk(BIOS_DEBUG, "LAN power off\n");
reg32 = inl(DEFAULT_GPIOBASE + GP_LVL);
- reg32 |= (1 << 24); // Disable LAN Power
+ reg32 |= (1 << 24); // Disable LAN Power
outl(reg32, DEFAULT_GPIOBASE + GP_LVL);
break;
case 0xdf:
@@ -151,27 +151,37 @@
u8 reg8;
switch (hotkey) {
- case 0x3b: break; // Fn+F1
- case 0x3c: break; // Fn+F2
- case 0x3d: break; // Fn+F3
- case 0x3e: break; // Fn+F4
- case 0x3f: break; // Fn+F5
- case 0x40: // Fn+F6 (Decrease Display Brightness)
- reg8 = ec_read(0x17);
- reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
- ec_write(0x17, reg8);
- return;
- case 0x41: // Fn+F7 (Increase Display Brightness)
- reg8 = ec_read(0x17);
- reg8 += 8;
- reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
- ec_write(0x17, reg8);
- return;
- case 0x42: break; // Fn+F8
- case 0x43: break; // Fn+F9
- case 0x44: break; // Fn+F10
- case 0x57: break; // Fn+F11
- case 0x58: break; // Fn+F12
+ case 0x3b: // Fn+F1
+ break;
+ case 0x3c: // Fn+F2
+ break;
+ case 0x3d: // Fn+F3
+ break;
+ case 0x3e: // Fn+F4
+ break;
+ case 0x3f: // Fn+F5
+ break;
+ case 0x40: // Fn+F6 (Decrease Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
+ ec_write(0x17, reg8);
+ return;
+ case 0x41: // Fn+F7 (Increase Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 += 8;
+ reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
+ ec_write(0x17, reg8);
+ return;
+ case 0x42: // Fn+F8
+ break;
+ case 0x43: // Fn+F9
+ break;
+ case 0x44: // Fn+F10
+ break;
+ case 0x57: // Fn+F11
+ break;
+ case 0x58: // Fn+F12
+ break;
}
printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31652
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3
Gerrit-Change-Number: 31652
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
4
10
Change in ...coreboot[master]: mb/apple/macbook21: Use common ACPI code
by Evgeny Zinoviev (Code Review) 09 Feb '21
by Evgeny Zinoviev (Code Review) 09 Feb '21
09 Feb '21
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33104
Change subject: mb/apple/macbook21: Use common ACPI code
......................................................................
mb/apple/macbook21: Use common ACPI code
Use common ACPI code from ec/apple to avoid duplication between boards.
Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M src/mainboard/apple/macbook21/acpi/ec.asl
1 file changed, 5 insertions(+), 232 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33104/1
diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl
index 0a8ebca..bd56af5 100644
--- a/src/mainboard/apple/macbook21/acpi/ec.asl
+++ b/src/mainboard/apple/macbook21/acpi/ec.asl
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -11,235 +13,6 @@
* GNU General Public License for more details.
*/
-Device(EC)
-{
- Name(_HID, EISAID("PNP0C09"))
- Name(_UID, 0)
-
- Name(_GPE, 0x17)
- Mutex(ECLK, 0)
-
- OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100)
- Field(ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset(0x01),
- LIDS, 1, /* Lid status */
- HPAC, 1,
- Offset(0x02),
- WKLD, 1, /* Lid wake */
-
- Offset(0x20),
- SPTR, 8,
- SSTS, 8,
- SADR, 8,
- SCMD, 8,
- SBFR, 256,
- }
- Field(ERAM, ByteAcc, Lock, Preserve)
- {
- Offset(0x24),
- SBDW, 16,
- }
-
- Method(SBPC, 0, NotSerialized)
- {
- Store(1000, Local0)
- While(Local0)
- {
- If(LEqual(SPTR, 0x00))
- {
- Return()
- }
-
- Sleep(1)
- Decrement(Local0)
- }
- }
-
- Method(SBRW, 2, NotSerialized)
- {
- Acquire(ECLK, 0xFFFF)
- Store(ShiftLeft(Arg0, 0x01), SADR)
- Store(Arg1, SCMD)
- Store(0x09, SPTR)
- SBPC()
- Store(SBDW, Local0)
- Release(ECLK)
- Return(Local0)
- }
-
- Method(SBRB, 2, NotSerialized)
- {
- Acquire(ECLK, 0xFFFF)
- Store(ShiftLeft(Arg0, 0x01), SADR)
- Store(Arg1, SCMD)
- Store(0x0B, SPTR)
- SBPC()
- Store(SBFR, Local0)
- Release(ECLK)
- Return(Local0)
- }
-
- /* LID status change. */
- Method(_Q20, 0, NotSerialized)
- {
- Notify(LID, 0x80)
- }
-
- /* AC status change. */
- Method(_Q21, 0, NotSerialized)
- {
- Notify(AC, 0x80)
- }
-
- Method(_CRS, 0)
- {
- Name(ECMD, ResourceTemplate()
- {
- IO(Decode16, 0x62, 0x62, 1, 1)
- IO(Decode16, 0x66, 0x66, 1, 1)
- })
- Return(ECMD)
- }
-
- Method(_INI, 0, NotSerialized)
- {
- }
-
- Device(LID)
- {
- Name(_HID, "PNP0C0D")
-
- Method(_LID, 0, NotSerialized)
- {
- return(LIDS)
- }
-
- Method(_PRW, 0, NotSerialized)
- {
- Return (Package() { 0x1d, 0x03 })
- }
-
- Method(_PSW, 1, NotSerialized)
- {
- if (Arg0) {
- Store(1, WKLD)
- } else {
- Store(0, WKLD)
- }
- }
- }
-
- Device(AC)
- {
- Name(_HID, "ACPI0003")
- Name(_UID, 0x00)
- Name(_PCL, Package() { \_SB } )
-
- Method(_PSR, 0, NotSerialized)
- {
- return(HPAC)
- }
-
- Method(_STA, 0, NotSerialized)
- {
- Return(0x0f)
- }
- }
-
- Device(BAT0)
- {
- Name(_HID, EisaId("PNP0C0A"))
- Name(_UID, 0x00)
- Name(_PCL, Package() { \_SB })
-
- Name(BATS, Package()
- {
- 0x00, // 0: PowerUnit: Report in mWh
- 0xFFFFFFFF, // 1: Design cap
- 0xFFFFFFFF, // 2: Last full charge cap
- 0x01, // 3: Battery Technology
- 10800, // 4: Design Voltage(mV)
- 0x00, // 5: Warning design capacity
- 200, // 6: Low design capacity
- 10, // 7: granularity1
- 10, // 8: granularity2
- "", // 9: Model number
- "", // A: Serial number
- "", // B: Battery Type
- "" // C: OEM information
- })
-
- Name(BATI, Package()
- {
- 0, // Battery State
- // Bit 0 - discharge
- // Bit 1 - charge
- // Bit 2 - critical state
- 0, // Battery present Rate
- 0, // Battery remaining capacity
- 0 // Battery present voltage
- })
-
- Method(_BIF, 0, NotSerialized)
- {
- Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01))
- Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02))
- Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04))
- Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09))
- Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B))
- Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C))
-
- Return(BATS)
- }
-
- Method(_STA, 0, NotSerialized)
- {
- If(And(^^SBRW(0x0A, 0x01), 0x01)) {
- Return(0x1f)
- } else {
- Return(0x0f)
- }
- }
-
- Method(_BST, 0, NotSerialized)
- {
- /* Check for battery presence. */
- If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) {
- Return(Package(4) {
- 0,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF
- })
- }
- Store(^^SBRW(0x0B, 0x09), Local1)
- Store(Local1, Index(BATI, 0x03))
- Store(^^SBRW(0x0B, 0x0A), Local0)
- /* Sign-extend Local0. */
- If(And(Local0, 0x8000))
- {
- Not(Local0, Local0)
- And(Increment(Local0), 0xFFFF, Local0)
- }
-
- Multiply(Local0, Local1, Local0)
- Divide(Local0, 1000, , Index(BATI, 1))
- Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2))
- If(HPAC)
- {
- If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) {
- Store(2, Index(BATI, 0))
- } Else {
- Store(0, Index(BATI, 0))
- }
- }
- Else
- {
- Store(0x01, Index(BATI, 0))
- }
-
- Return(BATI)
- }
- }
-}
+#include <ec/apple/acpi/ec.asl>
+#include <ec/apple/acpi/ac_01.asl>
+#include <ec/apple/acpi/lid_01.asl>
--
To view, visit https://review.coreboot.org/c/coreboot/+/33104
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728
Gerrit-Change-Number: 33104
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
4
8
Change in ...coreboot[master]: mb/apple/macbookair4_2: ACPI support for EC
by Evgeny Zinoviev (Code Review) 05 Feb '21
by Evgeny Zinoviev (Code Review) 05 Feb '21
05 Feb '21
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33103
Change subject: mb/apple/macbookair4_2: ACPI support for EC
......................................................................
mb/apple/macbookair4_2: ACPI support for EC
Added ACPI support for battery, AC and LID.
I don't have MacBook Air 4,2 to test, but:
- I tested it on 5,2;
- I found decompiled DSDT for 4,2 and compared registers and bits,
they are the same as on 5,2.
So it should work.
Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M src/mainboard/apple/macbookair4_2/acpi/ec.asl
1 file changed, 5 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/33103/1
diff --git a/src/mainboard/apple/macbookair4_2/acpi/ec.asl b/src/mainboard/apple/macbookair4_2/acpi/ec.asl
index f70cb3d..cd74865 100644
--- a/src/mainboard/apple/macbookair4_2/acpi/ec.asl
+++ b/src/mainboard/apple/macbookair4_2/acpi/ec.asl
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -11,10 +13,6 @@
* GNU General Public License for more details.
*/
-Device(EC)
-{
- Name (_HID, EISAID("PNP0C09"))
- Name (_UID, 0)
- Name (_GPE, 23)
-/* FIXME: EC support */
-}
+#include <ec/apple/acpi/ec.asl>
+#include <ec/apple/acpi/ac_60.asl>
+#include <ec/apple/acpi/lid_60.asl>
--
To view, visit https://review.coreboot.org/c/coreboot/+/33103
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c
Gerrit-Change-Number: 33103
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
5
11
Change in ...coreboot[master]: ec/apple: ACPI code for Apple MacBooks
by Evgeny Zinoviev (Code Review) 05 Feb '21
by Evgeny Zinoviev (Code Review) 05 Feb '21
05 Feb '21
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33102
Change subject: ec/apple: ACPI code for Apple MacBooks
......................................................................
ec/apple: ACPI code for Apple MacBooks
Move ACPI code for Apple MacBooks to a separate directory to avoid it's
duplication in mainboards.
AC and LID implementation files are named by EC register that's used
in them. Older generations (macbook2,1) use 0x01 while newer
generations like 2011-2012 Airs use 0x60. Battery registers seem to be
the same.
Tested on MacBook Air 5,2.
Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
A src/ec/apple/acpi/ac_01.asl
A src/ec/apple/acpi/ac_60.asl
A src/ec/apple/acpi/battery.asl
A src/ec/apple/acpi/ec.asl
A src/ec/apple/acpi/lid_01.asl
A src/ec/apple/acpi/lid_60.asl
6 files changed, 405 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33102/1
diff --git a/src/ec/apple/acpi/ac_01.asl b/src/ec/apple/acpi/ac_01.asl
new file mode 100644
index 0000000..86966ae8
--- /dev/null
+++ b/src/ec/apple/acpi/ac_01.asl
@@ -0,0 +1,42 @@
+
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+ Field(ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x01),
+ 1,
+ HPAC, 1, /* AC status */
+ }
+
+ Device(AC)
+ {
+ Name(_HID, "ACPI0003")
+ Name(_UID, 0x00)
+ Name(_PCL, Package() { \_SB } )
+
+ Method(_PSR, 0, NotSerialized)
+ {
+ return(HPAC)
+ }
+
+ Method(_STA, 0, NotSerialized)
+ {
+ Return(0x0f)
+ }
+ }
+}
diff --git a/src/ec/apple/acpi/ac_60.asl b/src/ec/apple/acpi/ac_60.asl
new file mode 100644
index 0000000..76adea1
--- /dev/null
+++ b/src/ec/apple/acpi/ac_60.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+ Field(ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x60),
+ , 1,
+ HPAC, 1, /* AC status */
+ }
+
+ Device(AC)
+ {
+ Name(_HID, "ACPI0003")
+ Name(_UID, 0x00)
+ Name(_PCL, Package() { \_SB } )
+
+ Method(_PSR, 0, NotSerialized)
+ {
+ return(HPAC)
+ }
+
+ Method(_STA, 0, NotSerialized)
+ {
+ Return(0x0f)
+ }
+ }
+}
diff --git a/src/ec/apple/acpi/battery.asl b/src/ec/apple/acpi/battery.asl
new file mode 100644
index 0000000..f1706be
--- /dev/null
+++ b/src/ec/apple/acpi/battery.asl
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Field(ERAM, ByteAcc, NoLock, Preserve)
+{
+ Offset(0x20),
+ SPTR, 8,
+ SSTS, 8,
+ SADR, 8,
+ SCMD, 8,
+ SBFR, 256,
+}
+
+Field(ERAM, ByteAcc, Lock, Preserve)
+{
+ Offset(0x24),
+ SBDW, 16,
+}
+
+Method(SBPC, 0, NotSerialized)
+{
+ Store(1000, Local0)
+ While(Local0)
+ {
+ If(LEqual(SPTR, 0x00))
+ {
+ Return()
+ }
+
+ Sleep(1)
+ Decrement(Local0)
+ }
+}
+
+Method(SBRW, 2, NotSerialized)
+{
+ Acquire(ECLK, 0xFFFF)
+ Store(ShiftLeft(Arg0, 0x01), SADR)
+ Store(Arg1, SCMD)
+ Store(0x09, SPTR)
+ SBPC()
+ Store(SBDW, Local0)
+ Release(ECLK)
+ Return(Local0)
+}
+
+Method(SBRB, 2, NotSerialized)
+{
+ Acquire(ECLK, 0xFFFF)
+ Store(ShiftLeft(Arg0, 0x01), SADR)
+ Store(Arg1, SCMD)
+ Store(0x0B, SPTR)
+ SBPC()
+ Store(SBFR, Local0)
+ Release(ECLK)
+ Return(Local0)
+}
+
+Device(BAT0)
+{
+ Name(_HID, EisaId("PNP0C0A"))
+ Name(_UID, 0x00)
+ Name(_PCL, Package() { \_SB })
+
+ Name(BATS, Package()
+ {
+ 0x00, // 0: PowerUnit: Report in mWh
+ 0xFFFFFFFF, // 1: Design cap
+ 0xFFFFFFFF, // 2: Last full charge cap
+ 0x01, // 3: Battery Technology
+ 10800, // 4: Design Voltage(mV)
+ 0x00, // 5: Warning design capacity
+ 200, // 6: Low design capacity
+ 10, // 7: granularity1
+ 10, // 8: granularity2
+ "", // 9: Model number
+ "", // A: Serial number
+ "", // B: Battery Type
+ "" // C: OEM information
+ })
+
+ Name(BATI, Package()
+ {
+ 0, // Battery State
+ // Bit 0 - discharge
+ // Bit 1 - charge
+ // Bit 2 - critical state
+ 0, // Battery present Rate
+ 0, // Battery remaining capacity
+ 0 // Battery present voltage
+ })
+
+ Method(_BIF, 0, NotSerialized)
+ {
+ Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01))
+ Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02))
+ Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04))
+ Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09))
+ Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B))
+ Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C))
+
+ Return(BATS)
+ }
+
+ Method(_STA, 0, NotSerialized)
+ {
+ If(And(^^SBRW(0x0A, 0x01), 0x01)) {
+ Return(0x1f)
+ } else {
+ Return(0x0f)
+ }
+ }
+
+ Method(_BST, 0, NotSerialized)
+ {
+ /* Check for battery presence. */
+ If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) {
+ Return(Package(4) {
+ 0,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF
+ })
+ }
+ Store(^^SBRW(0x0B, 0x09), Local1)
+ Store(Local1, Index(BATI, 0x03))
+ Store(^^SBRW(0x0B, 0x0A), Local0)
+ /* Sign-extend Local0. */
+ If(And(Local0, 0x8000))
+ {
+ Not(Local0, Local0)
+ And(Increment(Local0), 0xFFFF, Local0)
+ }
+
+ Multiply(Local0, Local1, Local0)
+ Divide(Local0, 1000, , Index(BATI, 1))
+ Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2))
+ If(HPAC)
+ {
+ If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) {
+ Store(2, Index(BATI, 0))
+ } Else {
+ Store(0, Index(BATI, 0))
+ }
+ }
+ Else
+ {
+ Store(0x01, Index(BATI, 0))
+ }
+
+ Return(BATI)
+ }
+}
diff --git a/src/ec/apple/acpi/ec.asl b/src/ec/apple/acpi/ec.asl
new file mode 100644
index 0000000..982011c
--- /dev/null
+++ b/src/ec/apple/acpi/ec.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC)
+{
+ Name(_HID, EISAID("PNP0C09"))
+ Name(_UID, 0)
+
+ Name(_GPE, 0x17)
+ Mutex(ECLK, 0)
+
+ OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100)
+
+ /* LID status change. */
+ Method(_Q20, 0, NotSerialized)
+ {
+ Notify(LID, 0x80)
+ }
+
+ /* AC status change. */
+ Method(_Q21, 0, NotSerialized)
+ {
+ Notify(AC, 0x80)
+ }
+
+ Method(_CRS, 0)
+ {
+ Name(ECMD, ResourceTemplate()
+ {
+ IO(Decode16, 0x62, 0x62, 1, 1)
+ IO(Decode16, 0x66, 0x66, 1, 1)
+ })
+ Return(ECMD)
+ }
+
+ Method(_PRW, 0, NotSerialized)
+ {
+ return (Package () { 0x23, 0x04 })
+ }
+
+ Method(_INI, 0, NotSerialized)
+ {
+ }
+
+#include "battery.asl"
+}
diff --git a/src/ec/apple/acpi/lid_01.asl b/src/ec/apple/acpi/lid_01.asl
new file mode 100644
index 0000000..88ad045
--- /dev/null
+++ b/src/ec/apple/acpi/lid_01.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+ Field(ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x01),
+ LIDS, 1, /* Lid status */
+
+ Offset(0x02),
+ WKLD, 1, /* Lid wake */
+ }
+
+ Device(LID)
+ {
+ Name(_HID, "PNP0C0D")
+
+ Method(_LID, 0, NotSerialized)
+ {
+ return(LIDS)
+ }
+
+ Method(_PRW, 0, NotSerialized)
+ {
+ Return (Package() { 0x1d, 0x03 })
+ }
+
+ Method(_PSW, 1, NotSerialized)
+ {
+ if (Arg0) {
+ Store(1, WKLD)
+ } else {
+ Store(0, WKLD)
+ }
+ }
+ }
+}
diff --git a/src/ec/apple/acpi/lid_60.asl b/src/ec/apple/acpi/lid_60.asl
new file mode 100644
index 0000000..e0836b6
--- /dev/null
+++ b/src/ec/apple/acpi/lid_60.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+ Field(ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x60),
+ LIDS, 1, /* Lid status */
+
+ Offset(0x68),
+ WKLD, 1, /* Lid wake */
+ }
+
+ Device(LID)
+ {
+ Name(_HID, "PNP0C0D")
+
+ Method(_LID, 0, NotSerialized)
+ {
+ return(LIDS)
+ }
+
+ Method(_PRW, 0, NotSerialized)
+ {
+ Return (Package() { 0x23, 0x04 })
+ }
+
+ Method(_PSW, 1, NotSerialized)
+ {
+ if (Arg0) {
+ Store(1, WKLD)
+ } else {
+ Store(0, WKLD)
+ }
+ }
+ }
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/33102
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069
Gerrit-Change-Number: 33102
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
8
45
Change in ...coreboot[master]: superio/ite: Add and use it8528e
by Patrick Rudolph (Code Review) 26 Dec '20
by Patrick Rudolph (Code Review) 26 Dec '20
26 Dec '20
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30957
Change subject: superio/ite: Add and use it8528e
......................................................................
superio/ite: Add and use it8528e
* Add SuperIO ITE8528E
* Use ITE8528E to configure serial on wedge100s
TODO: Add support for accessing EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/ocp/wedge100s/Kconfig
M src/mainboard/ocp/wedge100s/devicetree.cb
M src/superio/ite/Makefile.inc
A src/superio/ite/it8528e/Kconfig
A src/superio/ite/it8528e/Makefile.inc
A src/superio/ite/it8528e/chip.h
A src/superio/ite/it8528e/it8528e.h
A src/superio/ite/it8528e/superio.c
8 files changed, 226 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30957/1
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index ce9c097..6224340 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -16,6 +16,7 @@
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select DRIVERS_UART_8250IO
+ select SUPERIO_ITE_IT8528E
config VBOOT
select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
index 3d66d0d..fc6dccc 100644
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ b/src/mainboard/ocp/wedge100s/devicetree.cb
@@ -11,6 +11,58 @@
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
+ chip superio/ite/it8528e
+ # COM1, routed to COM-e header
+ device pnp 6e.1 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ # COM2, routed to COM-e header
+ device pnp 6e.2 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 6e.4 off end
+ device pnp 6e.5 off end
+ device pnp 6e.6 off end
+ device pnp 6e.a off end
+ device pnp 6e.f off end
+ device pnp 6e.10 off
+ io 0x60 = 0x70
+ io 0x62 = 0x72
+ irq 0x70 = 8
+ end
+ device pnp 6e.11 off
+ io 0x60 = 0x620
+ io 0x62 = 0x660
+ irq 0x70 = 1
+ end
+ device pnp 6e.12 off
+ io 0x60 = 0x680
+ io 0x62 = 0x6c0
+ irq 0x70 = 1
+ end
+ device pnp 6e.13 off
+ io 0x60 = 0x300
+ irq 0x70 = 2
+ end
+ device pnp 6e.14 off end
+ device pnp 6e.17 off
+ io 0x60 = 0x6a0
+ io 0x62 = 0x6e0
+ irq 0x70 = 1
+ end
+ device pnp 6e.18 off
+ io 0x60 = 0x740
+ io 0x62 = 0x780
+ irq 0x70 = 1
+ end
+ device pnp 6e.19 off
+ io 0x60 = 0x7a0
+ io 0x62 = 0x7c0
+ irq 0x70 = 1
+ end
+ end #superio/ite/it8528e
end # LPC Bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus Controller
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index e73fd71..551abe9 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -20,6 +20,7 @@
## include generic ite environment controller driver
ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c
+subdirs-y += it8528e
subdirs-y += it8623e
subdirs-y += it8671f
subdirs-y += it8712f
diff --git a/src/superio/ite/it8528e/Kconfig b/src/superio/ite/it8528e/Kconfig
new file mode 100644
index 0000000..3815c28
--- /dev/null
+++ b/src/superio/ite/it8528e/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8528E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8528e/Makefile.inc b/src/superio/ite/it8528e/Makefile.inc
new file mode 100644
index 0000000..def04e5
--- /dev/null
+++ b/src/superio/ite/it8528e/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8528E) += superio.c
diff --git a/src/superio/ite/it8528e/chip.h b/src/superio/ite/it8528e/chip.h
new file mode 100644
index 0000000..ef7e14f
--- /dev/null
+++ b/src/superio/ite/it8528e/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8528E_CHIP_H
+#define SUPERIO_ITE_IT8528E_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8528e_config {
+ // FIXME: Add support for EC
+};
+
+#endif /* SUPERIO_ITE_IT8528E_CHIP_H */
diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h
new file mode 100644
index 0000000..7b19349
--- /dev/null
+++ b/src/superio/ite/it8528e/it8528e.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8528E_H
+#define SUPERIO_ITE_IT8528E_H
+
+#define IT8528E_SP1 0x01 /* Com1 */
+#define IT8528E_SP2 0x02 /* Com2 */
+#define IT8528E_SWUC 0x04 /* System Wake-Up */
+#define IT8528E_KBCM 0x05 /* PS/2 mouse */
+#define IT8528E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8528E_IR 0x0a /* Consumer IR */
+#define IT8528E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8528E_RTCT 0x10 /* RTC-like Timer */
+#define IT8528E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8528E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8528E_SSPI 0x13 /* Serial Periphial Interface */
+#define IT8528E_PECI 0x14 /* Platform EC Interface */
+#define IT8528E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8528E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8528E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8528E_H */
diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c
new file mode 100644
index 0000000..ae2a8e9
--- /dev/null
+++ b/src/superio/ite/it8528e/superio.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de>
+ * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "chip.h"
+#include "it8528e.h"
+
+static void it8528e_init(struct device *dev)
+{
+ // FIXME: Init EC
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8528e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, IT8528E_KBCM, PNP_IRQ0, },
+ /* Documentation: Programm io0 = 0x60 and io1 = 0x64 */
+ { NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ /* Documentation: Programm io0 = 0x70 and io1 = 0x272 */
+ { NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ /* Documentation: Programm io0 = 0x62 and io1 = 0x66 */
+ { NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 , 0x07fc,
+ 0x07fc, 0xfff0 },
+ /* Documentation is unclear if PMC3-5 have LPC I/O decoding support */
+ { NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8528E_PECI, PNP_IO0 , 0xfff8 },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8528e_ops = {
+ CHIP_NAME("ITE IT8528E Super I/O")
+ .enable_dev = enable_dev,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/30957
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Gerrit-Change-Number: 30957
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
6
22
Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation
by Balázs Vinarz (Code Review) 06 Dec '20
by Balázs Vinarz (Code Review) 06 Dec '20
06 Dec '20
Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1
diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md
new file mode 100644
index 0000000..5f50c5a
--- /dev/null
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -0,0 +1,131 @@
+# ASUS A88XM-E
+
+This page describes how to run coreboot on the [ASUS A88XM-E].
+
+## Technology
+
+Both "Trinity" and "Richland" FM2 desktop processing units are working,
+the CPU architecture in these CPUs/APUs are [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+Kaveri is non-working at the moment (FM2+),
+the CPU architecture in these CPUs/APUs are [Steamroller],
+and their GPU is [Sea Islands] (GCN2-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| A88XM-E | |
++------------------+--------------------------------------------------+
+| DDR voltage IC | Nuvoton 3101S |
++------------------+--------------------------------------------------+
+| Network | Realtek RTL8111G - Not working |
++------------------+--------------------------------------------------+
+| Northbridge | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge | Bolton-D4 |
++------------------+--------------------------------------------------+
+| Sound IC | Realtek ALC887 |
++------------------+--------------------------------------------------+
+| Super I/O | ITE 8603E |
++------------------+--------------------------------------------------+
+| VRM controller | DIGI VRM ASP1206 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | [GD25Q64] |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | yes |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom], if the
+AmdSpiRomProtect modules have been deleted in the factory image previously.
+
+## Integrated graphics
+
+### Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+ # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+This version is usable for all the GPUs.
+1002,9901 Trinity (Radeon HD 7660D)
+1002,9904 Trinity (Radeon HD 7560D)
+1002,990c Richland (Radeon HD 8670D)
+1002,990e Richland (Radeon HD 8570D)
+1002,9991 Trinity (Radeon HD 7540D)
+1002,9993 Trinity (Radeon HD 7480D)
+1002,9996 Richland (Radeon HD 8470D)
+1002,9998 Richland (Radeon HD 8370D)
+1002,999d Richland (Radeon HD 8550D)
+1002,130f Kaveri (Radeon R7)
+
+## Known issues
+
+- AHCI hot-plug
+- Integrated ethernet
+- S3 resume
+- XHCI
+
+### XHCI ports can broke after using any of the blobs, restarting the
+board with factory image makes it work again as fallback.
+Tested even with/without the Bolton and Hudson blobs.
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- one ATOMBIOS module for all the integrated GPUs
+- manage to work with Kaveri/Godavary (missing PSP firmware?)
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Hardware monitoring
+- Integrated graphics
+- Keyboard
+- KVM virtualization
+- Onboard audio
+- PCI
+- PCIe
+- PS/2 keyboard (during payload, bootloader)
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
+
+## Extra resources
+
+- [Board manual]
+
+[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
+[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)
+[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000..56c1753
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+ };
+#else
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+};
+#endif
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+ /* Fan Control */
+ FchParams_env->Imc.ImcEnable = FALSE;
+ FchParams_env->Hwm.HwMonitorEnable = FALSE;
+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000..70be2f1
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,117 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/a88xm-e
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A88XM-E" if BOARD_ASUS_A88XM_E
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,990e"
+
+config CONFIG_DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config CONFIG_HUDSON_XHCI_ENABLE
+ bool
+ default n
+
+config HUDSON_LEGACY_FREE
+ bool
+ default n
+
+config POST_IO
+ bool
+ default n
+
+config CONFIG_POST_DEVICE_PCI_PCIE
+ bool
+ default y
+
+config DEVICETREE
+ string
+ default "devicetree_a88xm-e.cb"
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000..492d610
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+ bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000..4c4c5bf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
+ },
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ // DP0 to HDMI0/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ // DP1 to FCH
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // DP2 to HDMI1/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000..b45f5a8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000..69de2d8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000..297db37
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000..8398c88
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000..08b7de4
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000..f94fde0
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000..bc090ff
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas… SPI]
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000..c324532
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+
+/* Select the CPU family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the CPU socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if IS_ENABLED(CONFIG_GFXUMA)
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
+#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+//#define FCH_NO_XHCI_SUPPORT FALSE
+GPIO_CONTROL a88xm_e_gpio[] = {
+// {183, Function1, PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000..e1dbd9a
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
new file mode 100644
index 0000000..e2b0eea
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
@@ -0,0 +1,143 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics
+ device pci 1.1 on end # Internal Audio (iGPU)
+ device pci 2.0 on end # PCIE x4/x16 yellow (?)
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE x4/x16 yellow (?)
+ device pci 5.0 off end # unused
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "0x80" # never
+ register "FAN1.smart.tmp_start" = "20"
+ register "FAN1.smart.tmp_full" = "70"
+ register "FAN1.smart.tmp_delta" = "0"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "32"
+
+ # Enable tacho reading for chassis fan.
+ register "FAN2.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #
+ device pci 14.3 off end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 off end # unused
+ device pci 15.2 on end # PCI bridge
+ device pci 15.3 off end # unused
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000..45a2606
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ /**
+ * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+ * be referenced anywhere and could possibly be removed.
+ */
+ Device(SBR0) { /* PCIe 1x SB */
+ Name(_ADR, 0x00150000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(ABR0) } /* APIC mode */
+ Return (PBR0) /* PIC mode */
+ }
+ }
+
+ Device(SBR1) { /* Onboard network */
+ Name(_ADR, 0x00150001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT, 0) {
+ If(PMOD){ Return(ABR1) } /* APIC mode */
+ Return (PBR1) /* PIC mode */
+ }
+ }
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000..88d2160
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000..2a0e618
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(struct device *dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(LS_CFG_MSR);
+ msr.lo &= ~(1 << 28);
+ wrmsr(LS_CFG_MSR, msr);
+
+ msr = rdmsr(DC_CFG_MSR);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(DC_CFG_MSR, msr);
+
+ msr = rdmsr(BU_CFG_MSR);
+ msr.lo &= ~(1 << 23);
+ wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000..d97663d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000..0a85c27
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_e(void)
+{
+ pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ u8 byte;
+ pci_devfn_t dev;
+
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ superio_init_e();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30987
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 1
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-MessageType: newchange
9
252