18 Jan
2019
18 Jan
'19
6:10 p.m.
Balázs Vinarz has uploaded this change for review. (
https://review.coreboot.org/c/coreboot/+/30987
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1
diff --git a/Documentation/mainboard/asus/a88xm-e.md
b/Documentation/mainboard/asus/a88xm-e.md
new file mode 100644
index 0000000..5f50c5a
--- /dev/null
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -0,0 +1,131 @@
+# ASUS A88XM-E
+
+This page describes how to run coreboot on the [ASUS A88XM-E].
+
+## Technology
+
+Both "Trinity" and "Richland" FM2 desktop processing units are
working,
+the CPU architecture in these CPUs/APUs are [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+Kaveri is non-working at the moment (FM2+),
+the CPU architecture in these CPUs/APUs are [Steamroller],
+and their GPU is [Sea Islands] (GCN2-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| A88XM-E | |
++------------------+--------------------------------------------------+
+| DDR voltage IC | Nuvoton 3101S |
++------------------+--------------------------------------------------+
+| Network | Realtek RTL8111G - Not working |
++------------------+--------------------------------------------------+
+| Northbridge | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge | Bolton-D4 |
++------------------+--------------------------------------------------+
+| Sound IC | Realtek ALC887 |
++------------------+--------------------------------------------------+
+| Super I/O | ITE 8603E |
++------------------+--------------------------------------------------+
+| VRM controller | DIGI VRM ASP1206 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | [GD25Q64] |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | yes |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom], if the
+AmdSpiRomProtect modules have been deleted in the factory image previously.
+
+## Integrated graphics
+
+### Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+ # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+This version is usable for all the GPUs.
+1002,9901 Trinity (Radeon HD 7660D)
+1002,9904 Trinity (Radeon HD 7560D)
+1002,990c Richland (Radeon HD 8670D)
+1002,990e Richland (Radeon HD 8570D)
+1002,9991 Trinity (Radeon HD 7540D)
+1002,9993 Trinity (Radeon HD 7480D)
+1002,9996 Richland (Radeon HD 8470D)
+1002,9998 Richland (Radeon HD 8370D)
+1002,999d Richland (Radeon HD 8550D)
+1002,130f Kaveri (Radeon R7)
+
+## Known issues
+
+- AHCI hot-plug
+- Integrated ethernet
+- S3 resume
+- XHCI
+
+### XHCI ports can broke after using any of the blobs, restarting the
+board with factory image makes it work again as fallback.
+Tested even with/without the Bolton and Hudson blobs.
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- one ATOMBIOS module for all the integrated GPUs
+- manage to work with Kaveri/Godavary (missing PSP firmware?)
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Hardware monitoring
+- Integrated graphics
+- Keyboard
+- KVM virtualization
+- Onboard audio
+- PCI
+- PCIe
+- PS/2 keyboard (during payload, bootloader)
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
+
+## Extra resources
+
+- [Board manual]
+
+[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
+[Board manual]:
https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
+[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)
+[TeraScale 3]:
https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c
b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000..56c1753
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+ };
+#else
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+};
+#endif
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST
*)(&CodecTableList[0]);
+
+ /* Fan Control */
+ FchParams_env->Imc.ImcEnable = FALSE;
+ FchParams_env->Hwm.HwMonitorEnable = FALSE;
+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling
*/
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000..70be2f1
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,117 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/a88xm-e
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A88XM-E" if BOARD_ASUS_A88XM_E
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,990e"
+
+config CONFIG_DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config CONFIG_HUDSON_XHCI_ENABLE
+ bool
+ default n
+
+config HUDSON_LEGACY_FREE
+ bool
+ default n
+
+config POST_IO
+ bool
+ default n
+
+config CONFIG_POST_DEVICE_PCI_PCIE
+ bool
+ default y
+
+config DEVICETREE
+ string
+ default "devicetree_a88xm-e.cb"
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name
b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000..492d610
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+ bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc
b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c
b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000..4c4c5bf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
+ },
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ // DP0 to HDMI0/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ // DP1 to FCH
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // DP2 to HDMI1/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+
*----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to
AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If
PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it
will
+ * use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h
b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000..b45f5a8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000..69de2d8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID,
ACPI_TABLE_CREATOR, 0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl
b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000..297db37
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000..8398c88
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space,
1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl
b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl
b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl
b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl
b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000..08b7de4
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl
b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl
b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c
b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000..f94fde0
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt
b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000..bc090ff
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol:
[http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas…
SPI]
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c
b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000..c324532
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+
+/* Select the CPU family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the CPU socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default
value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L,
Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the
VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if IS_ENABLED(CONFIG_GFXUMA)
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) =
256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A',
'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0',
'.', '0', '.', '1', ' ', ' ', ' ',
' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
+#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+//#define FCH_NO_XHCI_SUPPORT FALSE
+GPIO_CONTROL a88xm_e_gpio[] = {
+// {183, Function1, PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0])
+
+// The following definitions specify the default values for various parameters in which
there are
+// no clearly defined defaults to be used in the common file. The values below are based
on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout
b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000..e1dbd9a
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
new file mode 100644
index 0000000..e2b0eea
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
@@ -0,0 +1,143 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics
+ device pci 1.1 on end # Internal Audio (iGPU)
+ device pci 2.0 on end # PCIE x4/x16 yellow (?)
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE x4/x16 yellow (?)
+ device pci 5.0 off end # unused
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "0x80" # never
+ register "FAN1.smart.tmp_start" = "20"
+ register "FAN1.smart.tmp_full" = "70"
+ register "FAN1.smart.tmp_delta" = "0"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "32"
+
+ # Enable tacho reading for chassis fan.
+ register "FAN2.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #
+ device pci 14.3 off end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 off end # unused
+ device pci 15.2 on end # PCI bridge
+ device pci 15.3 off end # unused
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD
addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD
addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000..45a2606
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed
*/
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ /**
+ * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+ * be referenced anywhere and could possibly be removed.
+ */
+ Device(SBR0) { /* PCIe 1x SB */
+ Name(_ADR, 0x00150000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(ABR0) } /* APIC mode */
+ Return (PBR0) /* PIC mode */
+ }
+ }
+
+ Device(SBR1) { /* Onboard network */
+ Name(_ADR, 0x00150001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT, 0) {
+ If(PMOD){ Return(ABR1) } /* APIC mode */
+ Return (PBR1) /* PIC mode */
+ }
+ }
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c
b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000..88d2160
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c
b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000..2a0e618
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(struct device *dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER "
Enable.\n");
+
+ msr = rdmsr(LS_CFG_MSR);
+ msr.lo &= ~(1 << 28);
+ wrmsr(LS_CFG_MSR, msr);
+
+ msr = rdmsr(DC_CFG_MSR);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(DC_CFG_MSR, msr);
+
+ msr = rdmsr(BU_CFG_MSR);
+ msr.lo &= ~(1 << 23);
+ wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000..d97663d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
(intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus),
(((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c
b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000..0a85c27
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_e(void)
+{
+ pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ u8 byte;
+ pci_devfn_t dev;
+
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ superio_init_e();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 1
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-MessageType: newchange
18 Jan
18 Jan
6:10 p.m.
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Patch Set 1:
(235 comments)
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
File src/mainboard/asus/a88xm-e/BiosCallOuts.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 24: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 79: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 80: {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
"(foo*)" should be "(foo *)"
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 81: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
"(foo*)" should be "(foo *)"
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 84: void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK
*FchParams_reset)
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 92: FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST
*)(&CodecTableList[0]);
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/BiosCall…
PS1, Line 97: FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI
Auto Polling */
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 78: /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4)
*/
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 117: PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 147:
/*----------------------------------------------------------------------------------------
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 149:
*----------------------------------------------------------------------------------------
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 153: * Platform Specific Overriding Table allows IBV/OEM to pass in platform
information to AGESA
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 154: * (e.g. MemClk routing, the number of DIMM slots per channel,...). If
PlatformSpecificTable
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 155: * is populated, AGESA will base its settings on the data from the table.
Otherwise, it will
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 161: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 162: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 164: PSO_END
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/OemCusto…
PS1, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/acpi_tab…
File src/mainboard/asus/a88xm-e/acpi_tables.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/acpi_tab…
PS1, Line 29: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
CONFIG_MAX_CPUS,
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/acpi_tab…
PS1, Line 42: current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
0xff, 5, 1);
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 142: #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread
Spectrum default value 0.36%
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 158: //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 159: //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable
NBPSI_L, Non-zero - enable NBPSI_L
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 160: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 161: //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 162: //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 163: //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
please, no space before tabs
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 174: #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
please, no space before tabs
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 230: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 231: { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 232: { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 233: { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 234: { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 235: { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 236: { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 237: { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 238: { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 239: { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 240: { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 241: { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 242: { CPU_LIST_TERMINAL }
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 245: #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 247: // This is the delivery package title,
"BrazosPI"
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 248: // This string MUST be exactly 8 characters long
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 251: // This is the release version number of the AGESA
component
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 252: // This string MUST be exactly 12 characters long
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 253: #define AGESA_VERSION_STRING {'V', '0', '.',
'0', '.', '0', '.', '1', ' ', ' ',
' ', ' '}
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 267: #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR
frequency
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 270: #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 271: #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 274: #define TIMING_MODE_AUTO 0 ///< Use best rate possible
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 275: #define TIMING_MODE_LIMITED 1 ///< Set user top limit
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 280: #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 334: // The following definitions specify the default values for various
parameters in which there are
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/buildOpt…
PS1, Line 335: // no clearly defined defaults to be used in the common file. The values
below are based on product
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/irq_tabl…
File src/mainboard/asus/a88xm-e/irq_tables.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/irq_tabl…
PS1, Line 94: if (sum != pirq->checksum) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/irq_tabl…
PS1, Line 98: printk(BIOS_INFO, "write_pirq_routing_table done.\n");
Prefer using '"%s...", __func__' to using
'write_pirq_routing_table', this function's name, in a string
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mainboar…
File src/mainboard/asus/a88xm-e/mainboard.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mainboar…
PS1, Line 28: printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER
" Enable.\n");
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.c
File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
line over 80 characters
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PS1, Line 39: 0x10,0x11,0x12,0x13
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PS1, Line 42: static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 91: for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
space prohibited before that '++' (ctx:WxB)
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 97: for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
space prohibited before that '++' (ctx:WxB)
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PS1, Line 102: /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID
PIN# */
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 103: #define IO_LOCAL_INT(type, intr, apicid, pin) \
macros should not use a trailing semicolon
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin));
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/mptable.…
PS1, Line 167: /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID
PIN# */
line over 80 characters
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/romstage…
File src/mainboard/asus/a88xm-e/romstage.c:
https://review.coreboot.org/#/c/30987/1/src/mainboard/asus/a88xm-e/romstage…
PS1, Line 31: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 +
(x))
Macros with complex values should be enclosed in parentheses
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 1
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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6:25 p.m.
New subject: Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation, the port bas...
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#2).
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation, the port based on F2A85-M.
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/2
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Gerrit-Change-Number: 30987
Gerrit-PatchSet: 2
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Balázs Vinarz <vinibali1(a)gmail.com>
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7:22 p.m.
New subject: Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation, the port bas...
Angel Pons has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 2:
(9 comments)
https://review.coreboot.org/#/c/30987/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/30987/2//COMMIT_MSG@7
PS2, Line 7: Adding Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
Please use imperative mode for the verbs in the commit message: "Add Asus A88XM-E
FM2+..."
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
File Documentation/mainboard/asus/a88xm-e.md:
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 59:
trailing space
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 83: - Integrated ethernet
Maybe it is missing a MAC address? coreboot has a driver for that.
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 87:
trailing space
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 88: board with factory image makes it work again as fallback.
This is probably because the xHCI blob is loaded by the vendor BIOS onto the controllers,
which coreboot should do. Does booting the vendor BIOS, flashing coreboot internally,
powering off the board completely and then booting coreboot result in usable xHCI ports?
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/Kconfig
File src/mainboard/asus/a88xm-e/Kconfig:
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/Kconfig@…
PS2, Line 29: SUPERIO_ITE_IT8728F
This works with the ITE IT8603?
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/Kconfig@…
PS2, Line 113: config DEVICETREE
: string
: default "devicetree_a88xm-e.cb"
Rename the devicetree to "devicetree.cb" and drop this.
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/board_in…
File src/mainboard/asus/a88xm-e/board_info.txt:
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/board_in…
PS2, Line 4:
[http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas…
SPI]
There is no need to link anything here. Just "SPI" is enough.
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/romstage…
File src/mainboard/asus/a88xm-e/romstage.c:
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/romstage…
PS2, Line 49: pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
: pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
These can be macros
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9:12 p.m.
New subject: Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation, the port bas...
Kyösti Mälkki has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
File Documentation/mainboard/asus/a88xm-e.md:
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 13: and their GPU is [Sea Islands] (GCN2-based).
We have binaryPI blob for Kaveri, but it is for FP3 socket only. If you get innovative you
can do a search on KaveriPI and build your own blob. That could support all TN/RL/KV on
FM2+ (FM2r2).
You will not get such blobs or headerfiles merged (incompatible license, leaked source) to
coreboot repos. What you publish on your personal repos elsewhere is none of our
business.
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 88: board with factory image makes it work again as fallback.
This is probably because the xHCI blob is loaded by
the vendor BIOS onto the controllers, which core […]
I think xhci firmware loader in
fam15tn vendorcode was buggy. Not sure if there are any visible symptomps with
"Hudson A85". Looking at firmware blobs, architecture/layout appears to be the
same for bolton.
According to blobs/southbridge/amd/bolton/XHCI_Release_Notes.txt file, first version
compatible with Bolton would be 1.1.0.0049.
I would assume bolton/xhci FW is 1.1.0.0059, the last relnotes mentions.
According to logs, hudson/xhci FW would be 1.1.0.0048.
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11:43 p.m.
New subject: Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation, the port bas...
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 2:
Patch Set 2:
(9 comments)
Documentation/mainboard/asus/a88xm-e.md:
Line 83:
Maybe it is missing a MAC address? coreboot has a driver for that.
It's not. No interface/device found on OS level, neighter during Coreboot init. But
the device tree has been modified according to the factory bios.
Line 88:
This is probably because the xHCI blob is loaded by the vendor BIOS onto the controllers,
>which coreboot should do. Does booting the vendor BIOS, flashing coreboot internally,
>powering off the board completely and then booting coreboot result in usable xHCI
ports?
Belive me, I tried literally everything. Somehow I managed it to work once on F2A85-M, but
never again.
src/mainboard/asus/a88xm-e/Kconfig:
Line 29:
This works with the ITE IT8603?
Yes, it is. Probably really same chip, just
different package pin count.
https://lm-sensors.lm-sensors.narkive.com/VnxI9zvt/it8620e-it8623e-vs-it860…
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19 Jan
19 Jan
4:49 a.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#3).
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Add Asus A88XM-E FM2+ motherboard with documentation, the port based on F2A85-M.
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/3
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4:50 a.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 3:
(235 comments)
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
File src/mainboard/asus/a88xm-e/BiosCallOuts.c:
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 24: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 79: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 80: {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
"(foo*)" should be "(foo *)"
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 81: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
"(foo*)" should be "(foo *)"
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 84: void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK
*FchParams_reset)
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 92: FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST
*)(&CodecTableList[0]);
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/BiosCall…
PS3, Line 97: FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI
Auto Polling */
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 78: /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4)
*/
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 117: PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 147:
/*----------------------------------------------------------------------------------------
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 149:
*----------------------------------------------------------------------------------------
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 153: * Platform Specific Overriding Table allows IBV/OEM to pass in platform
information to AGESA
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 154: * (e.g. MemClk routing, the number of DIMM slots per channel,...). If
PlatformSpecificTable
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 155: * is populated, AGESA will base its settings on the data from the table.
Otherwise, it will
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 161: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 162: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 164: PSO_END
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/OemCusto…
PS3, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/acpi_tab…
File src/mainboard/asus/a88xm-e/acpi_tables.c:
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/acpi_tab…
PS3, Line 29: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
CONFIG_MAX_CPUS,
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/acpi_tab…
PS3, Line 42: current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
0xff, 5, 1);
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 142: #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread
Spectrum default value 0.36%
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 158: //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 159: //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable
NBPSI_L, Non-zero - enable NBPSI_L
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 160: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 161: //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 162: //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 163: //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
please, no space before tabs
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 174: #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
please, no space before tabs
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 230: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 231: { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 232: { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 233: { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 234: { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 235: { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 236: { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 237: { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 238: { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 239: { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 240: { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 241: { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 242: { CPU_LIST_TERMINAL }
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 245: #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 247: // This is the delivery package title,
"BrazosPI"
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 248: // This string MUST be exactly 8 characters long
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 251: // This is the release version number of the AGESA
component
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 252: // This string MUST be exactly 12 characters long
code indent should use tabs where possible
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 253: #define AGESA_VERSION_STRING {'V', '0', '.',
'0', '.', '0', '.', '1', ' ', ' ',
' ', ' '}
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 267: #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR
frequency
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 270: #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 271: #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 274: #define TIMING_MODE_AUTO 0 ///< Use best rate possible
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 275: #define TIMING_MODE_LIMITED 1 ///< Set user top limit
line over 80 characters
https://review.coreboot.org/#/c/30987/3/src/mainboard/asus/a88xm-e/buildOpt…
PS3, Line 280: #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
line over 80 characters
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PS3, Line 334: // The following definitions specify the default values for various
parameters in which there are
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PS3, Line 335: // no clearly defined defaults to be used in the common file. The values
below are based on product
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File src/mainboard/asus/a88xm-e/irq_tables.c:
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PS3, Line 94: if (sum != pirq->checksum) {
braces {} are not necessary for single statement blocks
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PS3, Line 98: printk(BIOS_INFO, "write_pirq_routing_table done.\n");
Prefer using '"%s...", __func__' to using
'write_pirq_routing_table', this function's name, in a string
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File src/mainboard/asus/a88xm-e/mainboard.c:
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PS3, Line 28: printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER
" Enable.\n");
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File src/mainboard/asus/a88xm-e/mptable.c:
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PS3, Line 26:
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PS3, Line 26:
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PS3, Line 26:
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PS3, Line 26:
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PS3, Line 26:
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PS3, Line 26:
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PS3, Line 26:
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PS3, Line 42: static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
Prefer 'unsigned int' to bare use of 'unsigned'
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PS3, Line 91: for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
space prohibited before that '++' (ctx:WxB)
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PS3, Line 97: for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
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PS3, Line 102: /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID
PIN# */
line over 80 characters
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PS3, Line 103: #define IO_LOCAL_INT(type, intr, apicid, pin) \
macros should not use a trailing semicolon
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PS3, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin));
line over 80 characters
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PS3, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 80 characters
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PS3, Line 167: /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID
PIN# */
line over 80 characters
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File src/mainboard/asus/a88xm-e/romstage.c:
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PS3, Line 31: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 +
(x))
Macros with complex values should be enclosed in parentheses
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22 Jan
22 Jan
4:59 a.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
mikeb mikeb has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 3:
Hi there Balázs! Please could you tell more about your hardware setup, especially what CPU
you are using with your A88XM-E board? Thank you in advance
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7:35 p.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
Paul Menzel has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 3:
(2 comments)
Could this be made a variant?
https://review.coreboot.org/#/c/30987/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/30987/3//COMMIT_MSG@7
PS3, Line 7: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
Please use a prefix and a shorter commit message summary. Maybe:
mb/asus: Add Asus A88XM-E FM2+
The other information should go into the commit message body:
The port is based on the Asus F2A85-M. The differences
are …
Also add the documentation.
Please also add, how you tested this.
Successfully booted coreboot with SeaBIOS payload
1.12… and then Linux 4.… from the hard drive?
The CPU is AMD … and the RAM ….
https://review.coreboot.org/#/c/30987/3//COMMIT_MSG@9
PS3, Line 9: Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Please remove the duplicate line here, and leave the Signed-off-by line below.
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23 Jan
23 Jan
1:27 a.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 3:
(9 comments)
Patch Set 3:
Hi there Balázs! Please could you tell more about your hardware setup, especially what
CPU you are using with your A88XM-E board? Thank you in advance
It's an A8-6500.
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
File Documentation/mainboard/asus/a88xm-e.md:
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 13: and their GPU is [Sea Islands] (GCN2-based).
We have binaryPI blob for Kaveri, but it is for FP3
socket only. […]
Ack
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 59:
trailing space
Ack
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 83: - Integrated ethernet
Maybe it is missing a MAC address? coreboot has a
driver for that.
It's not. No interface/device found on OS level, neighter
during Coreboot init. But the device tree has been modified according to the factory
bios.
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 87:
trailing space
Ack
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 88: board with factory image makes it work again as fallback.
I think xhci firmware loader in fam15tn vendorcode was
buggy. […]
Angel:
Belive me, I tried literally everything. Somehow I managed it to work once on F2A85-M, but
never again. After starting with wrong blob, just another power off and boot with factory
image managed it to work again.
Kyösti:
the firmware is very similar for both chipsets, but it differs of course.
For both of you:
Can we go with extracted blobs (microcode, psp, vga, xhci...)? Are these allowed to ship
with the coreboot sources or are these marked as leaked ones?
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/Kconfig
File src/mainboard/asus/a88xm-e/Kconfig:
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/Kconfig@…
PS2, Line 29: SUPERIO_ITE_IT8728F
This works with the ITE IT8603?
Yes, it is.
Probably really same chip, just different package pin count.
https://lm-sensors.lm-sensors.narkive.com/VnxI9zvt/it8620e-it8623e-vs-it860…
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/Kconfig@…
PS2, Line 113: config DEVICETREE
: string
: default "devicetree_a88xm-e.cb"
Rename the devicetree to "devicetree.cb" and
drop this.
Done
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/board_in…
File src/mainboard/asus/a88xm-e/board_info.txt:
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/board_in…
PS2, Line 4:
[http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas…
SPI]
There is no need to link anything here. Just
"SPI" is enough.
Done
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/romstage…
File src/mainboard/asus/a88xm-e/romstage.c:
https://review.coreboot.org/#/c/30987/2/src/mainboard/asus/a88xm-e/romstage…
PS2, Line 49: pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
: pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
These can be macros
I wouldn't bother these
lines, the GPIO have a 0x07 value on superio/ite/it8728f/it8728f.h.
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1:47 a.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 3:
Patch Set 3:
(2 comments)
Could this be made a variant?
Do you mean a variant of the Asus A88-series?
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1:54 a.m.
New subject: Change in ...coreboot[master]: Add Asus A88XM-E FM2+ motherboard with documentation, the port based ...
Kyösti Mälkki has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: Add Asus A88XM-E FM2+ motherboard with documentation, the port based on
F2A85-M.
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
File Documentation/mainboard/asus/a88xm-e.md:
https://review.coreboot.org/#/c/30987/2/Documentation/mainboard/asus/a88xm-…
PS2, Line 88: board with factory image makes it work again as fallback.
Angel: […]
You will probably not get such blobs
merged, even extracted microcode updates have recently been rejected or are on indefinite
hold.
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2:54 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#4).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/4
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Gerrit-MessageType: newpatchset
2:55 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
(235 comments)
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
File src/mainboard/asus/a88xm-e/BiosCallOuts.c:
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 24: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 79: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 80: {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
"(foo*)" should be "(foo *)"
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 81: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
"(foo*)" should be "(foo *)"
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 84: void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK
*FchParams_reset)
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 92: FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST
*)(&CodecTableList[0]);
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/BiosCall…
PS4, Line 97: FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI
Auto Polling */
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 78: /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4)
*/
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 117: PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 147:
/*----------------------------------------------------------------------------------------
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 149:
*----------------------------------------------------------------------------------------
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 153: * Platform Specific Overriding Table allows IBV/OEM to pass in platform
information to AGESA
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 154: * (e.g. MemClk routing, the number of DIMM slots per channel,...). If
PlatformSpecificTable
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 155: * is populated, AGESA will base its settings on the data from the table.
Otherwise, it will
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 161: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 162: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 164: PSO_END
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/OemCusto…
PS4, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/acpi_tab…
File src/mainboard/asus/a88xm-e/acpi_tables.c:
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/acpi_tab…
PS4, Line 29: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
CONFIG_MAX_CPUS,
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/acpi_tab…
PS4, Line 42: current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
0xff, 5, 1);
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 142: #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread
Spectrum default value 0.36%
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 158: //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 159: //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable
NBPSI_L, Non-zero - enable NBPSI_L
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 160: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 161: //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 162: //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 163: //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently
used on Trinity
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
line over 80 characters
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
please, no space before tabs
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 174: #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
please, no space before tabs
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 230: {
that open brace { should be on the previous line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 231: { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 232: { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 233: { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 234: { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 235: { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 236: { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 237: { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 238: { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/#/c/30987/4/src/mainboard/asus/a88xm-e/buildOpt…
PS4, Line 239: { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
please, no spaces at the start of a line
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PS4, Line 240: { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
please, no spaces at the start of a line
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PS4, Line 241: { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
please, no spaces at the start of a line
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PS4, Line 242: { CPU_LIST_TERMINAL }
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PS4, Line 245: #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
Macros with complex values should be enclosed in parentheses
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PS4, Line 247: // This is the delivery package title,
"BrazosPI"
code indent should use tabs where possible
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PS4, Line 248: // This string MUST be exactly 8 characters long
code indent should use tabs where possible
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PS4, Line 251: // This is the release version number of the AGESA
component
code indent should use tabs where possible
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PS4, Line 252: // This string MUST be exactly 12 characters long
code indent should use tabs where possible
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PS4, Line 253: #define AGESA_VERSION_STRING {'V', '0', '.',
'0', '.', '0', '.', '1', ' ', ' ',
' ', ' '}
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PS4, Line 267: #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR
frequency
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PS4, Line 270: #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
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PS4, Line 271: #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
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PS4, Line 274: #define TIMING_MODE_AUTO 0 ///< Use best rate possible
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PS4, Line 275: #define TIMING_MODE_LIMITED 1 ///< Set user top limit
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PS4, Line 280: #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
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PS4, Line 334: // The following definitions specify the default values for various
parameters in which there are
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PS4, Line 335: // no clearly defined defaults to be used in the common file. The values
below are based on product
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File src/mainboard/asus/a88xm-e/irq_tables.c:
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PS4, Line 94: if (sum != pirq->checksum) {
braces {} are not necessary for single statement blocks
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PS4, Line 98: printk(BIOS_INFO, "write_pirq_routing_table done.\n");
Prefer using '"%s...", __func__' to using
'write_pirq_routing_table', this function's name, in a string
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File src/mainboard/asus/a88xm-e/mainboard.c:
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PS4, Line 28: printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER
" Enable.\n");
line over 80 characters
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File src/mainboard/asus/a88xm-e/mptable.c:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 26:
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PS4, Line 27:
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PS4, Line 27:
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PS4, Line 27:
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PS4, Line 27:
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PS4, Line 27:
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PS4, Line 27:
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PS4, Line 42: static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
Prefer 'unsigned int' to bare use of 'unsigned'
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PS4, Line 91: for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
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PS4, Line 102: /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID
PIN# */
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PS4, Line 103: #define IO_LOCAL_INT(type, intr, apicid, pin) \
macros should not use a trailing semicolon
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PS4, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin));
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PS4, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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PS4, Line 167: /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID
PIN# */
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File src/mainboard/asus/a88xm-e/romstage.c:
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PS4, Line 31: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 +
(x))
Macros with complex values should be enclosed in parentheses
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25 Jan
25 Jan
5:25 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
mikeb mikeb has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
A8-6500 (Richland)
I am curious if more powerful
A10 CPUs could work there, like A10-6700 (Richland) or A10-7800 (Kaveri) or A10-7870K
(Godavari). What do you think? And how much work would be needed (approximately) to get
them working in case they wouldn't work out-of-the-box?
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New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
mikeb mikeb has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
A8-6500 (Richland)
I am curious if more powerful A10 CPUs could work there, like A10-6700 (Richland) or
A10-7800 (Kaveri) or A10-7870K (Godavari). What do you think? And how much work would be
needed (approximately) to get them working in case they wouldn't work out-of-the-box?
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New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Patch Set 4:
A10-6700 should work out of the box, Kaveri needs some work with the AMD Agesa blob.
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A8-6500 (Richland)
I am curious if more powerful A10 CPUs could work there, like A10-6700 (Richland) or
A10-7800 (Kaveri) or A10-7870K (Godavari). What do you think? And how much work would be
needed (approximately) to get them working in case they wouldn't work out-of-the-box?
17 Feb
17 Feb
6:20 p.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
mikeb mikeb has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Patch Set 4:
Thank you for reply, maybe I would get A88XM-E FM2+ and A10-6700 also. Please could you
confirm that your board looks like this? https://www.asus.com/Motherboards/A88XME/ . I am
asking because there is also "A88XM-E/USB 3.1" board (don't know if it is
also supported or different enough)
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Patch Set 4:
A10-6700 should work out of the box, Kaveri needs some work with the AMD Agesa blob.
A8-6500 (Richland)
I am curious if more powerful A10 CPUs could work there, like A10-6700 (Richland) or
A10-7800 (Kaveri) or A10-7870K (Godavari). What do you think? And how much work would be
needed (approximately) to get them working in case they wouldn't work out-of-the-box?
9 Mar
9 Mar
1:09 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Thank you for reply, maybe I would get A88XM-E FM2+
and A10-6700 also. Please could you confirm that your board looks like this?
https://www.asus.com/Motherboards/A88XME/ . I am asking because there is also
"A88XM-E/USB 3.1" board (don't know if it is also supported or different
enough)
It's the vanilla A88XME version, not the USB3.1 one.
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1:26 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
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Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Patch Set 3:
(1 comment)
I spent a few hours with the blobizing :)
The original version seems to based so much on the open-source AGESA version, I
couldn't really make CPU_AMD_PI_00630F01 config to work.
Is there anything left to make this patch merged?
Do you have any idea, how can I make the NIC to work?
Replacing the pci route in the devicetree doesn't make any sense. The adater remain
unidentified during the boot as well.
Thanks
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3:30 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
mikeb mikeb has posted comments on this change. (
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Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Patch Set 4:
The original version seems to based so much on the open-source AGESA version, I
couldn't really make CPU_AMD_PI_00630F01 config to work.
In any case the open-source AGESA should be the way: it could be hard to attract more AMD
people to your platform if it is very blobbed. I am considering A88XME only because it has
opensource AGESA and no PSP backdoor inside the CPU - security is very important to me, so
I would prefer as much open-source code as possible.
Is there anything left to make this patch merged?
I haven't looked at your code yet (a bit busy with my own patches to be honest), but I
think you should try to fix as many "code style" warnings as possible. Please
see this message for a list -
https://review.coreboot.org/c/coreboot/+/30987#message-1484ecb7bc0a5a273dcd…
.
Do you have any idea, how can I make the NIC to work?
Replacing the pci route in the devicetree doesn't make any sense. The adapter remain
unidentified during the boot as well.
Could you build a coreboot with a max debug level (8: SPEW), and at the fully booted
system go to ./coreboot/util/cbmem/ , run "make", and then - sudo ./cbmem -c
> boot.log . That's to collect the whole coreboot boot log, to see if there are any
messages related to your NIC. Would be nice if you could upload such a log somewhere
(pastebin?) and share with us
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6:15 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Could you build a coreboot with a max debug level (8:
SPEW), and at the fully booted system go to ./coreboot/util/cbmem/ , run "make",
and then - sudo ./cbmem -c > boot.log . That's to collect the whole coreboot boot
log, to see if there are any messages related to your NIC. Would be nice if you could
upload such a log somewhere (pastebin?) and share with us
There is not a single line which points to a pci device found on the place where it exists
on the factory fw. Pastebin: https://pastebin.com/mQwUNgRx.
My idea would be that it's using some pci bridge, like in the F2A85M. I tried to
enable all the devices on the devicetree. Nothing showed up, but even the SDcard reader
etc.
```
Factory FW
03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express
Gigabit Ethernet Controller (rev 11)
Subsystem: ASUSTeK Computer Inc. RTL8111/8168/8411 PCI Express Gigabit Ethernet
Controller
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR-
FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort-
>SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 18
Region 0: I/O ports at e000 [size=256]
Region 2: Memory at fe900000 (64-bit, non-prefetchable) [size=4K]
Region 4: Memory at f0800000 (64-bit, prefetchable) [size=16K]
Capabilities: <access denied>
Kernel driver in use: r8169
Kernel modules: r8169
```
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11 Mar
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4:47 p.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
mikeb mikeb has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
I would have navigated the menus of "coreinfo" coreboot's secondary payload,
to see if there's anything interesting related to the PCI devices. Also: Please could
you plug in a discrete GPU (preferably AMD) into the PCI Express slot, and check if it is
working?
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New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Patch Set 4:
I would have navigated the menus of "coreinfo" coreboot's secondary
payload, to see if there's anything interesting related to the PCI devices. Also:
Please could you plug in a discrete GPU (preferably AMD) into the PCI Express slot, and
check if it is working?
I have an old X1050 just works perfect, if the setting are not forcing the iGPU which
works fine as well.
Host and PCI bridges (below) seems to missing from the list. I checked with both coreinfo
and Linux OS. So these are available on the factory image. External NIC also working
fine.
00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh)
Processor Root Port
00:03.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh)
Processor Root Port
00:04.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh)
Processor Root Port
00:15.0 PCI bridge: Advanced Micro Devices, Inc. [AMD] Hudson PCI to PCI bridge (PCIE port
0)
00:15.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Hudson PCI to PCI bridge (PCIE port
2)
As far as I remember I had the same problem before Bolton and Hudson has been merged, but
I'll have a look later.
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17 Apr
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New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
mikeb mikeb has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Martin Roth, huge thanks to you ;-) I got a couple of used A88XM-E boards from AliExpress
(one spare just in case) and A10-6700 CPU for FM2 socket with heatsink according to Balázs
Vinarz advice. Hopefully I'll be able to help him getting this board merged at the
near future :D
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8:54 p.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Paul Menzel has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/30987/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/30987/4//COMMIT_MSG@9
PS4, Line 9: Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Please move this to the very bottom right below the Change-Id line.
https://review.coreboot.org/#/c/30987/4//COMMIT_MSG@10
PS4, Line 10: Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
This is duplicated and can be removed.
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29 Jun
29 Jun
9:51 p.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Mike Banon has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
@Balazs : is there any difference between this patch and CB:31039 which got sent a few
days later? Also, are you going to keep working on this patch, or I could re-submit it (of
course mentioning your original authorship) to continue your work when I have more free
time?
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2 Jul
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2:25 a.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Patch Set 4:
@Balazs : is there any difference between this patch and CB:31039 which got sent a few
days later? Also, are you going to keep working on this patch, or I could re-submit it (of
course mentioning your original authorship) to continue your work when I have more free
time?
That one was created accidentally, just a duplicate. I recreated a pull request instead of
working on this one.
I have some free time in the weekend. Did you gained any progress?
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2:22 p.m.
New subject: Change in ...coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Mike Banon has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
I have some free time in the weekend. Did you gained any progress?
Currently I'm trying to fix a "low RAM speed" bug of AMD 16h ASUS AM1I-A
board - and going to have a vacation soon, so wouldn't be able to start real work on
A88XM-E until September. To be honest, I was asking in ahead. But I hope to at least test
your code in the near future and write some reports. So if you have some experimental
builds or ideas, or the code which has not been submitted to this patch yet - please
share
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24 Jul
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11:36 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Currently I'm trying to fix a "low RAM
speed" bug of AMD 16h ASUS AM1I-A board - and going to have a vacation soon, so
wouldn't be able to start real work on A88XM-E until September. To be honest, I was
asking in ahead. But I hope to at least test your code in the near future and write some
reports. So if you have some experimental builds or ideas, or the code which has not been
submitted to this patch yet - please share
I uploaded the latest version, I had. Nothing else remain uncommited :)
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20 Nov
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6:03 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Mike Banon has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 4:
Previous parent is 69f6fd4 (69f6fd4589ee4d7cb0bfa12face26eba1fa0a973) - AGESA/binaryPI:
Add NULL pointers check, Tue Jan 22 14:06:39 2019 +0000 . Rebasing on top of master...
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6:03 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 5:
(199 comments)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/BiosCallOuts.c:
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 24: {
that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 79: {
that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 80: {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
"(foo*)" should be "(foo *)"
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 81: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
"(foo*)" should be "(foo *)"
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 161: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 162: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 164: PSO_END
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 142: #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread
Spectrum default value 0.36%
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 159: //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable
NBPSI_L, Non-zero - enable NBPSI_L
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 160: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 173: //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000
<< 16) = 256M*/
please, no space before tabs
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 174: #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
please, no space before tabs
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 230: {
that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 231: { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 232: { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 233: { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 234: { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 235: { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 236: { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 237: { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 238: { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 239: { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 240: { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 241: { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 242: { CPU_LIST_TERMINAL }
please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 245: #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 247: // This is the delivery package title,
"BrazosPI"
code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 248: // This string MUST be exactly 8 characters long
code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 251: // This is the release version number of the AGESA
component
code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 252: // This string MUST be exactly 12 characters long
code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 334: // The following definitions specify the default values for various
parameters in which there are
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 335: // no clearly defined defaults to be used in the common file. The values
below are based on product
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/irq_tables.c:
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 94: if (sum != pirq->checksum) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 98: printk(BIOS_INFO, "write_pirq_routing_table done.\n");
Prefer using '"%s...", __func__' to using
'write_pirq_routing_table', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS5, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS5, Line 39: 0x10,0x11,0x12,0x13
space required after that ',' (ctx:VxV)
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PS5, Line 39: 0x10,0x11,0x12,0x13
space required after that ',' (ctx:VxV)
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PS5, Line 39: 0x10,0x11,0x12,0x13
space required after that ',' (ctx:VxV)
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PS5, Line 42: static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 91: for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
space prohibited before that '++' (ctx:WxB)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 97: for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
space prohibited before that '++' (ctx:WxB)
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 103: #define IO_LOCAL_INT(type, intr, apicid, pin) \
macros should not use a trailing semicolon
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin));
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/romstage.c:
https://review.coreboot.org/c/coreboot/+/30987/5/src/mainboard/asus/a88xm-e…
PS5, Line 31: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 +
(x))
Macros with complex values should be enclosed in parentheses
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Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 5
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-MessageType: comment
22 Nov
22 Nov
10:20 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#6).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/6
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Gerrit-MessageType: newpatchset
10:20 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 6:
(167 comments)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 163: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 247: #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 336: // The following definitions specify the default values for various
parameters in which there are
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 337: // no clearly defined defaults to be used in the common file. The values
below are based on product
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/irq_tables.c:
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 94: if (sum != pirq->checksum) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 98: printk(BIOS_INFO, "write_pirq_routing_table done.\n");
Prefer using '"%s...", __func__' to using
'write_pirq_routing_table', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
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PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 26:
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 27:
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS6, Line 27:
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS6, Line 27:
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS6, Line 27:
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS6, Line 38:
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PS6, Line 38:
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
space required after that ',' (ctx:VxV)
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PS6, Line 38:
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space required after that ',' (ctx:VxV)
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PS6, Line 38:
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PS6, Line 38:
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PS6, Line 38:
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space required after that ',' (ctx:VxV)
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PS6, Line 38:
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PS6, Line 39: 0x10,0x11,0x12,0x13
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PS6, Line 39: 0x10,0x11,0x12,0x13
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PS6, Line 39: 0x10,0x11,0x12,0x13
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PS6, Line 103: #define IO_LOCAL_INT(type, intr, apicid, pin) \
macros should not use a trailing semicolon
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin));
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/romstage.c:
https://review.coreboot.org/c/coreboot/+/30987/6/src/mainboard/asus/a88xm-e…
PS6, Line 31: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 +
(x))
Macros with complex values should be enclosed in parentheses
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Gerrit-Change-Number: 30987
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10:22 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 6:
Patch Set 4:
Previous parent is 69f6fd4 (69f6fd4589ee4d7cb0bfa12face26eba1fa0a973) - AGESA/binaryPI:
Add NULL pointers check, Tue Jan 22 14:06:39 2019 +0000 . Rebasing on top of master...
Hi Mike!
Do you mind, could we ever merge this?
I just fixed some of the code style errors, which I felt problematic.
I still have the mobo and a CPU somewhere, I could test the build.
Regards
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23 Nov
23 Nov
5:43 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Mike Banon has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 6:
Patch Set 6:
Balazs, I'm very sorry for delay, but I really hope to work on this patch in the near
future (winter holidays). I also have this board, so we are in the same boat.
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Patch Set 4:
Previous parent is 69f6fd4 (69f6fd4589ee4d7cb0bfa12face26eba1fa0a973) - AGESA/binaryPI:
Add NULL pointers check, Tue Jan 22 14:06:39 2019 +0000 . Rebasing on top of master...
Hi Mike!
Do you mind, could we ever merge this?
I just fixed some of the code style errors, which I felt problematic.
I still have the mobo and a CPU somewhere, I could test the build.
Regards
8 Dec
8 Dec
9:38 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 7:
(167 comments)
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
PS7, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
PS7, Line 163: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 96 characters
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PS7, Line 247: #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
Macros with complex values should be enclosed in parentheses
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PS7, Line 336: // The following definitions specify the default values for various
parameters in which there are
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PS7, Line 337: // no clearly defined defaults to be used in the common file. The values
below are based on product
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File src/mainboard/asus/a88xm-e/irq_tables.c:
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
PS7, Line 94: if (sum != pirq->checksum) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
PS7, Line 98: printk(BIOS_INFO, "write_pirq_routing_table done.\n");
Prefer using '"%s...", __func__' to using
'write_pirq_routing_table', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/mptable.c:
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PS7, Line 26:
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PS7, Line 26:
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PS7, Line 26:
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PS7, Line 26:
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PS7, Line 26:
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PS7, Line 26:
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PS7, Line 27:
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PS7, Line 27:
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PS7, Line 27:
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PS7, Line 27:
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bus_isa, (intr), (apicid), (pin));
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https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
PS7, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/romstage.c:
https://review.coreboot.org/c/coreboot/+/30987/7/src/mainboard/asus/a88xm-e…
PS7, Line 31: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 +
(x))
Macros with complex values should be enclosed in parentheses
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Gerrit-Branch: master
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Gerrit-Change-Number: 30987
Gerrit-PatchSet: 7
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11:18 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#8).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,373 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/8
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Gerrit-PatchSet: 8
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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Gerrit-MessageType: newpatchset
11:19 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 8:
(162 comments)
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
PS8, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
PS8, Line 165: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/irq_tables.c:
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
PS8, Line 97: printk(BIOS_INFO, "%s done.\n", __func__,);
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File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/c/coreboot/+/30987/8/src/mainboard/asus/a88xm-e…
PS8, Line 26:
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 8
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-CC: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Sun, 08 Dec 2019 15:19:07 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
11:31 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#9).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,373 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/9
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 9
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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11:31 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 9:
(161 comments)
https://review.coreboot.org/c/coreboot/+/30987/9/src/mainboard/asus/a88xm-e…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/9/src/mainboard/asus/a88xm-e…
PS9, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
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File src/mainboard/asus/a88xm-e/buildOpts.c:
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PS9, Line 165: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
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File src/mainboard/asus/a88xm-e/irq_tables.c:
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File src/mainboard/asus/a88xm-e/mptable.c:
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PS9, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin))
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PS9, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 96 characters
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Gerrit-Change-Number: 30987
Gerrit-PatchSet: 9
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11:37 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#10).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,373 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/10
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11:38 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 10:
(5 comments)
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
PS10, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/buildOpts.c:
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
PS10, Line 165: //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in
calculating the VSRampSlamTime
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/irq_tables.c:
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
PS10, Line 97: printk(BIOS_INFO, "%s done.\n", __func__,);
space required after that ',' (ctx:VxB)
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
PS10, Line 104: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), (apicid), (pin))
line over 96 characters
https://review.coreboot.org/c/coreboot/+/30987/10/src/mainboard/asus/a88xm-…
PS10, Line 111: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
line over 96 characters
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Gerrit-Change-Number: 30987
Gerrit-PatchSet: 10
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-Comment-Date: Sun, 08 Dec 2019 15:38:07 +0000
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11:50 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#11).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,377 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/11
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Gerrit-Change-Number: 30987
Gerrit-PatchSet: 11
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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Gerrit-MessageType: newpatchset
11:51 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30987/11/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/11/src/mainboard/asus/a88xm-…
PS11, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
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Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
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Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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9 Dec
9 Dec
12:27 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#12).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,380 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/12
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Gerrit-Change-Number: 30987
Gerrit-PatchSet: 12
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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Gerrit-MessageType: newpatchset
12:27 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30987/12/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/12/src/mainboard/asus/a88xm-…
PS12, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
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Gerrit-Change-Number: 30987
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Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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15 Dec
15 Dec
10:24 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#13).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,380 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/13
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Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
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10:24 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30987/13/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/13/src/mainboard/asus/a88xm-…
PS13, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
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16 Dec
16 Dec
4:05 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Kyösti Mälkki has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 13:
Boards with ROMCC_BOOTBLOCK=y are no longer accepted or build-tested on master.
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4:07 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#14).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/14
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4:08 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30987/14/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/14/src/mainboard/asus/a88xm-…
PS14, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
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17 Dec
4:42 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 14:
Patch Set 13:
Boards with ROMCC_BOOTBLOCK=y are no longer accepted or build-tested on master.
Thanks for the heads-up!
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20 Dec
20 Dec
9:33 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#15).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,367 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/15
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9:33 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30987/15/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/15/src/mainboard/asus/a88xm-…
PS15, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
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9:47 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 15:
Key differences:
F2A85MLE
lshw
*-pci:2
description: PCI bridge
product: Hudson PCI to PCI bridge (PCIE port 1)
vendor: Advanced Micro Devices, Inc. [AMD]
physical id: 15.1
bus info: pci@0000:00:15.1
version: 00
width: 32 bits
clock: 33MHz
capabilities: pci pm pciexpress msi ht normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:17 ioport:d000(size=4096) ioport:d0000000(size=1048576)
*-network
description: Ethernet interface
product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
vendor: Realtek Semiconductor Co., Ltd.
physical id: 0
bus info: pci@0000:03:00.0
logical name: enp3s0
version: 09
serial: 08:60:6e:e5:a2:02
capacity: 1Gbit/s
width: 64 bits
clock: 33MHz
capabilities: pm msi pciexpress msix vpd bus_master cap_list ethernet physical tp mii
10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation
configuration: autonegotiation=on broadcast=yes driver=r8169 firmware=rtl8168f-1_0.0.5
06/18/12 latency=0 link=no multicast=yes port=MII
resources: irq:17 ioport:d000(size=256) memory:d0004000-d0004fff
memory:d0000000-d0003fff
A88XME
lshw
*-pci:2
description: PCI bridge
product: Hudson PCI to PCI bridge (PCIE port 2)
vendor: Advanced Micro Devices, Inc. [AMD]
physical id: 15.2
bus info: pci@0000:00:15.2
version: 00
width: 32 bits
clock: 33MHz
capabilities: pci pm pciexpress msi ht normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:17 ioport:d000(size=4096) memory:fe900000-fe9fffff
ioport:f0000000(size=1048576)
*-network
description: Ethernet interface
product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
vendor: Realtek Semiconductor Co., Ltd.
physical id: 0
bus info: pci@0000:03:00.0
logical name: enp3s0
version: 11
serial: 40:16:7e:7a:e1:47
capacity: 1Gbit/s
width: 64 bits
clock: 33MHz
capabilities: pm msi pciexpress msix vpd bus_master cap_list ethernet physical tp aui
bnc mii fibre 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation
configuration: autonegotiation=on broadcast=yes driver=r8169 firmware=rtl8168g-2_0.0.1
02/06/13 latency=0 link=no multicast=yes port=MII
resources: irq:18 ioport:d000(size=256) memory:fe900000-fe900fff
memory:f0000000-f0003fff
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21 Dec
21 Dec
1:01 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30987
to look at the new patch set (#16).
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
mb/asus: Add Asus A88XM-E FM2+ with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- Kaveri/Godavari support
- no optical SPDIF/IO
Successfully booted configuration:
- 2*8 GB Kingston KVR 1333 Mhz (LP)
- A8-6500 (Richland)
- Arch Linux 4.19 from both SATA and USB
- Seabios 1.12
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,364 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/16
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New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30987/16/src/mainboard/asus/a88xm-…
File src/mainboard/asus/a88xm-e/OemCustomize.c:
https://review.coreboot.org/c/coreboot/+/30987/16/src/mainboard/asus/a88xm-…
PS16, Line 170: InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)
MemoryTable_XM_E;
line over 96 characters
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7:46 p.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Balázs Vinarz has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 16:
Hi!
Can some of the reviewers guide me?
I'd like to make this port upstream. What should I do to make it merged?
Regards
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23 Dec
23 Dec
2:02 a.m.
New subject: Change in coreboot[master]: mb/asus: Add Asus A88XM-E FM2+ with documentation
Mike Banon has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/30987 )
Change subject: mb/asus: Add Asus A88XM-E FM2+ with documentation
......................................................................
Patch Set 16:
Patch Set 16:
Hi!
Can some of the reviewers guide me?
I'd like to make this port upstream. What should I do to make it merged?
Regards
Good day! You need to check the "switch away from ROMCC_BOOTBLOCK", especially
CB:37727 ( https://review.coreboot.org/c/coreboot/+/37727 ) since your port is based on
F2A85-M, and try to do the same for your change - while preserving as many code as
possible, and ensuring that your board is still booting. This switch is quite easy by the
way, I've done it for a few boards this week.
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