coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Nico Huber (Code Review) 05 Aug '19

05 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31457 Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [WIP] 3rdparty/libgfxinit: Update submodule pointer Update libgfxinit: o Add support for ULX (CPU Y series) variants o Add support for Kaby/Coffee/Whiskey/Amber Lakes o Publish Read_EDID() procedure Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31457/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index f70edda..47fa150 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit f70eddafbc2c6045a14e2f8bbb3273ee738fbaf7 +Subproject commit 47fa150df7ffee54659aebfdc78ff644ad319894 -- To view, visit https://review.coreboot.org/c/coreboot/+/31457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f Gerrit-Change-Number: 31457 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/sifive/fu540: Add opensbi support
by Patrick Rudolph (Code Review) 05 Aug '19

05 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34142 ) Change subject: soc/sifive/fu540: Add opensbi support ...................................................................... soc/sifive/fu540: Add opensbi support Change-Id: I35abacc16f244b95f9fd1947d1a5ea10c4dee097 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/sifive/fu540/Kconfig M src/soc/sifive/fu540/include/soc/memlayout.ld 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34142/1 diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..dcf7896 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,11 @@ int default 0 +config OPENSBI_PLATFORM + string + default "sifive/fu540" + +config OPENSBI_TEXT_START + hex + default 0x80000000 endif diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..1d11aa0 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -31,6 +31,7 @@ L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) - RAMSTAGE(FU540_DRAM, 256K) - MEM_STACK(FU540_DRAM + 256K, 20K) + REGION(opensbi, FU540_DRAM, 128K, 4K) + RAMSTAGE(FU540_DRAM + 128K, 256K) + MEM_STACK(FU540_DRAM + 448K, 20K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/34142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35abacc16f244b95f9fd1947d1a5ea10c4dee097 Gerrit-Change-Number: 34142 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: DO NOT SUBMIT: It is just init current BOE TV101WUM-NL2 panel, it is ...
by Peichao Li (Code Review) 05 Aug '19

05 Aug '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33184 Change subject: DO NOT SUBMIT: It is just init current BOE TV101WUM-NL2 panel, it is not final soultion of Bitland kukui project. ...................................................................... DO NOT SUBMIT: It is just init current BOE TV101WUM-NL2 panel, it is not final soultion of Bitland kukui project. *** DO NOT SUBMIT *** Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I1191b33c63ba9947e700670882a048b014fb7c27 --- M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/display.c A src/mainboard/google/kukui/display.h M src/mainboard/google/kukui/mainboard.c A src/mainboard/google/kukui/panel_bitland.c 5 files changed, 382 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/33184/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..49f09c7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -22,6 +22,9 @@ ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c +ramstage-y += panel_bitland.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c new file mode 100644 index 0000000..68042d5 --- /dev/null +++ b/src/mainboard/google/kukui/display.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> +#include "display.h" +#include "gpio.h" + +static void _display_startup(struct edid *edid, + struct lcm_init_table *init_table, + u32 init_table_size) +{ + int ret = 0; + u32 mipi_dsi_flags; + if ((edid == NULL) || (init_table == NULL)) { + printk(BIOS_ERR, "%s: wrong parameters\n", __func__); + return; + } + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM; + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, edid, init_table, init_table_size); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } + mtk_ddp_mode_set(edid); + set_vbe_mode_info_valid(edid, (uintptr_t) 0); +} + +static struct edid *get_edid(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + if (info) + return info->edid; + return NULL; +} + +static struct lcm_init_table *get_panel_init_table(struct board_display_intf + *intf, u32 *table_size) +{ + struct panel_info *info = intf->cur_panel_info; + if (info) { + *table_size = info->table_size; + return info->init_table; + } + *table_size = 0; + return NULL; +} + +static const char *get_panel_name(struct board_display_intf *intf) +{ + struct panel_info *info = intf->cur_panel_info; + if (info) + return info->panel_name; + return NULL; +} + +/* Exported Functions */ +struct board_display_intf *get_current_display_intf(void) +{ + return &bitland_panel_display_intf; +} + +int update_panel_info(struct board_display_intf *intf) +{ + int i; + union panel_id id = intf->get_panel_id(intf); + if (intf->is_panel_id_valid(id)) { + for (i = 0; i < intf->all_panel_info_size; ++i) { + if (id.value == intf->all_panel_info[i].disp_id.value) { + intf->cur_panel_info = &intf->all_panel_info[i]; + return 0; + } + } + } + return ERR; +} + +void configure_backlight(void) +{ + /* Configure PANEL_LCD_POWER_EN */ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ +} + +void display_startup(struct board_display_intf *intf) +{ + struct edid *edid; + u32 init_table_size; + struct lcm_init_table *init_table; + edid = get_edid(intf); + init_table = get_panel_init_table(intf, &init_table_size); + printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n", + __func__, get_panel_name(intf), init_table_size); + _display_startup(edid, init_table, init_table_size); +} + diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h new file mode 100644 index 0000000..1e65720 --- /dev/null +++ b/src/mainboard/google/kukui/display.h @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Bitland tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_DISPLAY_H__ + +#include <soc/dsi.h> +#include <soc/gpio.h> + +#define ERR (-1) +#define OK (1) + +#define MAKE_AS_A_STRING(arg) #arg + +enum kukui_panel_id { + PANEL_KUKUI_FIRST = 0, + PANEL_KUKUI_INNOLUX = 0, + PANEL_KUKUI_P097PFG_SSD2858, + PANEL_KUKUI_UNKNOWN, + PANEL_KUKUI_COUNT, + PANEL_KUKUI_UNINITIALIZED +}; + +enum krane_panel_id { + PANEL_KRANE_FIRST = 0, + PANEL_KRANE_BOE_TV101WUM_NL6, + PANEL_KRANE_BOE_TV101WUM_NL2, + PANEL_KRANE_UNKNOWN, + PANEL_KRANE_COUNT, + PANEL_KRANE_UNINITIALIZED +}; + + +union panel_id { + enum kukui_panel_id kukui_panel; + enum krane_panel_id krane_panel; + int value; +}; + +struct panel_info { + union panel_id disp_id; /* the ID for panel */ + const char *panel_name; /* display panel name */ + int voltage; /* voltage of LCM_ID */ + struct edid *edid; /* edid info of this panel */ + struct lcm_init_table *init_table; /* init command table */ + u32 table_size; /* init command table size */ +}; + +#define PANEL(_panel_id, _voltage, _edid, _init_table) \ + { \ + .disp_id = {_panel_id},\ + .panel_name = MAKE_AS_A_STRING(_panel_id),\ + .voltage = _voltage,\ + .edid = &_edid,\ + .init_table = _init_table,\ + .table_size = ARRAY_SIZE(_init_table)} \ + + +struct board_display_intf { + const char *board; /* board name */ + struct panel_info *all_panel_info; /* all supported panel info */ + u32 all_panel_info_size; /* num of supported panel */ + /* + * Runtime member + */ + struct panel_info *cur_panel_info; /* detected panel info */ + /* + * board related functions + */ + + union panel_id (*get_panel_id)(struct board_display_intf *intf); + bool (*is_panel_id_valid)(union panel_id id); + int (*backlight)(struct board_display_intf *intf); + int (*power)(struct board_display_intf *intf); +}; + +/* + * Exported functions + */ + +struct board_display_intf *get_current_display_intf(void); +int update_panel_info(struct board_display_intf *intf); +void configure_backlight(void); +void display_startup(struct board_display_intf *intf); + + +/* + * Panel Interface for boards + */ +extern struct board_display_intf bitland_panel_display_intf; + +#endif + diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 40b8a49..aea91cb 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -14,10 +14,15 @@ */ #include <device/device.h> +#include <soc/bl31_plat_params.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> #include <soc/usb.h> +#include <console/console.h> +#include "display.h" +#include "gpio.h" + static void configure_emmc(void) { @@ -49,11 +54,37 @@ gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); } + +static void register_reset_to_bl31(void) +{ + static struct bl31_gpio_param param_reset = { + .h = { + .type = PARAM_RESET, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_HIGH, + }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_param(&param_reset.h); +} + static void mainboard_init(struct device *dev) { + struct board_display_intf *intf; + intf = get_current_display_intf(); + if (intf != NULL) { + display_startup(intf); + } else { + printk(BIOS_INFO, "Display init failure.\n"); + } + configure_emmc(); configure_usb(); configure_audio(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/kukui/panel_bitland.c b/src/mainboard/google/kukui/panel_bitland.c new file mode 100644 index 0000000..955c117 --- /dev/null +++ b/src/mainboard/google/kukui/panel_bitland.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 bitland tech Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +static struct edid kukui_boe_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159391, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 142, .y_mm = 228, + }, +}; + +struct lcm_init_table lcm_boe_init_cmd[] = { + /* For full HD */ + {INIT_DCS_CMD, 1, {0x11} }, + {DELAY_CMD, 800, {} }, + {INIT_DCS_CMD, 2, {0x36, 0x03} }, + {INIT_DCS_CMD, 1, {0x29} }, + {DELAY_CMD, 20, {} }, + {INIT_DCS_CMD, 2, {0x85, 0x04} }, + {INIT_DCS_CMD, 2, {0x86, 0x08} }, + {INIT_DCS_CMD, 2, {0x83, 0xAA} }, + {INIT_DCS_CMD, 2, {0x84, 0x11} }, + {INIT_DCS_CMD, 2, {0x98, 0x12} }, + +}; + +struct panel_info krane_panel_info[] = { + PANEL(PANEL_KRANE_BOE_TV101WUM_NL2, + 74000, + kukui_boe_edid, + lcm_boe_init_cmd), + {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id krane_get_panel_id(struct board_display_intf *intf) +{ + return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL2; +}; + +static bool krane_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_KRANE_UNKNOWN) + return true; + return false; +}; + + +static int krane_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int krane_power(struct board_display_intf *intf) +{ + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(1500); + //gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + mdelay(5); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(MISC_BSI_CK_3), 1); + mdelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + } + + return 0; + +}; + +struct board_display_intf bitland_panel_display_intf = { + .board = "krane", + .all_panel_info = krane_panel_info, + .all_panel_info_size = ARRAY_SIZE(krane_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &krane_get_panel_id, + .is_panel_id_valid = &krane_is_panel_id_valid, + .backlight = &krane_backlight, + .power = &krane_power, +}; + -- To view, visit https://review.coreboot.org/c/coreboot/+/33184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1191b33c63ba9947e700670882a048b014fb7c27 Gerrit-Change-Number: 33184 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/intel/common/block/uart: Update the UART PCI device reference
by Aamir Bohra (Code Review) 04 Aug '19

04 Aug '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34582 ) Change subject: soc/intel/common/block/uart: Update the UART PCI device reference ...................................................................... soc/intel/common/block/uart: Update the UART PCI device reference This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device refernce using pcidev_path_on_root. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/icelake/uart.c M src/soc/intel/skylake/uart.c 5 files changed, 19 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34582/1 diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 27be4e6..de07a80 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -82,13 +82,13 @@ */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART2); case 3: - return (struct device *)PCH_DEV_UART3; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART3); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 7174a9a..1909996 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -58,11 +58,11 @@ */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 82e5df4..6a4765d 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -71,7 +71,8 @@ void uart_common_init(struct device *device, uintptr_t baseaddr) { #if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = (pci_devfn_t)(uintptr_t)device; + unsigned int devfn = device->path.pci.devfn; + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); #else struct device *dev = device; #endif @@ -108,11 +109,13 @@ bool uart_is_controller_initialized(void) { uintptr_t base; + struct device *dev_uart = uart_get_device(); #if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = (pci_devfn_t)(uintptr_t)uart_get_device(); + unsigned int devfn = dev_uart->path.pci.devfn; + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); #else - struct device *dev = uart_get_device(); + struct device *dev = dev_uart; #endif if (!dev) return false; diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 7174a9a..1909996 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -58,11 +58,11 @@ */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 8b7c99e..ee181dc 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -59,11 +59,11 @@ */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return (struct device *)pcidev_path_on_root(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/34582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Gerrit-Change-Number: 34582 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: lib: Add FIT payload support
by Martin Roth (Code Review) 04 Aug '19

04 Aug '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25019 ) Change subject: lib: Add FIT payload support ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/c/coreboot/+/25019/37/src/lib/fit_payload.c File src/lib/fit_payload.c: https://review.coreboot.org/c/coreboot/+/25019/37/src/lib/fit_payload.c@45 PS37, Line 45: * Returns true on error, false on success. Patrick, This was just pointed out in another commit. Maybe add a comment as to WHY it was done this way, because this is not what's expected. -- To view, visit https://review.coreboot.org/c/coreboot/+/25019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Gerrit-Change-Number: 25019 Gerrit-PatchSet: 37 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Sun, 04 Aug 2019 15:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] utils/inteltool: More refactoring
by Felix Singer (Code Review) 03 Aug '19

03 Aug '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33422 ) Change subject: [WIP] utils/inteltool: More refactoring ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/33422/3/util/inteltool/inteltool.c File util/inteltool/inteltool.c: https://review.coreboot.org/c/coreboot/+/33422/3/util/inteltool/inteltool.c… PS3, Line 815: > I will remove it in the next patch set. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Aug 2019 19:12:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] utils/inteltool: More refactoring
by Felix Singer (Code Review) 03 Aug '19

03 Aug '19

Hello Marius Genheimer, Patrick Rudolph, Matt DeVillier, Thomas Heijligen, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33422 to look at the new patch set (#4). Change subject: [WIP] utils/inteltool: More refactoring ...................................................................... [WIP] utils/inteltool: More refactoring * Add new method `print_system_info` to get a better idea what this code does * Assign PCI devices through switch case by checking the device classes Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 82 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/33422/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] utils/inteltool: More refactoring
by Felix Singer (Code Review) 03 Aug '19

03 Aug '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33422 ) Change subject: [WIP] utils/inteltool: More refactoring ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/33422/3/util/inteltool/inteltool.c File util/inteltool/inteltool.c: https://review.coreboot.org/c/coreboot/+/33422/3/util/inteltool/inteltool.c… PS3, Line 815: > extra newline? I will remove it in the next patch set. -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Aug 2019 18:30:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] utils/inteltool: More refactoring
by Matt DeVillier (Code Review) 03 Aug '19

03 Aug '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33422 ) Change subject: [WIP] utils/inteltool: More refactoring ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/33422/3/util/inteltool/inteltool.c File util/inteltool/inteltool.c: https://review.coreboot.org/c/coreboot/+/33422/3/util/inteltool/inteltool.c… PS3, Line 815: extra newline? -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Aug 2019 17:37:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/i945,gm45,pineview,x4x: Fix stage cache location
by Martin Roth (Code Review) 03 Aug '19

03 Aug '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34671 ) Change subject: intel/i945,gm45,pineview,x4x: Fix stage cache location ...................................................................... intel/i945,gm45,pineview,x4x: Fix stage cache location The cache is at the end of TSEG. As SMM_RESERVED_SIZE was half of TSEG size, offseting from the start gave same position. Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34671 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c 4 files changed, 12 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 719c59f..6795f7a 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -126,13 +126,12 @@ void stage_cache_external_region(void **base, size_t *size) { - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + /* The stage cache lives at the end of the TSEG region. * The top of RAM is defined to be the TSEG base address. */ *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); } /* platform_enter_postcar() determines the stack to use after diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index dbe74c4..ac1499e 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -92,13 +92,12 @@ void stage_cache_external_region(void **base, size_t *size) { - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + /* The stage cache lives at the end of the TSEG region. * The top of RAM is defined to be the TSEG base address. */ *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); } /* platform_enter_postcar() determines the stack to use after diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index a3caaf7..2f3ff6e 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -142,13 +142,12 @@ void stage_cache_external_region(void **base, size_t *size) { - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + /* The stage cache lives at the end of the TSEG region. * The top of RAM is defined to be the TSEG base address. */ *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); } /* platform_enter_postcar() determines the stack to use after diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 54295a9..dda8387 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -137,13 +137,12 @@ void stage_cache_external_region(void **base, size_t *size) { - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + /* The stage cache lives at the end of the TSEG region. * The top of RAM is defined to be the TSEG base address. */ *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); } /* platform_enter_postcar() determines the stack to use after -- To view, visit https://review.coreboot.org/c/coreboot/+/34671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7 Gerrit-Change-Number: 34671 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit August 2019