coreboot-gerrit August 2019

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Change in coreboot[master]: soc/intel/skylake: Make use of common thermal code for SKL
by Subrata Banik (Code Review) 02 Aug '19

02 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34648 ) Change subject: soc/intel/skylake: Make use of common thermal code for SKL ...................................................................... soc/intel/skylake: Make use of common thermal code for SKL This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/finalize.c D src/soc/intel/skylake/include/soc/thermal.h D src/soc/intel/skylake/thermal.c 12 files changed, 16 insertions(+), 149 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34648/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 7fcb3b8..50cb0e5 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -64,7 +64,6 @@ register "tdp_pl2_override" = "15" register "psys_pmax" = "45" register "tcc_offset" = "10" - register "pch_trip_temp" = "75" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -182,6 +181,7 @@ #| I2C2 | Trackpad | #| I2C3 | Camera | #| I2C4 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -217,6 +217,7 @@ .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = "75", }" # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 727a10f..b2239bf 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -177,6 +177,7 @@ #| I2C3 | Pen | #| I2C4 | Camera | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -226,6 +227,7 @@ .sda_hold = 36, }, }, + .pch_thermal_trip = "75", }" # Touchscreen @@ -270,9 +272,6 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 7c11ea1..0bcdb3e 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -219,6 +219,7 @@ #| I2C1 | Trackpad | #| I2C2 | Pen | #| I2C3 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -263,6 +264,7 @@ .sda_hold = 36, }, }, + .pch_thermal_trip = "75", }" # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -285,9 +287,6 @@ register "tcc_offset" = "3" # TCC of 97C register "psys_pmax" = "101" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 1e4133b..1efadad 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -189,6 +189,7 @@ #| I2C3 | Pen | #| I2C4 | Camera | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -247,6 +248,7 @@ .sda_hold = 36, }, }, + .pch_thermal_trip = "75", }" # Touch Screen @@ -291,9 +293,6 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index bf1897c..5f2841d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -67,7 +67,6 @@ register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" - register "pch_trip_temp" = "75" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -201,6 +200,7 @@ #| I2C3 | Camera | #| I2C4 | Audio | #| I2C5 | Rear Camera & SAR | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -241,6 +241,7 @@ .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = "75", }" # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 1f73a59..19ad997 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -172,6 +172,7 @@ #| I2C0 | Touchscreen | #| I2C1 | Trackpad | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -207,6 +208,7 @@ .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = "75", }" # Touchscreen @@ -242,9 +244,6 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 872e2e5..6bb56c9 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -179,6 +179,7 @@ #| I2C2 | Camera | #| I2C4 | Camera | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -228,6 +229,7 @@ .sda_hold = 36, }, }, + .pch_thermal_trip = "75", }" # Touchscreen @@ -271,9 +273,6 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..4def3b3 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -69,6 +69,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BLOCK_THERMAL select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 913a9d9..e2f5c1b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -64,7 +64,6 @@ ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c -ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += xhci.c diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 3c137c5..8afaf4d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -26,6 +26,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <intelblocks/thermal.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/me.h> @@ -35,7 +36,6 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/systemagent.h> -#include <soc/thermal.h> #include <stdlib.h> #include <timer.h> diff --git a/src/soc/intel/skylake/include/soc/thermal.h b/src/soc/intel/skylake/include/soc/thermal.h deleted file mode 100644 index 31c47c6..0000000 --- a/src/soc/intel/skylake/include/soc/thermal.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_THERMAL_H_ -#define _SOC_THERMAL_H_ - -#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c - -/* Enable thermal sensor power management */ -void pch_thermal_configuration(void); - -#endif diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c deleted file mode 100644 index 006f3ae..0000000 --- a/src/soc/intel/skylake/thermal.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/thermal.h> - -#include "chip.h" - -#define MAX_TRIP_TEMP 205 -#define DEFAULT_TRIP_TEMP 50 - -static void *pch_thermal_get_bar(struct device *dev) -{ - uintptr_t bar; - - bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - /* - * Bits [31:12] are the base address as per EDS for Thermal Device, - * Don't care about [11:0] bits - */ - return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); -} - -static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar) -{ - uint8_t pcireg; - - /* Assign Resources to Thermal Device */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for Thermal Device */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - -/* PCH Low Temp Threshold (LTT) */ -static uint16_t pch_get_ltt_value(struct device *dev) -{ - struct soc_intel_skylake_config *config; - uint16_t ltt_value; - uint16_t trip_temp = DEFAULT_TRIP_TEMP; - - config = config_of(dev); - - if (config->pch_trip_temp) - trip_temp = config->pch_trip_temp; - - if (trip_temp > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - /* Trip Point Temp = (LTT / 2 - 50 degree C) */ - ltt_value = (trip_temp + 50) * 2; - - return ltt_value; -} - -/* Enable thermal sensor power management */ -void pch_thermal_configuration(void) -{ - uint16_t reg16; - struct device *dev = PCH_DEV_THERMAL; - if (!dev) { - printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n"); - return; - } - void *thermalbar = pch_thermal_get_bar(dev); - - /* Use default pre-ram bar */ - if (!thermalbar) { - pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS); - thermalbar = (void *)THERMAL_BASE_ADDRESS; - } - - /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT); - reg16 &= ~0x1ff; - /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(dev); - write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Gerrit-Change-Number: 34648 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold...
by Frank Chu (Code Review) 02 Aug '19

02 Aug '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34647 ) Change subject: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time ...................................................................... Patch Set 2: > Patch Set 2: > > Did you verify that you can still communicate with all of the I2C devices? yes -- To view, visit https://review.coreboot.org/c/coreboot/+/34647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Gerrit-Change-Number: 34647 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 02 Aug 2019 02:10:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Clear the GPI IS & IE registers
by David Wu (Code Review) 01 Aug '19

01 Aug '19

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34624 ) Change subject: soc/intel/cannonlake: Clear the GPI IS & IE registers ...................................................................... soc/intel/cannonlake: Clear the GPI IS & IE registers Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34624/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 4e0dba5..fc511db 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -184,6 +184,12 @@ void soc_init_pre_device(void *chip_info) { + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); -- To view, visit https://review.coreboot.org/c/coreboot/+/34624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Gerrit-Change-Number: 34624 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

7 36

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 01 Aug '19

01 Aug '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 15: (4 comments) https://review.coreboot.org/c/coreboot/+/34089/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/13/src/soc/intel/common/bloc… PS13, Line 32: LPSS controllers need to be assigned unique IRQs > What I was referring to is: […] yes. https://review.coreboot.org/c/coreboot/+/34089/13/src/soc/intel/common/bloc… PS13, Line 33: * > Can you please add a debug dump function that prints out the configuration for all devices? And atta […] Ok. Below is the current IRQ config that gets passed for hatch: Interrupt assignment: Dxx:Fx INTx IRQ D18:F0 1 016 D20:F0 1 016 D20:F3 2 017 D20:F5 3 018 D21:F0 1 016 D21:F1 2 017 D21:F3 3 018 D22:F0 1 016 D23:F0 1 016 D25:F0 4 019 D29:F0 1 016 D29:F5 2 017 D30:F0 1 020 D30:F2 2 021 D30:F3 3 022 D31:F3 1 016 D31:F4 2 017 https://review.coreboot.org/c/coreboot/+/34089/13/src/soc/intel/common/bloc… PS13, Line 47: slot != PCI_SLOT(dev->path.pci.devfn) > > Is there even any guarantee that the devicetree provides the devices "in order" ? I could arbitra […] OK Updated the implementation to scan from min to max devfn. https://review.coreboot.org/c/coreboot/+/34089/13/src/soc/intel/common/bloc… PS13, Line 99: index++; > Yes, you have SoC maintain the buffer. […] Ok, I tried moving the buffer to common, But then the contents from the buffer pointer runs null in the SOC and if I pass the same to FSP all IRQs are programmed to 0. I checked the pointer through print the address it same(points to buffer), but then content runs all zeros in SOC. I'll check further on this. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 15 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Aug 2019 15:27:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 01 Aug '19

01 Aug '19

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Arthur Heymans, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34089 to look at the new patch set (#15). Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices Add implementation to fill PCI IRQ table. Each IRQ entry in the table would have information on PCI device number, bus number, irq number and INTx mapping information. This table will be used by FSP as interrupt config to program ITSS PIRx register and also to program interrupt pin for LPSS controllers. Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/irq.h M src/soc/intel/common/block/itss/Kconfig M src/soc/intel/common/block/itss/Makefile.inc A src/soc/intel/common/block/itss/irq.c 4 files changed, 167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34089/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 15 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold...
by Tim Wawrzynczak (Code Review) 01 Aug '19

01 Aug '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34647 ) Change subject: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time ...................................................................... Patch Set 2: Did you verify that you can still communicate with all of the I2C devices? -- To view, visit https://review.coreboot.org/c/coreboot/+/34647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Gerrit-Change-Number: 34647 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Aug 2019 13:59:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold...
by Paul Fagerburg (Code Review) 01 Aug '19

01 Aug '19

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34647 ) Change subject: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Gerrit-Change-Number: 34647 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Aug 2019 13:59:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Fix VBOOT
by Christian Walter (Code Review) 01 Aug '19

01 Aug '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34654 ) Change subject: Fix VBOOT ...................................................................... Fix VBOOT Change-Id: Ie1341ac40086f1ed878f7c86a8963f913adf6bcd Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/security/vboot/Makefile.inc M src/security/vboot/tpm_common.c 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/34654/1 diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 33a9a5e..d554f10 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -89,8 +89,8 @@ romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif -ifneq ($(filter y,$(CONFIG_TPM1) $(CONFIG_TPM2)),) -verstage-y+= tpm_common.c +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c endif romstage-y += vboot_logic.c diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 02fb810..9d4d8f2 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -14,7 +14,6 @@ #include <security/tpm/tspi.h> #include <vb2_api.h> -#include <security/vboot/antirollback.h> #include <security/vboot/tpm_common.h> #define TPM_PCR_GBB_FLAGS_NAME "GBB flags" -- To view, visit https://review.coreboot.org/c/coreboot/+/34654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1341ac40086f1ed878f7c86a8963f913adf6bcd Gerrit-Change-Number: 34654 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold...
by Frank Chu (Code Review) 01 Aug '19

01 Aug '19

Hello Philip Chen, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34647 to look at the new patch set (#2). Change subject: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time ...................................................................... mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/34647/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Gerrit-Change-Number: 34647 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2019