coreboot-gerrit August 2019

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Change in coreboot[master]: intel/i945,gm45,pineview,x4x: Move stage cache support function
by Martin Roth (Code Review) 03 Aug '19

03 Aug '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34670 ) Change subject: intel/i945,gm45,pineview,x4x: Move stage cache support function ...................................................................... intel/i945,gm45,pineview,x4x: Move stage cache support function Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/gm45/ram_calc.c D src/northbridge/intel/gm45/stage_cache.c M src/northbridge/intel/i945/Makefile.inc M src/northbridge/intel/i945/ram_calc.c D src/northbridge/intel/i945/stage_cache.c M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/ram_calc.c D src/northbridge/intel/pineview/stage_cache.c M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/ram_calc.c D src/northbridge/intel/x4x/stage_cache.c 12 files changed, 50 insertions(+), 130 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index e74f475..b59a7c3 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -39,8 +39,4 @@ postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c614082..719c59f 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <program_loading.h> +#include <stage_cache.h> #include <cpu/intel/smm/gen1/smi.h> #include "gm45.h" @@ -123,6 +124,17 @@ return (void *) top_of_ram; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/gm45/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 47014bc..ffeabdc 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -31,8 +31,4 @@ postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - endif diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 525a5b9..dbe74c4 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -25,6 +25,8 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stdint.h> +#include <stage_cache.h> /* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) @@ -88,6 +90,17 @@ return ggc2uma[gms] << 10; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/i945/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 2d16613..8348771 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -30,8 +30,5 @@ romstage-y += early_init.c postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d1b43aa..a3caaf7 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -26,6 +26,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/romstage.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stdint.h> +#include <stage_cache.h> u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -138,6 +140,17 @@ } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/pineview/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index cc0a97d..3118b09 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -30,8 +30,5 @@ ramstage-y += northbridge.c postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index be9c10f..54295a9 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -29,6 +29,7 @@ #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stage_cache.h> /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -134,6 +135,17 @@ return (void *) top_of_ram; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c deleted file mode 100644 index 47f08c1..0000000 --- a/src/northbridge/intel/x4x/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091 Gerrit-Change-Number: 34670 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/baytrail,broadwell: Move stage cache support function
by Kyösti Mälkki (Code Review) 03 Aug '19

03 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34669 ) Change subject: intel/baytrail,broadwell: Move stage cache support function ...................................................................... intel/baytrail,broadwell: Move stage cache support function Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/memmap.c D src/soc/intel/baytrail/stage_cache.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/memmap.c D src/soc/intel/broadwell/stage_cache.c 6 files changed, 30 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/34669/1 diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 3ad6a8f..d966346 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -13,7 +13,6 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += spi.c -romstage-y += stage_cache.c romstage-y += tsc_freq.c postcar-y += iosf.c @@ -45,7 +44,6 @@ ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c -ramstage-y += stage_cache.c ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 211f476..94e91ca 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -14,6 +14,7 @@ */ #include <cbmem.h> +#include <stage_cache.h> #include <soc/iosf.h> #include <soc/smm.h> @@ -26,3 +27,16 @@ { return (void *) smm_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + *base = &smm_base[smm_region_size() - cache_size]; +} diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c deleted file mode 100644 index 4c2a976..0000000 --- a/src/soc/intel/baytrail/stage_cache.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <soc/smm.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; -} diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index a79fa46..91a3da0 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -68,9 +68,6 @@ postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -postcar-y += stage_cache.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 836fda8..7c53fa6 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -15,11 +15,14 @@ #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <cbmem.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <soc/smm.h> +#include <stage_cache.h> +#include <stdint.h> static uintptr_t dpr_region_start(void) { @@ -42,3 +45,15 @@ { return (void *) dpr_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + u32 offset = smm_region_size(); + offset -= CONFIG_IED_REGION_SIZE; + offset -= CONFIG_SMM_RESERVED_SIZE; + + *base = (void *)(cbmem_top() + offset); + *size = CONFIG_SMM_RESERVED_SIZE; +} diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c deleted file mode 100644 index dc59ab7..0000000 --- a/src/soc/intel/broadwell/stage_cache.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <soc/smm.h> -#include <stage_cache.h> -#include <stdint.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; - - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3 Gerrit-Change-Number: 34669 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: intel/haswell: Move stage_cache support function
by Kyösti Mälkki (Code Review) 03 Aug '19

03 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34668 ) Change subject: intel/haswell: Move stage_cache support function ...................................................................... intel/haswell: Move stage_cache support function Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE. Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/smmrelocate.c D src/cpu/intel/haswell/stage_cache.c M src/northbridge/intel/haswell/ram_calc.c 5 files changed, 17 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/34668/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index f960648..d46a422 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -7,12 +7,8 @@ postcar-y += tsc_freq.c ramstage-y += acpi.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - smm-y += finalize.c smm-y += tsc_freq.c diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cd8d5cb..cfd9d45 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -118,15 +118,9 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3948cfe..3a4a0a7 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -250,7 +250,7 @@ params->ied_size = tseg_size - params->smram_size; /* Adjust available SMM handler memory size. */ - params->smram_size -= RESERVED_SMM_SIZE; + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c deleted file mode 100644 index 009cc09..0000000 --- a/src/cpu/intel/haswell/stage_cache.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include "haswell.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); -} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index bdf54d2..3a63afc 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <cbmem.h> +#include <stage_cache.h> #include "haswell.h" static uintptr_t smm_region_start(void) @@ -34,3 +35,16 @@ { return (void *)smm_region_start(); } + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Gerrit-Change-Number: 34668 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold...
by Martin Roth (Code Review) 03 Aug '19

03 Aug '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34647 ) Change subject: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time ...................................................................... mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index cedf046..f97f120 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -29,12 +29,24 @@ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, }, .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/34647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Gerrit-Change-Number: 34647 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/octopus: Add custom SAR values for droid/blorb
by Sheng-Liang Pan (Code Review) 03 Aug '19

03 Aug '19

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34542 ) Change subject: mb/google/octopus: Add custom SAR values for droid/blorb ...................................................................... mb/google/octopus: Add custom SAR values for droid/blorb droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values. BUG=b:138091179 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bobba/Makefile.inc A src/mainboard/google/octopus/variants/bobba/variant.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34542/1 diff --git a/src/mainboard/google/octopus/variants/bobba/Makefile.inc b/src/mainboard/google/octopus/variants/bobba/Makefile.inc index 9fb63f5..ba865e9 100644 --- a/src/mainboard/google/octopus/variants/bobba/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bobba/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c new file mode 100644 index 0000000..f25e2d7 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <sar.h> +#include <baseboard/variants.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + sku_id = get_board_sku(); + + if (sku_id == SKU_UNKNOWN) + return NULL; + + if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || sku_id == 42 || sku_id == 43 || sku_id == 44) + filename = "wifi_sar-droid.hex"; + + return filename; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7 Gerrit-Change-Number: 34542 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: util/nvidia: Change ENODATA to ENOATTR for FreeBSD
by Martin Roth (Code Review) 03 Aug '19

03 Aug '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28365 ) Change subject: util/nvidia: Change ENODATA to ENOATTR for FreeBSD ...................................................................... util/nvidia: Change ENODATA to ENOATTR for FreeBSD FreeBSD doesn't have ENODATA defined, so the cbootimage utility wouldn't build. It looks like the BSDs use ENOATTR in the same fashion, so update the error to use that. Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df Signed-off-by: Martin Roth <martinr(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28365 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/nvidia/Makefile.inc 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/util/nvidia/Makefile.inc b/util/nvidia/Makefile.inc index 133778f..1894fad 100644 --- a/util/nvidia/Makefile.inc +++ b/util/nvidia/Makefile.inc @@ -43,6 +43,10 @@ CBOOTIMAGE_OBJS:=$(addprefix $(objutil)/nvidia/cbootimage/,$(patsubst %.c,%.o,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS)))) CBOOTIMAGE_FLAGS:=-Wall -std=c99 -O2 +ifeq ($(OS_ARCH), FreeBSD) +CBOOTIMAGE_FLAGS:=-DENODATA=ENOATTR +endif + additional-dirs += $(sort $(dir $(CBOOTIMAGE_OBJS))) $(objutil)/nvidia/cbootimage/%.o: util/nvidia/cbootimage/src/%.c -- To view, visit https://review.coreboot.org/c/coreboot/+/28365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df Gerrit-Change-Number: 28365 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: smbios: Make SMBIOS type 3 enclosure type settable at runtime
by Mathew King (Code Review) 03 Aug '19

03 Aug '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34646 ) Change subject: smbios: Make SMBIOS type 3 enclosure type settable at runtime ...................................................................... smbios: Make SMBIOS type 3 enclosure type settable at runtime smbios.h had already declared smbios_mainboard_enclosure_type so this change defines it. It can be overridden in a mainboard so the enclosure type can be set at runtime. BUG=b:138745917 TEST=Built arcada firmware and verified via dmidecode that enclosure type is correctly set to "Convertible", then temporarily added a smbios_mainboard_enclosure_type to arcadas board file returning 0x20 and verified with dmidecode that the enclosure type is "Detachable" Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c --- M src/arch/x86/smbios.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34646/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 2f5c3a6..346e874 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -500,6 +500,11 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } +u8 __weak smbios_mainboard_enclosure_type(void) +{ + return CONFIG_SMBIOS_ENCLOSURE_TYPE; +} + const char *__weak smbios_system_serial_number(void) { return smbios_mainboard_serial_number(); @@ -620,7 +625,7 @@ t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; - t->_type = CONFIG_SMBIOS_ENCLOSURE_TYPE; + t->_type = smbios_mainboard_enclosure_type(); t->security_status = SMBIOS_STATE_SAFE; len = t->length + smbios_string_table_len(t->eos); *current += len; -- To view, visit https://review.coreboot.org/c/coreboot/+/34646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c Gerrit-Change-Number: 34646 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/emulation/qemu-riscv: Add opensbi support
by Martin Roth (Code Review) 03 Aug '19

03 Aug '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34143 ) Change subject: mb/emulation/qemu-riscv: Add opensbi support ...................................................................... mb/emulation/qemu-riscv: Add opensbi support Tested on qemu-riscv: Boots into Linux until initrd should be loaded. Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34143 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/memlayout.ld 2 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index f0f658d..fa6dccc 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -40,6 +40,7 @@ select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM + select RISCV_HAS_OPENSBI config MAINBOARD_DIR string @@ -57,4 +58,26 @@ int default 32768 +config OPENSBI_PLATFORM + string + default "qemu/virt" + +# ugly, but CBFS is placed in DRAM... +config OPENSBI_TEXT_START + hex + default 0x80010000 if COREBOOT_ROMSIZE_KB_64 + default 0x80020000 if COREBOOT_ROMSIZE_KB_128 + default 0x80040000 if COREBOOT_ROMSIZE_KB_256 + default 0x80080000 if COREBOOT_ROMSIZE_KB_512 + default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 + default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 + default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 + default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 2166d23..b29bc14 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -33,6 +33,9 @@ #if ENV_ROMSTAGE ROMSTAGE(STAGES_START, 128K) #endif +#if ENV_RAMSTAGE + REGION(opensbi, STAGES_START, 128K, 4K) +#endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) -- To view, visit https://review.coreboot.org/c/coreboot/+/34143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8 Gerrit-Change-Number: 34143 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: riscv: add support to boot linux kernel binary using opensbi
by Xiang Wang (Code Review) 03 Aug '19

03 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32394 Change subject: riscv: add support to boot linux kernel binary using opensbi ...................................................................... riscv: add support to boot linux kernel binary using opensbi Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/Kconfig M payloads/external/Makefile.inc M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/soc/sifive/fu540/Kconfig 5 files changed, 49 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32394/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a44..4cf9d1e 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -28,6 +28,18 @@ You will be able to specify the location and file name of the payload image later. +config PAYLOAD_RISCV_LINUX_BINARY + bool "An linux binary payload" + depends on ARCH_RISCV + help + Select this option if you have a payload image (an binary file) + which coreboot should run as soon as the basic hardware + initialization is completed. This image will be used as the + payload of opensbi and will be started by coreboot. + + You will be able to specify the location and file name of the + payload image later. + config PAYLOAD_FIT bool "A FIT payload" depends on ARCH_ARM64 @@ -57,9 +69,10 @@ config PAYLOAD_FILE string "Payload path and filename" - depends on PAYLOAD_ELF || PAYLOAD_FIT + depends on PAYLOAD_ELF || PAYLOAD_FIT || PAYLOAD_RISCV_LINUX_BINARY default "payload.elf" if PAYLOAD_ELF default "uImage" if PAYLOAD_FIT + default "payload.bin" if PAYLOAD_RISCV_LINUX_BINARY help The path and filename of the ELF executable file to use as payload. diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5f9d800..3b29b41 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -48,7 +48,11 @@ endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload +ifeq ($(CONFIG_PAYLOAD_RISCV_LINUX_BINARY),y) +$(CONFIG_CBFS_PREFIX)/payload-file := $(obj)/opensbi.elf +else $(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) +endif ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) $(CONFIG_CBFS_PREFIX)/payload-type := flat-binary else diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d5f6295..d4d362b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -174,4 +174,27 @@ endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_RAMSTAGE_RISCV + +ifeq ($(CONFIG_PAYLOAD_RISCV_LINUX_BINARY),y) + +OPENSBI := $(obj)/opensbi.elf +OPENSBI_SOURCE := $(top)/payloads/external/opensbi +OPENSBI_BUILD := $(abspath $(obj)/payloads/external/opensbi) +OPENSBI_TARGET := $(OPENSBI_BUILD)/platform/$(CONFIG_OPENSBI_PLATFORM)/firmware/fw_payload.elf + +$(OPENSBI):$(obj)/build.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + mkdir -p $(OPENSBI_BUILD) + $(MAKE) \ + -C $(OPENSBI_SOURCE) \ + CROSS_COMPILE=riscv64-elf- \ + PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \ + O=$(OPENSBI_BUILD) \ + FW_PAYLOAD_PATH=$(abspath $(CONFIG_PAYLOAD_FILE)) + cp $(OPENSBI_TARGET) $(abspath $@) + +.PHONY: $(OPENSBI) + +endif #CONFIG_PAYLOAD_RISCV_LINUX_BINARY + endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 535067e..9998255 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -49,7 +49,11 @@ fdt = HLS()->fdt; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { +#if CONFIG(PAYLOAD_RISCV_LINUX_BINARY) + run_payload(prog, fdt, RISCV_PAYLOAD_MODE_M); +#else run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); +#endif return; } diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..2e88150 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,8 @@ int default 0 +config OPENSBI_PLATFORM + string + default "sifive/fu540" + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Gerrit-Change-Number: 32394 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: Kconfig: Remove symbol names for choices
by Nico Huber (Code Review) 03 Aug '19

03 Aug '19

Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30569 ) Change subject: Kconfig: Remove symbol names for choices ...................................................................... Abandoned no idea, why there were multiple copies... -- To view, visit https://review.coreboot.org/c/coreboot/+/30569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce3aea93d209d7408e93cc03528c17ca1830a9b Gerrit-Change-Number: 30569 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

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coreboot-gerrit August 2019