coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: string: implement strspn, strcspn, atol
by Patrick Georgi (Code Review) 02 Aug '19

02 Aug '19

Hello Yuji Sasaki, Paul Menzel, build bot (Jenkins), Nitheesh Sekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34450 to look at the new patch set (#5). Change subject: string: implement strspn, strcspn, atol ...................................................................... string: implement strspn, strcspn, atol Change-Id: Id8fa880357124b620bde8884949bd8ffff7d0762 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/include/string.h M src/lib/string.c 2 files changed, 43 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/34450/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/34450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8fa880357124b620bde8884949bd8ffff7d0762 Gerrit-Change-Number: 34450 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yuji Sasaki <sasakiy(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM
by Patrick Georgi (Code Review) 02 Aug '19

02 Aug '19

Hello nsekar(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32271 to review the following change. Change subject: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM ...................................................................... TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM This patch adds support to select the board id based on the TPM availability. Change-Id: Ib75d51a21a6129e3650e2af24ff85f37a462591b Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/boardid.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32271/1 diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c index 8258ac3..9a0d309 100644 --- a/src/mainboard/google/mistral/boardid.c +++ b/src/mainboard/google/mistral/boardid.c @@ -32,7 +32,22 @@ [1] = GPIO(106), [0] = GPIO(105)}; - bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + if (is_tpm_detected() == 0) { + bid = 25; /* Assign 25 for EVB boards */ + printk(BIOS_DEBUG, "EVB Board ID: %d\n", bid); + } else { + bid = 0; /* Assign 0 for Proto boards */ + + /* The board id assigned for Proto boards is 0. + * Since gpios are not wired in the initial phase, + * we will get 0 whihch is a coincidence. + * To make sure it starts working, after gpios are + * wired, reassign the value read from gpios to id. + */ + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_DEBUG, "Proto Board ID: %d\n", bid); + } return bid; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75d51a21a6129e3650e2af24ff85f37a462591b Gerrit-Change-Number: 32271 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold...
by Tim Wawrzynczak (Code Review) 02 Aug '19

02 Aug '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34647 ) Change subject: mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold time ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Gerrit-Change-Number: 34647 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 02 Aug 2019 15:52:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_ops: Make PCI_BDF() available in all stages
by Kyösti Mälkki (Code Review) 02 Aug '19

02 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34614 ) Change subject: device/pci_ops: Make PCI_BDF() available in all stages ...................................................................... device/pci_ops: Make PCI_BDF() available in all stages Caller needs to take into account that bus numbers may have not been assigned yet. Same issue existed before with early ramstage and mostly does not cause problems when used with static devices on bus 0. Change-Id: I4865b4277dbc858c8c2ffd2052defcaa1a92173c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/pci_device.c M src/device/pci_ops.c M src/include/device/pci_ops.h 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/34614/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..5765529 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -630,11 +630,6 @@ pci_write_config16(dev, PCI_COMMAND, command); } -void __noreturn pcidev_die(void) -{ - die("PCI: dev is NULL!\n"); -} - void pci_bus_enable_resources(struct device *dev) { u16 ctrl; diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 9613315..6f42978 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -14,6 +14,7 @@ #define __SIMPLE_DEVICE__ #include <stdint.h> +#include <console/console.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -85,3 +86,8 @@ { return pci_s_find_next_capability(dev, cap, 0); } + +void __noreturn pcidev_die(void) +{ + die("PCI: dev is NULL!\n"); +} diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9a9c575..af5ca08 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -20,25 +20,10 @@ #include <stdint.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_type.h> #include <arch/pci_ops.h> -#ifdef __SIMPLE_DEVICE__ - -/* Avoid name collisions as different stages have different signature - * for these functions. The _s_ stands for simple, fundamental IO or - * MMIO variant. - */ -#define pci_read_config8 pci_s_read_config8 -#define pci_read_config16 pci_s_read_config16 -#define pci_read_config32 pci_s_read_config32 -#define pci_write_config8 pci_s_write_config8 -#define pci_write_config16 pci_s_write_config16 -#define pci_write_config32 pci_s_write_config32 -#else - -#include <device/pci.h> - void __noreturn pcidev_die(void); static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -53,6 +38,20 @@ return pcidev_bdf(dev); } +#ifdef __SIMPLE_DEVICE__ + +/* Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ +#define pci_read_config8 pci_s_read_config8 +#define pci_read_config16 pci_s_read_config16 +#define pci_read_config32 pci_s_read_config32 +#define pci_write_config8 pci_s_write_config8 +#define pci_write_config16 pci_s_write_config16 +#define pci_write_config32 pci_s_write_config32 +#else + static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg) { -- To view, visit https://review.coreboot.org/c/coreboot/+/34614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4865b4277dbc858c8c2ffd2052defcaa1a92173c Gerrit-Change-Number: 34614 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/acpi: Constify struct device instances
by Aamir Bohra (Code Review) 02 Aug '19

02 Aug '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34625 ) Change subject: src/arch/x86/acpi: Constify struct device instances ...................................................................... src/arch/x86/acpi: Constify struct device instances Constify the struct device arguments in below APIs: > acpi_device_name > acpi_device_path_fill > acpi_device_path > acpi_write_dbg2_pci_uart > acpi_device_scope > acpi_device_path_join The APIs does not seem to modify the argument and is using device argument as reference to device only. Change-Id: Ic2ce045f17efa288eb41503795723d0ad5ec78bd Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/arch/x86/acpi.c M src/arch/x86/acpi_device.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/acpi_device.h 4 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/34625/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8ab993e..e4ccd37 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -946,7 +946,7 @@ } unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, - struct device *dev, uint8_t access_size) + const struct device *dev, uint8_t access_size) { acpi_dbg2_header_t *dbg2 = (acpi_dbg2_header_t *)current; struct resource *res; diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 0fb8f3b..47bcc52 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -53,9 +53,9 @@ } /* Locate and return the ACPI name for this device */ -const char *acpi_device_name(struct device *dev) +const char *acpi_device_name(const struct device *dev) { - struct device *pdev = dev; + const struct device *pdev = dev; const char *name = NULL; if (!dev) @@ -82,7 +82,7 @@ } /* Recursive function to find the root device and print a path from there */ -static ssize_t acpi_device_path_fill(struct device *dev, char *buf, +static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, size_t buf_len, size_t cur) { const char *name = acpi_device_name(dev); @@ -117,7 +117,7 @@ * Warning: just as with dev_path() this uses a static buffer * so should not be called mulitple times in one statement */ -const char *acpi_device_path(struct device *dev) +const char *acpi_device_path(const struct device *dev) { static char buf[DEVICE_PATH_MAX] = {}; @@ -131,7 +131,7 @@ } /* Return the path of the parent device as the ACPI Scope for this device */ -const char *acpi_device_scope(struct device *dev) +const char *acpi_device_scope(const struct device *dev) { static char buf[DEVICE_PATH_MAX] = {}; @@ -145,7 +145,7 @@ } /* Concatentate the device path and provided name suffix */ -const char *acpi_device_path_join(struct device *dev, const char *name) +const char *acpi_device_path_join(const struct device *dev, const char *name) { static char buf[DEVICE_PATH_MAX] = {}; ssize_t len; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6251b98..259efcd 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -901,7 +901,7 @@ const char *device_path); unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, - struct device *dev, uint8_t access_size); + const struct device *dev, uint8_t access_size); void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 3569546..d74af9d 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -62,10 +62,10 @@ #define ACPI_DT_NAMESPACE_HID "PRP0001" struct device; -const char *acpi_device_name(struct device *dev); -const char *acpi_device_path(struct device *dev); -const char *acpi_device_scope(struct device *dev); -const char *acpi_device_path_join(struct device *dev, const char *name); +const char *acpi_device_name(const struct device *dev); +const char *acpi_device_path(const struct device *dev); +const char *acpi_device_scope(const struct device *dev); +const char *acpi_device_path_join(const struct device *dev, const char *name); int acpi_device_status(const struct device *dev); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/34625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2ce045f17efa288eb41503795723d0ad5ec78bd Gerrit-Change-Number: 34625 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Fine-tune Kohaku I2C CLK frequency
by Philip Chen (Code Review) 02 Aug '19

02 Aug '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34559 ) Change subject: mb/google/hatch: Fine-tune Kohaku I2C CLK frequency ...................................................................... mb/google/hatch: Fine-tune Kohaku I2C CLK frequency Add rise time / fall time to I2C config in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). BUG=b:138258384 BRANCH=none TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run at 395-399 kHz. Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd Signed-off-by: Philip Chen <philipchen(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34559/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index e463b8b..6fdc0a0 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -29,15 +29,21 @@ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 135, + .fall_time_ns = 45, }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 55, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 100, + .fall_time_ns = 20, }, .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/34559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd Gerrit-Change-Number: 34559 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/i945,gm45,pineview,x4x: Fix stage cache location
by Arthur Heymans (Code Review) 02 Aug '19

02 Aug '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34671 ) Change subject: intel/i945,gm45,pineview,x4x: Fix stage cache location ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7 Gerrit-Change-Number: 34671 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Aug 2019 14:51:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/i945,gm45,pineview,x4x: Move stage cache support function
by Arthur Heymans (Code Review) 02 Aug '19

02 Aug '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34670 ) Change subject: intel/i945,gm45,pineview,x4x: Move stage cache support function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091 Gerrit-Change-Number: 34670 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Aug 2019 14:51:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/up/squared: Make optional settings configurable
by Felix Singer (Code Review) 02 Aug '19

02 Aug '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34642 ) Change subject: mb/up/squared: Make optional settings configurable ...................................................................... mb/up/squared: Make optional settings configurable Change-Id: I6e1deb2d3ef676829034d0b67aa8b72a5f2fd766 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/mainboard/up/squared/Kconfig 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34642/1 diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index b9f5b27..7019b30 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -2,18 +2,26 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select USE_BLOBS - select ADD_FSP_BINARIES - select FSP_USE_REPO select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 - select ONBOARD_VGA_IS_PRIMARY select MAINBOARD_HAS_LIBGFXINIT +config USE_BLOBS + bool + default y + +config ADD_FSP_BINARIES + bool + default y + +config FSP_USE_REPO + bool + default y + config VBOOT select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN @@ -65,6 +73,10 @@ int default 2 +config ONBOARD_VGA_IS_PRIMARY + bool + default y + config LINUX_COMMAND_LINE string default "console=ttyS4,115200 earlyprintk=ttyS4,115200,keep" if PAYLOAD_LINUXBOOT && UART_FOR_CONSOLE=0 -- To view, visit https://review.coreboot.org/c/coreboot/+/34642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e1deb2d3ef676829034d0b67aa8b72a5f2fd766 Gerrit-Change-Number: 34642 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/cavium/bdk/libbdk-hal: Fix eye data memory leak
by Jacob Garber (Code Review) 02 Aug '19

02 Aug '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34591 ) Change subject: vc/cavium/bdk/libbdk-hal: Fix eye data memory leak ...................................................................... vc/cavium/bdk/libbdk-hal: Fix eye data memory leak This function can capture and allocate its own eye data, so in that case set need_free to true so it is freed at the end. Change-Id: I63ca6d743e6610d3e3ab6bd7b0356aabdfa6f784 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1393969 --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34591/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index f7d631f..5416b73 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -362,9 +362,12 @@ bdk_error("Failed to allocate space for eye\n"); return -1; } - if (bdk_qlm_eye_capture(node, qlm, qlm_lane, eye_data)) - return -1; + if (bdk_qlm_eye_capture(node, qlm, qlm_lane, eye_data)) { + free(eye_data); + return -1; + } eye = eye_data; + need_free = 1; } /* Calculate the max eye width */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63ca6d743e6610d3e3ab6bd7b0356aabdfa6f784 Gerrit-Change-Number: 34591 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019