coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/lenovo/t400: Add VBT file
by Arthur Heymans (Code Review) 21 May '19

21 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32884 Change subject: mb/lenovo/t400: Add VBT file ...................................................................... mb/lenovo/t400: Add VBT file All variants (t400, r400, t500, w500) use the same OPROM for the IGD. Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/Kconfig A src/mainboard/lenovo/t400/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32884/1 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9f94051..16f1680 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -25,6 +25,7 @@ select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/data.vbt b/src/mainboard/lenovo/t400/data.vbt new file mode 100644 index 0000000..e9bfaaf --- /dev/null +++ b/src/mainboard/lenovo/t400/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/32884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02 Gerrit-Change-Number: 32884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/intel/fsp2_0: Fix logical 'and' of equal expressions
by HAOUAS Elyes (Code Review) 21 May '19

21 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32886 Change subject: src/drivers/intel/fsp2_0: Fix logical 'and' of equal expressions ...................................................................... src/drivers/intel/fsp2_0: Fix logical 'and' of equal expressions Probably a copy/past issue. Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp2_0/hand_off_block.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32886/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 5efd590..c5c78ca 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -237,9 +237,9 @@ /* Don't show ingredient name and version if its all 0xFF */ if (fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && + fvi[index].Version.MinorVersion == 0xFF && + fvi[index].Version.Revision == 0xFF && + fvi[index].Version.BuildNumber == 0xFF && fvi[index].VersionStringIndex == 0) { str_ptr = (char *)((uintptr_t)str_ptr + cnt + sizeof(uint8_t)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76 Gerrit-Change-Number: 32886 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by mikeb mikeb (Code Review) 21 May '19

21 May '19

mikeb mikeb has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Abandoned Huge Thanks to Martin Roth, the patches with new AMD microcodes have been merged - so these scripts for installing them are not needed now. -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 12 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: SDM845: USB: Add Super speed mode support on cheza
by Julius Werner (Code Review) 21 May '19

21 May '19

Julius Werner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29200 ) Change subject: SDM845: USB: Add Super speed mode support on cheza ...................................................................... Abandoned Merged into CB:25213 -- To view, visit https://review.coreboot.org/c/coreboot/+/29200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib051138350f95cadcd1f1cd66c074ad77801ed1f Gerrit-Change-Number: 29200 Gerrit-PatchSet: 15 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Ciluveru chandana kishori <cchiluve(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Chandana Kishori Chiluveru <cchiluve(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Paul Menzel (Code Review) 20 May '19

20 May '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... Patch Set 8: Thank you Stefan and Patrick. -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 8 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 20 May 2019 18:55:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [Test] Remaining unused variables
by HAOUAS Elyes (Code Review) 20 May '19

20 May '19

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#25). Change subject: [Test] Remaining unused variables ...................................................................... [Test] Remaining unused variables Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch R util/crossgcc/patches/gcc-9.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-9.1.0_gnat.patch R util/crossgcc/patches/gcc-9.1.0_libgcc.patch D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum A util/crossgcc/sum/gcc-9.1.0.tar.xz.cksum 8 files changed, 5 insertions(+), 21,023 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 25 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Pass more SPI options to FSP.
by Tim Wawrzynczak (Code Review) 20 May '19

20 May '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32791 Change subject: soc/intel/cannonlake: Pass more SPI options to FSP. ...................................................................... soc/intel/cannonlake: Pass more SPI options to FSP. Add the ability for the device tree to set CsEnable, CsPolarity, and DefaultCsOutput parameters to the FSP. BUG=b:130329260 BRANCh=none TEST=Compiles. Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/serialio.h 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32791/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2b2a51f..c3f3023 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -338,6 +338,17 @@ */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + /* 0 = Active low CS, 1 = Active high CS */ + uint8_t SerialIoSpi0CsPolarity[2]; + uint8_t SerialIoSpi1CsPolarity[2]; + uint8_t SerialIoSpi2CsPolarity[2]; + /* 0 = GPIO, 1 = Chip select */ + uint8_t SerialIoSpi0CsEnable[2]; + uint8_t SerialIoSpi1CsEnable[2]; + uint8_t SerialIoSpi2CsEnable[2]; + /* Default CS as output; 0 = CS0, 1 = CS1 */ + uint8_t SerialIoSpiDefaultCsOutput[3]; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..dd5e2c4 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -86,6 +86,20 @@ params->SerialIoUartMode[i] = get_param_value(config, dev_offset); } + + for (i = 0; i < 2; i++) { + params->SerialIoSpi0CsPolarity[i] = + config->SerialIoSpi0CsPolarity[i]; + params->SerialIoSpi1CsPolarity[i] = + config->SerialIoSpi1CsPolarity[i]; + params->SerialIoSpi2CsPolarity[i] = + config->SerialIoSpi2CsPolarity[i]; + } + + for (i = 0; i < 3; i++) { + params->SerialIoSpiDefaultCsOutput[i] = + config->SerialIoSpiDefaultCsOutput[i]; + } } #else static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index c92bd2d..5ce4a80 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -54,4 +54,19 @@ PchSerialIoIndexMAX } PCH_SERIAL_IO_CONTROLLER; +typedef enum { + PchSerialIoCsActiveLow, + PchSerialIoCsActiveHigh, +} PCH_SPI_CS_ACTIVE_MODE; + +typedef enum { + PchSerialIoCsGpio, + PchSerialIoCsEnable, +} PCH_SPI_CS_ENABLE_MODE; + +typedef enum { + PchSerialIoCS0, + PchSerialIoCS1, +} PCH_SPI_CS_SELECT; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c Gerrit-Change-Number: 32791 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F...
by Martin Roth (Code Review) 20 May '19

20 May '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28273 ) Change subject: src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 ...................................................................... src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x600110F [2012-01-11] replaced by New version: 0x600111F [2018-03-05] Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28273 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: <awokd(a)danwin1210.me> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h D src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c A src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc 4 files changed, 408 insertions(+), 2,676 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved mikeb mikeb: Looks good to me, but someone else must approve awokd(a)danwin1210.me: Looks good to me, but someone else must approve diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h index f0d9194..bd00756 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h @@ -808,9 +808,9 @@ #define F15_TN_UCODE_0E #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc []; + extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc []; #undef F15_TN_UCODE_10F - #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600110F_Enc, + #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc, #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c deleted file mode 100644 index 80e60f6..0000000 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Tn Microcode patch. - * - * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/TN - * @e \$Revision: 64060 $ @e \$Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0600110F for 6101 and equivalent - -CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] = -{ - 0x12, - 0x20, - 0x11, - 0x01, - 0x0f, - 0x11, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x61, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0xd4, - 0x3d, - 0x97, - 0xf0, - 0xd2, - 0x1a, - 0xcf, - 0x44, - 0x1d, - 0x45, - 0x82, - 0x13, - 0xec, - 0xcd, - 0x52, - 0x24, - 0x2d, - 0x26, - 0x73, - 0x9f, - 0x0e, - 0x38, - 0x80, - 0x5b, - 0x02, - 0x6a, - 0xd3, - 0x80, - 0x97, - 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0x93, - 0xdd, - 0x16, - 0xed, - 0x8e, - 0x27, - 0x66, - 0x4d, - 0x59, - 0xf0, - 0x27, - 0x1b, - 0x37, - 0xa0, - 0x25, - 0x9a, - 0x62, - 0xb4, - 0x6f, - 0xbd, - 0x83, - 0x28, - 0x0b, - 0x26, - 0xa9, - 0x07, - 0xac, - 0xb5, - 0x91, - 0x93, - 0x91, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c new file mode 100644 index 0000000..71fb1df --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c @@ -0,0 +1,405 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F15Tn Microcode patch. + * + * F15Tn Microcode Patch rev 0600111F for 6101/6131 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 334098 $ @e \$Date: 2018-03-05 14:21:15 -0600 (Mon, 05 Mar 2018) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +// Encrypt Patch code 0600111F for 6101/6131 and equivalent + +CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc [IDS_PAD_4K] = +{ + 0x18, 0x20, 0x05, 0x03, 0x1f, 0x11, 0x00, 0x06, + 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xd0, 0xb7, 0x58, 0x1c, 0xca, 0xa2, 0xf2, 0x52, + 0x72, 0xa4, 0xe1, 0x1b, 0x37, 0xe0, 0x9f, 0xb3, + 0x58, 0xf4, 0x76, 0x85, 0x1a, 0x83, 0x4a, 0x89, + 0x78, 0x82, 0x4e, 0xf3, 0xa1, 0x6a, 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0xfb, 0x1b, + 0xe8, 0x4d, 0x49, 0x97, 0x23, 0xeb, 0x51, 0x38, + 0x9a, 0x22, 0xa7, 0xc0, 0xcf, 0x25, 0x3a, 0x4e, + 0x50, 0x0d, 0xff, 0x8e, 0xb5, 0x91, 0xd3, 0x85, + 0x54, 0xe9, 0x1f, 0x70, 0xea, 0x64, 0x6a, 0x77, + 0xbe, 0xd2, 0x15, 0xce, 0x9c, 0xb0, 0x70, 0x61, + 0x8b, 0x58, 0xdb, 0x9f, 0x0a, 0xe4, 0x80, 0xb3, + 0x21, 0x44, 0x0b, 0xea, 0x43, 0xab, 0x0d, 0xf0, + 0x7e, 0xbc, 0xd5, 0xde, 0x29, 0x12, 0xcd, 0xde, + 0xd9, 0xf3, 0xf3, 0x0e, 0xf4, 0xb8, 0x3d, 0xd7, + 0x4e, 0x24, 0xcf, 0x9b, 0x4b, 0xad, 0x96, 0x1e, + 0xca, 0x6d, 0x3f, 0x9c, 0xe4, 0xb8, 0x8b, 0xf5, + 0x3a, 0x43, 0xb0, 0xce, 0x16, 0x27, 0x87, 0xe3, + 0x1b, 0x54, 0xd0, 0xed, 0x3c, 0xe2, 0xb0, 0x1f, + 0x24, 0xa3, 0x6d, 0x31, 0x00, 0x7d, 0x58, 0x69, + 0xc9, 0xc6, 0x50, 0xc8, 0x87, 0xac, 0x45, 0x54, + 0x66, 0x06, 0x7f, 0xc3, 0x51, 0xb8, 0xdf, 0x51 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc index 7d52cb6..e4b0424 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc @@ -4,7 +4,7 @@ libagesa-y += F15TnInitEarlyTable.c libagesa-y += F15TnIoCstate.c libagesa-y += F15TnLogicalIdTables.c -libagesa-y += F15TnMicrocodePatch0600110F_Enc.c +libagesa-y += F15TnMicrocodePatch0600111F_Enc.c libagesa-y += F15TnMicrocodePatchTables.c libagesa-y += F15TnMsrTables.c libagesa-y += F15TnPciTables.c -- To view, visit https://review.coreboot.org/c/coreboot/+/28273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961 Gerrit-Change-Number: 28273 Gerrit-PatchSet: 6 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110...
by Martin Roth (Code Review) 20 May '19

20 May '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28370 ) Change subject: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 ...................................................................... src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 This microcode update for CPU ID 0x700F01 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x700010B [2013-07-09] replaced by New version: 0x7000110 [2018-02-09] Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28370 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c 1 file changed, 437 insertions(+), 3,462 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c index 61876b8..a0a20eb 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c @@ -4,16 +4,16 @@ * * AMD F16Kb Microcode patch. * - * F16Kb Microcode Patch rev 0700010B for 7001 or equivalent. + * F16Kb Microcode Patch rev 07000110 for 7001 or equivalent. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 267923 $ @e \$Date: 2013-07-15 16:49:48 -0400 (Mon, 15 Jul 2013) $ + * @e \$Revision: 334098 $ @e \$Date: 2018-02-09 14:21:15 -0400 (Fri, 09 Feb 2018) $ */ /***************************************************************************** * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -64,3468 +64,443 @@ */ -// Encrypt Patch code 0700010B for 7001 and equivalent +// Encrypt Patch code 07000110 for 7001 and equivalent CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] = { - 0x13, - 0x20, - 0x09, - 0x07, - 0x0b, - 0x01, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x70, - 0x00, - 0x00, - 0x00, - 0xaa, - 0xaa, - 0xaa, - 0x1c, - 0x8a, - 0x19, - 0x02, - 0x24, - 0xb6, - 0x41, - 0xb0, - 0x60, - 0x6a, - 0x6e, - 0xc3, - 0xdb, - 0xae, - 0xd9, - 0xa3, - 0x9e, - 0x4c, - 0x89, - 0xd2, - 0xe6, - 0xb8, - 0xb1, - 0x81, - 0x30, - 0xbd, - 0x57, - 0x94, - 0x81, - 0xa3, - 0xbc, - 0x81, - 0x95, - 0x47, - 0xb5, - 0x93, - 0x5f, - 0x8a, - 0xf6, - 0x82, - 0xcd, - 0x0e, - 0x4d, - 0xd3, - 0x26, - 0xd8, - 0xa8, - 0x35, - 0xb7, - 0x64, - 0xba, - 0x32, - 0x33, - 0x09, - 0xfd, - 0x93, - 0xc6, - 0x49, - 0x19, - 0xe3, - 0x53, - 0xc1, - 0xb5, - 0xcc, - 0x2f, - 0xf3, - 0x52, - 0xaa, - 0xe3, - 0x9c, - 0x79, - 0x52, - 0x10, - 0x5f, - 0xff, - 0x90, - 0x29, - 0x0b, - 0xf1, - 0x7f, - 0xfa, - 0x0c, - 0x10, - 0x75, - 0x84, - 0x74, - 0x81, - 0x8b, - 0x63, - 0xb3, - 0x71, - 0x20, - 0x25, - 0xc8, - 0x16, - 0x6d, - 0xc2, - 0xcc, - 0xf7, - 0x78, - 0x30, - 0xb6, - 0x2d, - 0x81, - 0x2b, - 0xdd, - 0xc4, - 0x6b, - 0xab, - 0x31, - 0x90, - 0xa8, - 0x6d, - 0xd7, - 0x6c, - 0xae, - 0x66, - 0xe5, - 0xdf, - 0xd6, - 0x65, - 0xd4, - 0x95, - 0xe5, - 0x68, - 0xae, - 0x26, - 0xa5, - 0x48, - 0xe6, - 0xf5, - 0xf3, - 0x22, - 0x67, - 0xb9, - 0x4d, - 0x22, - 0x38, - 0x32, - 0x51, - 0x4b, - 0x8a, - 0x6b, - 0xc1, - 0x9c, - 0xd2, - 0xc3, - 0x91, - 0xb5, - 0x43, - 0xe9, - 0xcc, - 0x73, - 0x49, - 0x07, - 0x7c, - 0x7d, - 0xe8, - 0xc8, - 0x5e, - 0x56, - 0x7a, - 0x22, - 0x80, - 0xcc, - 0xbd, - 0x21, - 0x1b, - 0x32, - 0x0d, - 0xd4, - 0x92, - 0x62, - 0x37, - 0xaf, - 0xf6, - 0x18, - 0xfa, - 0x9f, - 0x9f, - 0x12, - 0x6b, - 0x4b, - 0x4f, - 0x1d, - 0x5a, - 0xca, - 0x3c, - 0x7d, - 0x7d, - 0x38, - 0x66, - 0x00, - 0x90, - 0xc5, - 0x7e, - 0x44, - 0xf3, - 0xa8, - 0x65, - 0xc3, - 0x1b, - 0x41, - 0x1d, - 0xef, - 0xb3, - 0xd4, - 0x43, - 0xb5, - 0x02, - 0x1a, - 0x0d, - 0x08, - 0x44, - 0xa5, - 0x57, - 0xa7, - 0x65, - 0x90, - 0xdc, - 0xdc, - 0x1e, - 0xdf, - 0x45, - 0x5f, - 0x88, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 }; /*---------------------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/28370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Gerrit-Change-Number: 28370 Gerrit-PatchSet: 6 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110...
by Martin Roth (Code Review) 20 May '19

20 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28370 ) Change subject: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Gerrit-Change-Number: 28370 Gerrit-PatchSet: 5 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Mon, 20 May 2019 15:14:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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