coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F...
by Martin Roth (Code Review) 20 May '19

20 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28273 ) Change subject: src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 ...................................................................... Patch Set 5: Code-Review+2 AMD has given authorization to merge this. -- To view, visit https://review.coreboot.org/c/coreboot/+/28273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961 Gerrit-Change-Number: 28273 Gerrit-PatchSet: 5 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Mon, 20 May 2019 15:14:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110...
by Martin Roth (Code Review) 20 May '19

20 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28370 ) Change subject: src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 ...................................................................... Patch Set 5: AMD has given authorization to merge this. -- To view, visit https://review.coreboot.org/c/coreboot/+/28370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Gerrit-Change-Number: 28370 Gerrit-PatchSet: 5 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 20 May 2019 15:14:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM confi...
by Subrata Banik (Code Review) 20 May '19

20 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32848 Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ...................................................................... mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration sarien/arcada: GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating hatch: GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32848/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 09e004e..9d10cac 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,6 +89,16 @@ register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b6377ba..d3848a2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -201,6 +201,16 @@ register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 3807047..c96423c 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -205,6 +205,16 @@ register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/32848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Gerrit-Change-Number: 32848 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/dragonegg: Override FSP default GPIO PM configuration
by Subrata Banik (Code Review) 20 May '19

20 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32847 Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ...................................................................... mb/google/dragonegg: Override FSP default GPIO PM configuration GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32847/1 diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..f820924 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -167,6 +167,16 @@ }, }" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/32847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Gerrit-Change-Number: 32847 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot
by Subrata Banik (Code Review) 20 May '19

20 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32790 Change subject: soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot ...................................................................... soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot This patch ensures to override FSP default gpio pm programming based on platform need. BUG=b:130764684 TEST=Able to build and boot from fixed media on ICL and CML. Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/icelake/chip.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 1bd34c3..f64aa17 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -176,6 +176,9 @@ /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); + + /* Overriding FSP default GPIO PM programming. */ + gpio_pm_configure(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 11d14de..73f003c 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -117,6 +117,9 @@ /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + /* Overriding FSP default GPIO PM programming. */ + gpio_pm_configure(); } static void pci_domain_set_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/32790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Gerrit-Change-Number: 32790 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Enable SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING if !SOC_INTEL_SKY...
by Subrata Banik (Code Review) 20 May '19

20 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32789 Change subject: Enable SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING if !SOC_INTEL_SKYLAKE ...................................................................... Enable SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING if !SOC_INTEL_SKYLAKE Additional gpio pm programming logic has been added since CNP PCH hence selecting this feature for all PCH family beyond SPT PCH. BUG=b:130764684 TEST=Able to build and boot ICL and CML. Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/pch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32789/1 diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index a832742..0c654bc 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -44,5 +44,6 @@ select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING if !SOC_INTEL_SKYLAKE endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1 Gerrit-Change-Number: 32789 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/block/gpio: Add gpio_pm_configure() function
by Subrata Banik (Code Review) 20 May '19

20 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32788 Change subject: soc/intel/common/block/gpio: Add gpio_pm_configure() function ...................................................................... soc/intel/common/block/gpio: Add gpio_pm_configure() function This patch adds new function to perform gpio power management programming as per EDS. Logic is to enable gpio pm registers as GPDLCGEN, GPDPCGEN, GPRTCDLCGEN, GPRCOMPCDLCGEN if !CONFIG_SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING and GPSIDEDPCGEN for GPIO communities. BUG=b:130764684 TEST=Able to build and boot from fixed media on ICL and CML. Change-Id: I816a70ad92595f013740a235a9799912ad51665e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32788/1 diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index bdbc323..30e61d4 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -43,3 +43,8 @@ depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n + +config SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING + depends on SOC_INTEL_COMMON_BLOCK_GPIO + bool + default n diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 3a0594c..7fdf084 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -57,6 +57,11 @@ #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) #define MISCCFG_GPE0_DW2_SHIFT 16 #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) +#define MISCCFG_GPSIDEDPCGEN 0x20 +#define MISCCFG_GPRCOMPCDLCGEN 0x10 +#define MISCCFG_GPRTCDLCGEN 0x8 +#define MISCCFG_GPDPCGEN 0x2 +#define MISCCFG_GPDLCGEN 0x1 #define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \ ((group) * sizeof(uint32_t))) @@ -609,3 +614,36 @@ } } } + +/* + * The function performs GPIO Power Management programming. + * + * Enable GPDLCGEN, GPDPCGEN, GPRTCDLCGEN, + * GPRCOMPCDLCGEN if !CONFIG_SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING and + * GPSIDEDPCGEN for GPIO communities. + */ +void gpio_pm_configure(void) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + size_t gpio_communities; + const struct pad_community *comm; + + if (CONFIG(SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING)) + misccfg_mask = ~MISCCFG_GPRCOMPCDLCGEN; + else + misccfg_mask = ~0; + + if (!CONFIG(SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING)) + misccfg_value = MISCCFG_GPRCOMPCDLCGEN; + + misccfg_value |= (MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | + MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN); + + comm = soc_gpio_get_community(&gpio_communities); + /* Program GPIO_MISCCFG */ + for (i = 0; i < gpio_communities; i++, comm++) + pcr_rmw32(comm->port, GPIO_MISCCFG, + misccfg_mask, misccfg_value); +} diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 4179293..1630e5d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -215,5 +215,14 @@ */ void gpi_clear_int_cfg(void); +/* + * The function performs GPIO Power Management programming. + * + * Enable GPDLCGEN, GPDPCGEN, GPRTCDLCGEN, + * GPRCOMPCDLCGEN if !CONFIG_SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING and + * GPSIDEDPCGEN for GPIO communities. + */ +void gpio_pm_configure(void); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816a70ad92595f013740a235a9799912ad51665e Gerrit-Change-Number: 32788 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco: Add support for KB_ERR_CODE to Wilco EC
by Keith Short (Code Review) 20 May '19

20 May '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32776 Change subject: ec/google/wilco: Add support for KB_ERR_CODE to Wilco EC ...................................................................... ec/google/wilco: Add support for KB_ERR_CODE to Wilco EC Adds support for the KB_ERR_CODE command on the Wilco EC. This command is used to drive diagnostic LEDs on the platform after a failed boot. This change also adds the Wilco EC mailbox command support to bootblock and verstage so that those stages can use the KB_ERR_CODE command. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/ec/google/wilco/Makefile.inc M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h 3 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32776/1 diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index 3a7790c..f17869e 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) -bootblock-y += bootblock.c +bootblock-y += bootblock.c commands.c mailbox.c +verstage-y += commands.c mailbox.c romstage-y += commands.c mailbox.c romstage.c boardid.c ramstage-y += chip.c commands.c mailbox.c boardid.c smm-y += commands.c mailbox.c smihandler.c boardid.c diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index d0d572d..a97a28e 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -181,3 +181,9 @@ CONFIG_EC_BASE_ACPI_DATA); return !!ec_read(EC_RAM_SIGNED_FW); } + +int wilco_ec_err_code(enum ec_err_code err_code) +{ + return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE, + &err_code, 1, NULL, 0); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 3077eee..fafb7fd 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -50,6 +50,8 @@ KB_SLP_EN = 0x64, /* Inform the EC about BIOS boot progress */ KB_BIOS_PROGRESS = 0xc2, + /* Inform the EC that a fatal error occurred */ + KB_ERR_CODE = 0x7b, }; enum ec_ram_addr { @@ -86,6 +88,12 @@ CAMERA_OFF }; +enum ec_err_code { + DLED_MEMORY = 0x03, + DLED_PANEL = 0x10, + DLED_ROM = 0x19, +}; + /** * wilco_ec_radio_control() - Control wireless radios. * @ec_radio: Wireless radio type. @@ -310,4 +318,17 @@ */ int wilco_ec_signed_fw(void); +/** + * wilco_ec_err_code + * + * Send an error code to the EC to indicate a failed boot. The EC flashes the + * platform LED amber and white to provide user indication of the failure type. + * + * @err_code: Error code to send to the EC + * + * Returns 0 if EC command was successful + * Returns -1 if EC command failed + */ +int wilco_ec_err_code(enum ec_err_code err_code); + #endif /* EC_GOOGLE_WILCO_COMMANDS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3 Gerrit-Change-Number: 32776 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: i945: Add device identification D2:F1
by HAOUAS Elyes (Code Review) 20 May '19

20 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32877 Change subject: i945: Add device identification D2:F1 ...................................................................... i945: Add device identification D2:F1 Add device identification D2:F1 for desktop version. (see Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family datasheet page 192) Change-Id: Ie060644d635a7031ee6f55420d63751192481091 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/gma.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32877/1 diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9c4f410..1d20533 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -858,6 +858,7 @@ }; static const unsigned short i945_gma_func1_ids[] = { + 0x2776, /* Desktop 82945G/GZ/GC */ 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */ 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie060644d635a7031ee6f55420d63751192481091 Gerrit-Change-Number: 32877 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util: Fix typo on plural form of index
by HAOUAS Elyes (Code Review) 20 May '19

20 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32855 Change subject: util: Fix typo on plural form of index ...................................................................... util: Fix typo on plural form of index Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/romcc/romcc.c M util/romcc/tests/linux_test5.c M util/romcc/tests/raminit_test6.c M util/romcc/tests/raminit_test7.c M util/romcc/tests/simple_test46.c M util/romcc/tests/simple_test54.c M util/x86/x86_page_tables.go 7 files changed, 35 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32855/1 diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 43be171..c6507dc 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -14111,9 +14111,9 @@ struct block *block; struct triple *old_result, *first, *ins; size_t count, idx; - unsigned long used_indicies; + unsigned long used_indices; int i, max_index; -#define MAX_INDICIES (sizeof(used_indicies)*CHAR_BIT) +#define MAX_INDICES (sizeof(used_indices)*CHAR_BIT) #define ID_BITS(X) ((X) & (TRIPLE_FLAG_LOCAL -1)) struct { unsigned id; @@ -14183,7 +14183,7 @@ * * To gurantee that stability I lookup the variables * to see where they have been used before and - * I build my final list with the assigned indicies. + * I build my final list with the assigned indices. */ vars = 0; if (enclose_triple(old_result)) { @@ -14202,8 +14202,8 @@ ordered_triple_set(&vars, set->member); } - /* Lookup the current indicies of the live varialbe */ - used_indicies = 0; + /* Lookup the current indices of the live varialbe */ + used_indices = 0; max_index = -1; for(set = vars; set ; set = set->next) { struct triple *ins; @@ -14214,14 +14214,14 @@ if (index < 0) { continue; } - if (index >= MAX_INDICIES) { + if (index >= MAX_INDICES) { internal_error(state, ins, "index unexpectedly large"); } - if (used_indicies & (1 << index)) { + if (used_indices & (1 << index)) { internal_error(state, ins, "index previously used?"); } - /* Remember which indicies have been used */ - used_indicies |= (1 << index); + /* Remember which indices have been used */ + used_indices |= (1 << index); if (index > max_index) { max_index = index; } @@ -14239,31 +14239,31 @@ continue; } /* Find the lowest unused index value */ - for(index = 0; index < MAX_INDICIES; index++) { - if (!(used_indicies & ((uint64_t)1 << index))) { + for(index = 0; index < MAX_INDICES; index++) { + if (!(used_indices & ((uint64_t)1 << index))) { break; } } - if (index == MAX_INDICIES) { - internal_error(state, ins, "no free indicies?"); + if (index == MAX_INDICES) { + internal_error(state, ins, "no free indices?"); } info[ID_BITS(ins->id)].index = index; - /* Remember which indicies have been used */ - used_indicies |= (1 << index); + /* Remember which indices have been used */ + used_indices |= (1 << index); if (index > max_index) { max_index = index; } } /* Build the return list of variables with positions matching - * their indicies. + * their indices. */ *enclose = 0; last_var = enclose; for(i = 0; i <= max_index; i++) { struct triple *var; var = 0; - if (used_indicies & (1 << i)) { + if (used_indices & (1 << i)) { for(set = vars; set; set = set->next) { int index; index = info[ID_BITS(set->member->id)].index; diff --git a/util/romcc/tests/linux_test5.c b/util/romcc/tests/linux_test5.c index cf0df46..e94d5d7 100644 --- a/util/romcc/tests/linux_test5.c +++ b/util/romcc/tests/linux_test5.c @@ -156,7 +156,7 @@ unsigned device; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -224,7 +224,7 @@ continue; } debug('D'); - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); if (value < 0) continue; debug('E'); @@ -310,7 +310,7 @@ } /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); /* All is good if the selected clock speed * is what I need or slower. diff --git a/util/romcc/tests/raminit_test6.c b/util/romcc/tests/raminit_test6.c index e99e355..8048dce 100644 --- a/util/romcc/tests/raminit_test6.c +++ b/util/romcc/tests/raminit_test6.c @@ -1621,7 +1621,7 @@ unsigned min_cycle_time, min_latency; int i; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [0 ] = 0x50, [1 ] = 0x60, @@ -1651,7 +1651,7 @@ (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value < 0) { continue; } @@ -1701,7 +1701,7 @@ } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value <= min_cycle_time) { diff --git a/util/romcc/tests/raminit_test7.c b/util/romcc/tests/raminit_test7.c index 184e912..c768e86 100644 --- a/util/romcc/tests/raminit_test7.c +++ b/util/romcc/tests/raminit_test7.c @@ -1626,7 +1626,7 @@ unsigned min_cycle_time, min_latency; int i; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [0 ] = 0x50, [1 ] = 0x60, @@ -1656,7 +1656,7 @@ (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value < 0) { continue; } @@ -1706,7 +1706,7 @@ } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value <= min_cycle_time) { diff --git a/util/romcc/tests/simple_test46.c b/util/romcc/tests/simple_test46.c index 0b83125..2d3764e4 100644 --- a/util/romcc/tests/simple_test46.c +++ b/util/romcc/tests/simple_test46.c @@ -1,6 +1,6 @@ static void spd_set_memclk(void) { - static const int indicies[] = { 26, 23, 9 }; + static const int indices[] = { 26, 23, 9 }; int new_cycle_time, new_latency; int index; unsigned min_cycle_time, min_latency; @@ -15,7 +15,7 @@ for(index = 0; index < 3; index++) { unsigned long loops; unsigned long address; - address = indicies[index]; + address = indices[index]; loops = 1000000; do { } while(--loops); diff --git a/util/romcc/tests/simple_test54.c b/util/romcc/tests/simple_test54.c index 37dce79..b7dee66 100644 --- a/util/romcc/tests/simple_test54.c +++ b/util/romcc/tests/simple_test54.c @@ -569,7 +569,7 @@ unsigned device; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -637,7 +637,7 @@ continue; } debug('D'); - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); if (value < 0) continue; debug('E'); @@ -723,7 +723,7 @@ } /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); /* All is good if the selected clock speed * is what I need or slower. diff --git a/util/x86/x86_page_tables.go b/util/x86/x86_page_tables.go index 2dc0ed3..e477b54 100644 --- a/util/x86/x86_page_tables.go +++ b/util/x86/x86_page_tables.go @@ -223,7 +223,7 @@ return nil } -// This map represents what the IA32_PAT MSR should be at runtime. The indicies +// This map represents what the IA32_PAT MSR should be at runtime. The indices // are what the linux kernel uses. Reserved entries are not used. // 0 WB : _PAGE_CACHE_MODE_WB // 1 WC : _PAGE_CACHE_MODE_WC @@ -523,11 +523,11 @@ return as } -func (as *addressSpace) deleteEntries(indicies []int) { +func (as *addressSpace) deleteEntries(indices []int) { // deletions need to be processed in reverse order so as not // delete the wrong entries - sort.Sort(sort.Reverse(sort.IntSlice(indicies))) - for _, i := range indicies { + sort.Sort(sort.Reverse(sort.IntSlice(indices))) + for _, i := range indices { as.ranges = append(as.ranges[:i], as.ranges[i+1:]...) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5 Gerrit-Change-Number: 32855 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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