coreboot-gerrit May 2019

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Change in ...coreboot[master]: console: Add new function die_with_post_code()
by Patrick Georgi (Code Review) 20 May '19

20 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32838 ) Change subject: console: Add new function die_with_post_code() ...................................................................... console: Add new function die_with_post_code() Add a new helper function die_with_post_code() that generates a post code and an error string prior to halting the CPU. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Signed-off-by: Keith Short <keithshort(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32838 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/console/die.c M src/include/console/console.h 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved diff --git a/src/console/die.c b/src/console/die.c index 769e651..513d1c4 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -36,4 +36,11 @@ die_notify(); halt(); } + +/* Report a fatal error with a post code */ +void __noreturn die_with_post_code(uint8_t value, const char *msg) +{ + post_code(value); + die(msg); +} #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index ed10807..082ba29 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -43,6 +43,7 @@ /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __noreturn die(const char *msg); +void __noreturn die_with_post_code(uint8_t value, const char *msg); /* * This function is weak and can be overridden to provide additional -- To view, visit https://review.coreboot.org/c/coreboot/+/32838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Gerrit-Change-Number: 32838 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: util/scripts: update references to cross-repo-cherrypick
by Jett Rink (Code Review) 20 May '19

20 May '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32849 Change subject: util/scripts: update references to cross-repo-cherrypick ...................................................................... util/scripts: update references to cross-repo-cherrypick It appears that the rebase.sh script was renamed to cross-repo-cherrypick and changed directories. Update comments to reflect that change. Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105 Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M util/scripts/cross-repo-cherrypick 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32849/1 diff --git a/util/scripts/cross-repo-cherrypick b/util/scripts/cross-repo-cherrypick index 38d4f46..42b05b5 100755 --- a/util/scripts/cross-repo-cherrypick +++ b/util/scripts/cross-repo-cherrypick @@ -1,6 +1,6 @@ #!/bin/sh -# rebase.sh - rebase helper script +# cross-repo-cherrypick - rebase helper script # # Copyright 2015, 2017 Google Inc. # @@ -22,8 +22,8 @@ # git remote add ... # git checkout -b upstreaming # git cherry-pick ... -# git rebase -i --exec util/gitconfig/rebase.sh master -# Alternatively, you can run util/gitconfig/rebase.sh after every +# git rebase -i --exec util/scripts/cross-repo-cherrypick master +# Alternatively, you can run util/scripts/cross-repo-cherrypick after every # individual cherry-pick. # use $0 --cros to add a stub BUG/BRANCH/TEST block -- To view, visit https://review.coreboot.org/c/coreboot/+/32849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105 Gerrit-Change-Number: 32849 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Patrick Georgi (Code Review) 20 May '19

20 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... sb/amd/cimx/sb800: Get rid of power button device in coreboot Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD Brazos boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. [..] > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. The same problem exists with the AMD Hudson devices in coreboot. For AMD Hudson (2) and Yangtze based devices this was removed in commit 44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power button) [2]. Two devices are detected. $ dmesg | grep Button [ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.209254] ACPI: Power Button [PWRB] [ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.209349] ACPI: Power Button [PWRF] $ sudo evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Power Button /dev/input/event1: Power Button [..] [1]: https://review.coreboot.org/5546 [2]: https://review.coreboot.org/27272 Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/mainboard/amd/inagua/acpi/gpe.asl M src/mainboard/amd/persimmon/acpi/gpe.asl M src/mainboard/amd/south_station/acpi/gpe.asl M src/mainboard/amd/union_station/acpi/gpe.asl M src/mainboard/asrock/e350m1/acpi/gpe.asl M src/mainboard/elmex/pcm205400/acpi/gpe.asl M src/mainboard/gizmosphere/gizmo/acpi/gpe.asl M src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl M src/mainboard/pcengines/apu1/acpi/gpe.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl 10 files changed, 0 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Stefan Reinauer: Looks good to me, approved diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 30e6fdc..3cf38c0 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 30e6fdc..3cf38c0 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index 2f22758..e7a320e 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index 2f22758..e7a320e 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl index 0ba8899..7994ae3 100644 --- a/src/mainboard/asrock/e350m1/acpi/gpe.asl +++ b/src/mainboard/asrock/e350m1/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl index 30e6fdc..3cf38c0 100644 --- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl index 0b9250d..e520724 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl @@ -16,12 +16,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -43,7 +37,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -64,14 +57,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index 30e6fdc..3cf38c0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl index 30e6fdc..3cf38c0 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 2dc3438..b837b4c 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -354,12 +354,3 @@ PWDA, 1, } } - -Scope(\_SB) { - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } -} /* End Scope(_SB) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 8 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Patrick Georgi (Code Review) 20 May '19

20 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 7 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 20 May 2019 14:43:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Change SD_CD# reset config to PLTRST
by Krishna P Bhat D (Code Review) 20 May '19

20 May '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32782 Change subject: mb/google/hatch: Change SD_CD# reset config to PLTRST ...................................................................... mb/google/hatch: Change SD_CD# reset config to PLTRST The system should boot fine to OS on pressing power button before the system enters G3. However, on hatch, we observe that the system waits for few seconds at "Starting kernel" and then resets, with SD card tray inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD# pad reset config to PLTRST. BUG=b:129933011 TEST=Built and verified on hatch. Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32782/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 32526cc..0b66075 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -339,7 +339,7 @@ /* G4 : SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* G5 : SD_CD# */ - PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP => NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Gerrit-Change-Number: 32782 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell/pmutil.c: Use GEN_PMCON1 for RTC status
by Frans Hendriks (Code Review) 20 May '19

20 May '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32724 Change subject: soc/intel/braswell/pmutil.c: Use GEN_PMCON1 for RTC status ...................................................................... soc/intel/braswell/pmutil.c: Use GEN_PMCON1 for RTC status cbmem_find is not available in every stage. Remove usage of cbmem_find() and use GEN_PMCON1 always. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/pmutil.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32724/1 diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 271eefe..5608bf2 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <cbmem.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -364,15 +363,9 @@ { uint32_t gen_pmcon1; int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - if (ps != NULL) - gen_pmcon1 = ps->gen_pmcon1; - else - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); rtc_fail = !!(gen_pmcon1 & RPS); - if (rtc_fail) printk(BIOS_DEBUG, "RTC failure.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1 Gerrit-Change-Number: 32724 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Override emmc DLL values for Casta
by Jamie Chen (Code Review) 20 May '19

20 May '19

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32799 Change subject: mb/google/octopus: Override emmc DLL values for Casta ...................................................................... mb/google/octopus: Override emmc DLL values for Casta New emmc DLL values for Casta BUG=b:122307918 TEST=Boot to OS on 12 systems Change-Id: Ie51885fb9628fa093ecc38f4a3f3157f751ca9ab Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/mainboard/google/octopus/variants/casta/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32799/1 diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index dc9c911..091b302 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -1,4 +1,45 @@ chip soc/intel/apollolake + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x00000505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x00000c0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x0001000f" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x00000a0a" + # Override USB2 PER PORT register (PORT 4) register "usb2eye[4]" = "{ .Usb20OverrideEn = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/32799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie51885fb9628fa093ecc38f4a3f3157f751ca9ab Gerrit-Change-Number: 32799 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot/vboot_crtm.c: Use ENV_ conditions for vboot_measure_cb...
by Frans Hendriks (Code Review) 20 May '19

20 May '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32532 Change subject: security/vboot/vboot_crtm.c: Use ENV_ conditions for vboot_measure_cbfs_hook() ...................................................................... security/vboot/vboot_crtm.c: Use ENV_ conditions for vboot_measure_cbfs_hook() vboot_measure_cbfs_hook() is included when CONFIG_VBOOT_MEASURED_BOOT is enabled, but this function is defined a 0 in vboot_crtm.h using ENV_ Use same ENV_ for vboot_measure_cbfs_hook() as used in vboot_crtm.h. is_runtime_data() is not used when vboot_measure_cbfs_hook() is disabled, so use same conditions for this function also. BUG=NA TEST=Build Google Banon and Google Cyan Change-Id: Ic62c18db09c119dfb85340a6b7f36bfd148aaa45 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/vboot/vboot_crtm.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32532/1 diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..199bab6 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -139,6 +139,7 @@ return VB2_SUCCESS; } +#if !ENV_BOOTBLOCK && !ENV_DECOMPRESSOR && !ENV_SMM static bool is_runtime_data(const char *name) { const char *whitelist = CONFIG_VBOOT_MEASURED_BOOT_RUNTIME_DATA; @@ -193,3 +194,4 @@ return tpm_measure_region(&rdev, pcr_index, tcpa_metadata); } +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c18db09c119dfb85340a6b7f36bfd148aaa45 Gerrit-Change-Number: 32532 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 20 May '19

20 May '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/#/c/29662/23/src/soc/intel/braswell/romstage/ca… File src/soc/intel/braswell/romstage/car_stage_entry.S: https://review.coreboot.org/#/c/29662/23/src/soc/intel/braswell/romstage/ca… PS23, Line 24: #include "src/drivers/intel/fsp1_1/after_raminit.S" : > Tried to integrate this patch set with 30686 but build fails on redefinitions of car_get_var_ptr() a […] After resync and clean build, able to build. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 26 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 20 May 2019 13:26:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: vboot: save whether developer mode is enabled
by Joel Kitching (Code Review) 20 May '19

20 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32843 Change subject: vboot: save whether developer mode is enabled ...................................................................... vboot: save whether developer mode is enabled Save whether or not vboot has selected developer mode as a flag in vboot_working_data. Other coreboot code may access this flag without needing to consult vboot_handoff (which is in the process of being deprecated). BUG=b:124141368, b:124192753 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ieb6ac4937c943aea78ddc762595a05387d2b8114 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/bootmode.c M src/security/vboot/misc.h M src/security/vboot/vboot_common.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_logic.c 5 files changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32843/1 diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index e6e53b6..68749f0 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -164,10 +164,8 @@ int vboot_developer_mode_enabled(void) { - if (cbmem_possibly_online() && vboot_handoff_check_developer_flag()) - return 1; - - return 0; + return cbmem_possibly_online() && + vboot_get_working_data()->flags & VBOOT_WD_FLAG_DEVELOPER_MODE; } #if CONFIG(VBOOT_NO_BOARD_SUPPORT) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 23159c8..acb6dbb 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -47,6 +47,8 @@ */ /* vboot requests display initialization from coreboot. */ #define VBOOT_WD_FLAG_DISPLAY_INIT (1 << 0) +/* vboot has selected developer mode. */ +#define VBOOT_WD_FLAG_DEVELOPER_MODE (1 << 1) /* * Source: security/vboot/common.c diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 14f154c..ff8e6c8 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -88,11 +88,6 @@ return !!(vbho->out_flags & flag); } -int vboot_handoff_check_developer_flag(void) -{ - return vboot_get_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); -} - int vboot_handoff_check_recovery_flag(void) { return vboot_get_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 9a02303..a785a8b 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -62,7 +62,6 @@ * Returns value read for other fields */ int vboot_handoff_check_recovery_flag(void); -int vboot_handoff_check_developer_flag(void); int vboot_handoff_get_recovery_reason(void); /* ============================ VBOOT REBOOT ============================== */ diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index df34490..00347c3 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -364,10 +364,13 @@ vboot_reboot(); } - /* Is vboot declaring that display is available? If so, we should mark - it down, so that the mainboard/SoC knows to initialize display. */ + /* Jot down some information from vboot which may be required later on + in coreboot boot flow. */ if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + /* Mainboard/SoC should initialize display. */ vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; + if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb6ac4937c943aea78ddc762595a05387d2b8114 Gerrit-Change-Number: 32843 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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