coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/soc/intel/common/block/sgx: Add missing new lines
by Christian Walter (Code Review) 03 Jun '19

03 Jun '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33035 Change subject: src/soc/intel/common/block/sgx: Add missing new lines ...................................................................... src/soc/intel/common/block/sgx: Add missing new lines Added missing new lines to Debug Output. Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/common/block/sgx/sgx.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33035/1 diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 2d4cc53..60714d9 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -100,8 +100,8 @@ return; } - printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64); - printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64); + printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64); + printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64); /* Program core PRMRR MSRs. * - Set cache writeback mem attrib in PRMRR base MSR -- To view, visit https://review.coreboot.org/c/coreboot/+/33035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb Gerrit-Change-Number: 33035 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb//nvidia/mcp55/mcp55.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33061 Change subject: sb//nvidia/mcp55/mcp55.c: Remove variable set but not used ...................................................................... sb//nvidia/mcp55/mcp55.c: Remove variable set but not used Change-Id: I40cae58a7a7c9c3c20367541853001510a59e42b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/nvidia/mcp55/mcp55.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33061/1 diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index f93ec92..bd49d9b 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -59,8 +59,6 @@ u32 reg_old, reg; u8 byte; unsigned deviceid, vendorid, devfn; - struct southbridge_nvidia_mcp55_config *conf; - conf = dev->chip_info; int i; if (dev->device == 0x0000) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40cae58a7a7c9c3c20367541853001510a59e42b Gerrit-Change-Number: 33061 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/amd/pi/00630F01/northbridge.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33012 Change subject: nb/amd/pi/00630F01/northbridge.c: Remove variable set but not used ...................................................................... nb/amd/pi/00630F01/northbridge.c: Remove variable set but not used Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00630F01/northbridge.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33012/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c..309a762 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -463,11 +463,9 @@ acpi_header_t *ssdt; acpi_header_t *alib; acpi_header_t *ivrs; - acpi_hest_t *hest; /* HEST */ current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; @@ -680,7 +678,6 @@ struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -711,7 +708,6 @@ // Use hole_basek as mmio_basek, and we don't need to reset hole anymore if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d Gerrit-Change-Number: 33012 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/nvidia/ck804: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33007 Change subject: sb/nvidia/ck804: Remove variable set but not used ...................................................................... sb/nvidia/ck804: Remove variable set but not used Change-Id: Ia8586e229e04fa11696a846653a3a54909ca7c1a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/nvidia/ck804/ck804.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33007/1 diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 59796e1..02d70a6 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -58,9 +58,6 @@ u32 reg_old, reg; u8 byte; - struct southbridge_nvidia_ck804_config *conf; - conf = dev->chip_info; - if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/33007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8586e229e04fa11696a846653a3a54909ca7c1a Gerrit-Change-Number: 33007 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/amd/family_10h-family_15h: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33006 Change subject: cpu/amd/family_10h-family_15h: Remove variable set but not used ...................................................................... cpu/amd/family_10h-family_15h: Remove variable set but not used Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c 1 file changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33006/1 diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 719d62f..fb732c6 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -984,7 +984,6 @@ uint8_t nvram; u32 platform; uint64_t revision; - uint8_t enable_c_states; uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1060,21 +1059,16 @@ } if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { - enable_c_states = 0; if (CONFIG(HAVE_ACPI_TABLES)) - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (enable_c_states) { - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); - c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */ - wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); - } + if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && + (nvram)) { + /* Set up the C-state base address */ + msr_t c_state_addr_msr; + c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); + c_state_addr_msr.lo = ACPI_CPU_P_LVL2; + wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); + } } -#else - enable_c_states = 0; #endif if (revision & AMD_FAM15_ALL) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045 Gerrit-Change-Number: 33006 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/nvidia/mcp55: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33011 Change subject: sb/nvidia/mcp55: Remove variable set but not used ...................................................................... sb/nvidia/mcp55: Remove variable set but not used Change-Id: Ic8f6c264aedbdab0eacb6a99a32cc90336e08d84 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/nvidia/mcp55/lpc.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/33011/1 diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 1aef631..6416dd3 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -100,10 +100,9 @@ get_option(&on, "slow_cpu"); if (on) { u16 pm10_bar; - u32 dword; pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); + inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); -- To view, visit https://review.coreboot.org/c/coreboot/+/33011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8f6c264aedbdab0eacb6a99a32cc90336e08d84 Gerrit-Change-Number: 33011 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32972 Change subject: nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used ...................................................................... nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used Change-Id: Icd9c0541d9006f4ebddcefff9d2355056af0c5c4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32972/1 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 74e5234..853419e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3808,7 +3808,7 @@ { u8 Node; u32 NextBase, BottomIO; - u8 _MemHoleRemap, DramHoleBase, DramHoleOffset; + u8 _MemHoleRemap, DramHoleBase; u32 HoleSize, DramSelBaseAddr; u32 val; @@ -3867,7 +3867,6 @@ if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO)) base = DramSelBaseAddr; val = ((base + HoleSize) >> (24-8)) & 0xFF; - DramHoleOffset = val; val <<= 8; /* shl 16, rol 24 */ val |= DramHoleBase << 24; val |= 1 << DramHoleValid; -- To view, visit https://review.coreboot.org/c/coreboot/+/32972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9c0541d9006f4ebddcefff9d2355056af0c5c4 Gerrit-Change-Number: 32972 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/aspeed/ast2050: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32945 Change subject: drivers/aspeed/ast2050: Remove variable set but not used ...................................................................... drivers/aspeed/ast2050: Remove variable set but not used Change-Id: Iedda92edf8c4eb7be037dcc0faa6fe8aa0c0754c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/aspeed/ast2050/ast2050.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32945/1 diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 631372d..21af5c7 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -37,13 +37,12 @@ static void aspeed_ast2050_init(struct device *dev) { - u8 ret; struct drm_device drm_dev; drm_dev.pdev = dev; printk(BIOS_INFO, "ASpeed AST2050: initializing video device\n"); - ret = ast_driver_load(&drm_dev, 0); + ast_driver_load(&drm_dev, 0); /* Unlock extended configuration registers */ outb(0x80, 0x3d4); outb(0xa8, 0x3d5); -- To view, visit https://review.coreboot.org/c/coreboot/+/32945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedda92edf8c4eb7be037dcc0faa6fe8aa0c0754c Gerrit-Change-Number: 32945 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/fsp_rangeley: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32942 Change subject: sb/intel/fsp_rangeley: Remove variable set but not used ...................................................................... sb/intel/fsp_rangeley: Remove variable set but not used Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/fsp_rangeley/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32942/1 diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 19e470e..2c2427e 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -90,7 +90,6 @@ * Memory is setup and the stack is set by the FSP. */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; timestamp_add_now(TS_AFTER_INITRAM); @@ -113,7 +112,7 @@ /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Gerrit-Change-Number: 32942 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Remove variable set but not used
by HAOUAS Elyes (Code Review) 03 Jun '19

03 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32938 Change subject: nb/intel/sandybridge: Remove variable set but not used ...................................................................... nb/intel/sandybridge: Remove variable set but not used Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/32938/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..900633a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1452,9 +1452,8 @@ int lane; FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); } wait_428c(channel); @@ -1997,9 +1996,8 @@ MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - volatile u32 tmp; MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - tmp = MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ @@ -2344,9 +2342,8 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2425,8 +2422,7 @@ fill_pattern0(ctrl, channel, 0, 0); MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x400 * channel + lane * 4 + 0x4140); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2626,10 +2622,9 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2674,8 +2669,7 @@ wait_428c(channel); FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x4340 + + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d Gerrit-Change-Number: 32938 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019