coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/driver/vpd: Check decoded content length before invoking callback
by Hung-Te Lin (Code Review) 04 Jun '19

04 Jun '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33016 Change subject: src/driver/vpd: Check decoded content length before invoking callback ...................................................................... src/driver/vpd: Check decoded content length before invoking callback When decoding, the content (key or value) part should be also checked before we jump into callback because the callback function has no idea if the contents are all valid. BUG=chromium:967209 TEST=make; boots on at least kukui boards. Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/drivers/vpd/lib_vpd.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33016/1 diff --git a/src/drivers/vpd/lib_vpd.c b/src/drivers/vpd/lib_vpd.c index 0744a71..f235a82 100644 --- a/src/drivers/vpd/lib_vpd.c +++ b/src/drivers/vpd/lib_vpd.c @@ -79,8 +79,8 @@ if (VPD_OK != decodeLen(max_len - *consumed, &input_buf[*consumed], &key_len, &decoded_len) || - *consumed + decoded_len >= max_len) { - return VPD_FAIL; + *consumed + decoded_len + key_len >= max_len) { + return VPD_FAIL; } *consumed += decoded_len; @@ -91,8 +91,8 @@ if (VPD_OK != decodeLen(max_len - *consumed, &input_buf[*consumed], &value_len, &decoded_len) || - *consumed + decoded_len > max_len) { - return VPD_FAIL; + *consumed + decoded_len + value_len > max_len) { + return VPD_FAIL; } *consumed += decoded_len; value = &input_buf[*consumed]; -- To view, visit https://review.coreboot.org/c/coreboot/+/33016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a Gerrit-Change-Number: 33016 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Do not read SPD again if index hasn't changed
by Furquan Shaikh (Code Review) 04 Jun '19

04 Jun '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33137 Change subject: soc/intel/cannonlake: Do not read SPD again if index hasn't changed ...................................................................... soc/intel/cannonlake: Do not read SPD again if index hasn't changed With the recent refactoring of memory configuration in CB:32513 ("soc/intel/cannonlake: Support different SPD read type for each slot"), meminit_cbfs_spd_index ends up reading SPD from CBFS for each slot. However, for mainboards that use the same SPD index for each slot this is unneccessary. This change adds a check to see if spd_data_ptr is not NULL and current spd index is the same as the last call to decide if SPD read from CBFS should be skipped. TEST=Verified that SPD gets read only once on hatch. Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/cnl_memcfg_init.c 1 file changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/33137/1 diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index 4ebd997..d3e5e83 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -91,18 +91,29 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, int spd_index, uint8_t mem_slot) { - size_t spd_data_len; - uintptr_t spd_data_ptr; - struct region_device spd_rdev; + static size_t spd_data_len; + static uintptr_t spd_data_ptr; + static int last_spd_index; assert(mem_slot < NUM_DIMM_SLOT); - printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + + if ((spd_data_ptr == 0) || (last_spd_index != spd_index)) { + struct region_device spd_rdev; + + printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + last_spd_index = spd_index; + } + meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b Gerrit-Change-Number: 33137 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M
by Subrata Banik (Code Review) 04 Jun '19

04 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33144 Change subject: arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M ...................................................................... arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/riscv/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/33144/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..25a3980 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,8 +24,8 @@ # one implementation that will not have it due # to security concerns. bool - default n if ARCH_RISCV_M_DISABLED - default y + default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED + default n config ARCH_RISCV_S # S (supervisor) mode is for kernels. It is optional. -- To view, visit https://review.coreboot.org/c/coreboot/+/33144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Gerrit-Change-Number: 33144 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/intel/saddlebrook: Remove unused functions
by Arthur Heymans (Code Review) 03 Jun '19

03 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32985 Change subject: mainboard/intel/saddlebrook: Remove unused functions ...................................................................... mainboard/intel/saddlebrook: Remove unused functions Setting up the SIO serial console is done in the bootblock. Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/saddlebrook/romstage.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32985/1 diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 82b85fd..45f39d4 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -23,15 +23,7 @@ #include <soc/romstage.h> #include "spd/spd.h" #include <spd_bin.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) - -void car_mainboard_pre_console_init(void) -{ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void mainboard_memory_init_params( struct romstage_params *params, -- To view, visit https://review.coreboot.org/c/coreboot/+/32985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329 Gerrit-Change-Number: 32985 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel: Fix Coverity scan report
by John Zhao (Code Review) 03 Jun '19

03 Jun '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33152 Change subject: src/soc/intel: Fix Coverity scan report ...................................................................... src/soc/intel: Fix Coverity scan report Coverity detects pointer mem_info as NULL_RETURNS. Add sanity check for mem_info to prevent null pointer dereference. BUG=CID 1401394 TEST=Built and boot up to kernel. Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/broadwell/romstage/raminit.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33152/1 diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index fc8b7c6..ffa1feb 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -122,6 +122,10 @@ printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + + if (!mem_info) + return; + memset(mem_info, 0, sizeof(*mem_info)); /* Translate pei_memory_info struct data into memory_info struct */ mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; -- To view, visit https://review.coreboot.org/c/coreboot/+/33152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6 Gerrit-Change-Number: 33152 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/link: Prevent null pointer dereference
by Jacob Garber (Code Review) 03 Jun '19

03 Jun '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33154 Change subject: mb/google/link: Prevent null pointer dereference ...................................................................... mb/google/link: Prevent null pointer dereference Only check the lastidread if there is one. Change-Id: I81248192fe52b2d536976385715bc54aa73d450c Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1375985 --- M src/mainboard/google/link/i915.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33154/1 diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 12d424c..35a30c9 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -173,7 +173,7 @@ if (verbose & vio) printk(BIOS_SPEW, "\texpect %08lx\n", id->data); /* we're looking for something. */ - if (lastidread->addr == id->addr){ + if ((lastidread != NULL) && (lastidread->addr == id->addr)) { /* they're going to be polling. * just do it 1000 times */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81248192fe52b2d536976385715bc54aa73d450c Gerrit-Change-Number: 33154 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/link: Make iodefs array const
by Jacob Garber (Code Review) 03 Jun '19

03 Jun '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33157 Change subject: mb/google/link: Make iodefs array const ...................................................................... mb/google/link: Make iodefs array const This array is fixed during compile time and is not modified during program execution, so we can make it const. Change-Id: I3b4a71e1763b6d7e09859691f3a8d829f5f04577 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/mainboard/google/link/i915.c M src/mainboard/google/link/i915io.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33157/1 diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 12d424c..955ae4f 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -132,8 +132,8 @@ return microseconds(globalstart, rdtscll()); } -extern struct iodef iodefs[]; -extern int niodefs; +extern const struct iodef iodefs[]; +extern const int niodefs; static int i915_init_done = 0; @@ -154,7 +154,7 @@ static int run(int index) { int i, prev = 0; - struct iodef *id, *lastidread = NULL; + const struct iodef *id, *lastidread = NULL; unsigned long u, t; if (index >= niodefs) return index; diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 5ebb42d..dea78d0 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -17,7 +17,7 @@ #include <stdlib.h> #include "i915io.h" -struct iodef iodefs[] = { +const struct iodef iodefs[] = { {V, 0}, {W, 1, "", PCH_GMBUS0, 0x00000000, 0}, {R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0}, @@ -352,4 +352,4 @@ {I,}, }; -int niodefs = ARRAY_SIZE(iodefs); +const int niodefs = ARRAY_SIZE(iodefs); -- To view, visit https://review.coreboot.org/c/coreboot/+/33157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b4a71e1763b6d7e09859691f3a8d829f5f04577 Gerrit-Change-Number: 33157 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake/Kconfig: Add CONSOLE_UART_BASE_ADDRESS
by Patrick Rudolph (Code Review) 03 Jun '19

03 Jun '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33065 Change subject: soc/intel/apollolake/Kconfig: Add CONSOLE_UART_BASE_ADDRESS ...................................................................... soc/intel/apollolake/Kconfig: Add CONSOLE_UART_BASE_ADDRESS Set CONSOLE_UART_BASE_ADDRESS for SoC's internal UART. Allows to build SeaBios without manually specifying the MMIO address. Tested on Up squared: The serial works in SeaBios. Change-Id: I32c18aa6f767cfaf14e3b86796d7d7a32ff1d3d5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33065/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 217d1ea..bce276c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -361,6 +361,14 @@ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xddffc000 if UART_FOR_CONSOLE = 0 + default 0xddffe000 if UART_FOR_CONSOLE = 1 + default 0xde000000 if UART_FOR_CONSOLE = 2 + depends on DRIVERS_UART_8250MEM_32 + depends on CONSOLE_SERIAL + config APL_SKIP_SET_POWER_LIMITS bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/33065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32c18aa6f767cfaf14e3b86796d7d7a32ff1d3d5 Gerrit-Change-Number: 33065 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel: Replace UART_BASE() and friends with a Kconfig
by Nico Huber (Code Review) 03 Jun '19

03 Jun '19

Hello Patrick Rudolph, Lance Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33098 to review the following change. Change subject: soc/intel: Replace UART_BASE() and friends with a Kconfig ...................................................................... soc/intel: Replace UART_BASE() and friends with a Kconfig Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident on APL at least. It is used outside of soc/intel/ scope, e.g. to con- figure SeaBIOS. As we only ever configure a single UART for the coreboot console, we don't need different addresses for each possible UART. Which saves us a lot of code. Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/acpi/acpi_debug.asl M src/soc/intel/common/block/uart/uart.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/iomap.h 10 files changed, 25 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33098/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 217d1ea..1f819ea 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -361,6 +361,11 @@ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xddffc000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + config APL_SKIP_SET_POWER_LIMITS bool default n diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 8e2986d..4b82365 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -58,12 +58,4 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xddffc000 -/* UART BARs are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index e524275..76906b2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -223,6 +223,11 @@ default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 100bd11..1ebaf3f 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -29,14 +29,6 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xfe032000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index 6c52bbf..0c0be15 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -59,7 +59,7 @@ #if CONFIG(DRIVERS_UART_8250MEM_32) OperationRegion (UBAR, SystemMemory, - UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24) + CONFIG_CONSOLE_UART_BASE_ADDRESS, 24) Field (UBAR, AnyAcc, NoLock, Preserve) { TDR, 8, /* Transmit Data Register BAR + 0x000 */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 84ba1ee..9d820ff 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -47,7 +47,7 @@ uintptr_t uart_platform_base(int idx) { if (idx == CONFIG_UART_FOR_CONSOLE) - return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + return CONFIG_CONSOLE_UART_BASE_ADDRESS; return 0; } #endif @@ -137,8 +137,7 @@ void uart_bootblock_init(void) { /* Program UART BAR0, command, reset and clock register */ - uart_common_init(uart_get_device(), - UART_BASE(CONFIG_UART_FOR_CONSOLE)); + uart_common_init(uart_get_device(), CONFIG_CONSOLE_UART_BASE_ADDRESS); /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); @@ -155,8 +154,8 @@ uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ - res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE); - res->size = UART_BASE_SIZE; + res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS; + res->size = 0x1000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a4b46ba..052e37d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -138,6 +138,11 @@ int default 3 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 7c42b57..218b8bf 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -28,14 +28,6 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xfe032000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6..626b5f8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -289,6 +289,11 @@ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe030000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 628a272..c73d766 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -25,13 +25,6 @@ #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -#define UART_BASE_SIZE 0x1000 -#define UART_BASE_0_ADDRESS 0xfe030000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -- To view, visit https://review.coreboot.org/c/coreboot/+/33098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309 Gerrit-Change-Number: 33098 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI
by Arthur Heymans (Code Review) 03 Jun '19

03 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33064 Change subject: sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI ...................................................................... sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI This allows to use the CONFIG_CONSOLE_SPI_FLASH. Change-Id: I563c69ce6337d46380f889f42633e858ac207916 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801ix/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33064/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index a269773..5edb8a1 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -18,6 +18,7 @@ bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG -- To view, visit https://review.coreboot.org/c/coreboot/+/33064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I563c69ce6337d46380f889f42633e858ac207916 Gerrit-Change-Number: 33064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019