coreboot-gerrit April 2019

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Change in ...coreboot[master]: mb/google/sarien: Add psys_pmax setting to 136W
by Gaggery Tsai (Code Review) 29 Apr '19

29 Apr '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32457 Change subject: mb/google/sarien: Add psys_pmax setting to 136W ...................................................................... mb/google/sarien: Add psys_pmax setting to 136W This patch adds the setting of psys_pmax to 136W. According to the design, Rpsys is 11.8Kohm. Here is the equation to come out the Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm = 1.2V (full scale). Hence, Psys_pmax is 136W. BUG=b:124792558 BRANCH=None TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/32457/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 27c0913..b086b9f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -43,6 +43,7 @@ register "SlowSlewRateForFivr" = "2" register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" + register "psys_pmax" = "136" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/32457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056 Gerrit-Change-Number: 32457 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Clear the GPI IS & IE registers
by Karthik Ramasubramanian (Code Review) 29 Apr '19

29 Apr '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32448 to review the following change. Change subject: mb/google/octopus: Clear the GPI IS & IE registers ...................................................................... mb/google/octopus: Clear the GPI IS & IE registers Clear the GPI Interrupt Status & Enable registers before configuring the GPIO pad to prevent any interrupt storms due to GPI. BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/octopus/mainboard.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32448/1 diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 4316ffe..f3a015d 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -71,6 +71,7 @@ base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); + gpi_clear_int_cfg(); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); -- To view, visit https://review.coreboot.org/c/coreboot/+/32448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb Gerrit-Change-Number: 32448 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Add support to clear GPI IS & IE registers
by Karthik Ramasubramanian (Code Review) 29 Apr '19

29 Apr '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32447 to review the following change. Change subject: soc/intel/common: Add support to clear GPI IS & IE registers ...................................................................... soc/intel/common: Add support to clear GPI IS & IE registers Add support to reset the GPI Interrupt Status & Enable registers so that the system does not experience any interrupt storm from a GPI when it comes out of one of the sleep states. BUG=b:130593883 BRANCH=None TEST=Ensure that the Interrupt status & enable registers are reset during the boot up. Ensure that the system boots fine to ChromeOS. Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32447/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 47e2817..f5dd47b 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -582,3 +582,28 @@ { return reg_val; } + +void gpi_clear_int_cfg(void) +{ + int i, group, num_groups; + uint32_t offset, sts_value; + size_t gpio_communities; + const struct pad_community *comm; + + comm = soc_gpio_get_community(&gpio_communities); + for (i = 0; i < gpio_communities; i++, comm++) { + num_groups = comm->num_gpi_regs; + for (group = 0; group < num_groups; group++) { + /* Clear the enable register */ + offset = comm->gpi_int_en_reg_0 + + group * sizeof(uint32_t); + pcr_write32(comm->port, offset, 0); + + /* Read and clear the set status register bits*/ + offset = comm->gpi_int_sts_reg_0 + + group * sizeof(uint32_t); + sts_value = pcr_read32(comm->port, offset); + pcr_write32(comm->port, offset, sts_value); + } + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 147f689..4179293 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -209,5 +209,11 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val); +/* + * Function to reset/clear the GPI Interrupt Enable & Status registers for + * all GPIO pad communities. + */ +void gpi_clear_int_cfg(void); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb Gerrit-Change-Number: 32447 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel: Add GPI interrupt config register offset info
by Karthik Ramasubramanian (Code Review) 29 Apr '19

29 Apr '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32446 to review the following change. Change subject: soc/intel: Add GPI interrupt config register offset info ...................................................................... soc/intel: Add GPI interrupt config register offset info Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup. BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS. Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/apollolake/gpio_apl.c M src/soc/intel/apollolake/gpio_glk.c M src/soc/intel/apollolake/include/soc/gpio_apl.h M src/soc/intel/apollolake/include/soc/gpio_glk.h M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/denverton_ns/gpio.c M src/soc/intel/icelake/gpio.c M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h 14 files changed, 76 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/32446/1 diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index b76c9b0..10b7ba6 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -57,6 +57,8 @@ .gpi_status_offset = 0, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -74,6 +76,8 @@ .gpi_status_offset = NUM_SW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -91,6 +95,8 @@ .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -109,6 +115,8 @@ + NUM_SW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index 99f4e4d..0147519 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -57,6 +57,8 @@ .gpi_status_offset = 0, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -74,6 +76,8 @@ .gpi_status_offset = NUM_NW_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -91,6 +95,8 @@ .gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -109,6 +115,8 @@ NUM_AUDIO_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/apollolake/include/soc/gpio_apl.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h index 67c8a75..ecd9101 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_apl.h +++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h @@ -49,6 +49,7 @@ #define PAD_CFG_BASE 0x500 +#define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x140 diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h index f1ae49e..54ce952 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_glk.h +++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h @@ -282,6 +282,7 @@ */ #define HOSTSW_OWN_REG_0 0xB0 +#define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x170 diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 30ee939..dd51464 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -85,6 +85,8 @@ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -101,6 +103,8 @@ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -117,6 +121,8 @@ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -133,6 +139,8 @@ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -149,6 +157,8 @@ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index d59dea5..102444a 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -87,6 +87,8 @@ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -103,6 +105,8 @@ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -119,6 +123,8 @@ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -135,6 +141,8 @@ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -151,6 +159,8 @@ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 8a944b1..5c12e4c 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -246,6 +246,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index e77dbf8..d03723d 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -320,6 +320,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 11a03d0..147f689 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -105,8 +105,10 @@ gpio_t first_pad; /* first pad in community */ gpio_t last_pad; /* last pad in community */ uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */ - uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI EN Reg 0 */ - uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI STS Reg 0 */ + uint16_t gpi_int_sts_reg_0; /* offset to GPI Int STS Reg 0 */ + uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */ + uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */ + uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */ uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */ uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c index 7c45d40..510f184 100644 --- a/src/soc/intel/denverton_ns/gpio.c +++ b/src/soc/intel/denverton_ns/gpio.c @@ -58,6 +58,8 @@ NUM_SC0_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -75,6 +77,8 @@ .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -92,6 +96,8 @@ .gpi_status_offset = NUM_NC_GPI_REGS, .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -109,6 +115,8 @@ .gpi_status_offset = 0, .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET, .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN, + .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS, + .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE, .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS, .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index 5362005..b1c46ab 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -84,6 +84,8 @@ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -100,6 +102,8 @@ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -116,6 +120,8 @@ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -132,6 +138,8 @@ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -148,6 +156,8 @@ .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 86d5fb2..6ecda85 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -265,6 +265,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 39cbde6..67edeae 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -73,6 +73,8 @@ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -93,6 +95,8 @@ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -114,6 +118,8 @@ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, @@ -130,6 +136,8 @@ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 1c143a2..321d3c2 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -225,6 +225,8 @@ #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 #define HOSTSW_OWN_REG_0 0xd0 #define PAD_CFG_BASE 0x400 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Gerrit-Change-Number: 32446 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: Makefile: Check for errors in ACPI decompilation, too
by Nico Huber (Code Review) 29 Apr '19

29 Apr '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32469 Change subject: Makefile: Check for errors in ACPI decompilation, too ...................................................................... Makefile: Check for errors in ACPI decompilation, too We only grep'ed for "ACPI Warning" resulting in an actual more sever "ACPI Error" being ignored. Change-Id: I9cec8a388f5558b1ffc383cc2fc69405252cbb37 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32469/1 diff --git a/Makefile.inc b/Makefile.inc index 36c05db..fc04a16 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -267,7 +267,14 @@ @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $(obj)/$(1).asl cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $(1).asl - if [ -z "$$$$($(IASL) -d $$@ 2>&1 | grep 'ACPI Warning')" ]; then echo " IASL $$@ disassembled correctly."; true; else echo "Error: Could not correctly disassemble $$@"; $(IASL) -d $$@; false; fi + if ! $(IASL) -d $$@ 2>&1 | grep -Eq 'ACPI (Warning|Error)'; then \ + echo " IASL $$@ disassembled correctly."; \ + true; \ + else \ + echo "Error: Could not correctly disassemble $$@"; \ + $(IASL) -d $$@; \ + false; \ + fi endef ####################################################################### -- To view, visit https://review.coreboot.org/c/coreboot/+/32469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cec8a388f5558b1ffc383cc2fc69405252cbb37 Gerrit-Change-Number: 32469 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: nb/intel/sandybridge: Use system_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32493 Change subject: nb/intel/sandybridge: Use system_reset() ...................................................................... nb/intel/sandybridge: Use system_reset() Use already defined system_reset() function. Change-Id: Ic4716a3bb1dc6c6b29a028fc0ab28f9195f08416 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 4 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32493/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 050f4c2..efd56a5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -312,9 +312,7 @@ && reg_5d10 && !s3resume) { MCHBAR32(0x5d10) = 0; /* Need reset. */ - outb(0x6, 0xcf9); - - halt(); + system_reset(); } early_pch_init_native(); @@ -326,8 +324,7 @@ if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } ctrl_cached = NULL; } else { @@ -356,8 +353,7 @@ if (err) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* no need to erase bad mrc cache here, it gets overwritten on * successful boot. */ @@ -430,8 +426,7 @@ save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/32493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4716a3bb1dc6c6b29a028fc0ab28f9195f08416 Gerrit-Change-Number: 32493 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: mb/google/hatch/: FPMCU not rebooted when DUT reboots
by Tim Wawrzynczak (Code Review) 29 Apr '19

29 Apr '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32419 Change subject: mb/google/hatch/: FPMCU not rebooted when DUT reboots ...................................................................... mb/google/hatch/: FPMCU not rebooted when DUT reboots Add FP_RST_ODL to early GPIO table, configured as low, so that the FPMCU will get reset when coreboot enters bootblock. BUG=b:130229952 BRANCH=none TEST=Compiles (no Hatch device w/FP to test) Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32419/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 7e82b9b..6008910 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -441,6 +441,8 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347 Gerrit-Change-Number: 32419 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: linuxboot/Kconfig: Remove symbol name of a `choice`
by Nico Huber (Code Review) 29 Apr '19

29 Apr '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32390 Change subject: linuxboot/Kconfig: Remove symbol name of a `choice` ...................................................................... linuxboot/Kconfig: Remove symbol name of a `choice` Kconfig somehow adds spurious booleans for each alternative when the choice itself has a name. That's fixed simply by removing the name. Change-Id: Ic35f0697f1f7bb92c12414c17a8790464b376012 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/external/LinuxBoot/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32390/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index ccf62b8..84af49c 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -123,7 +123,7 @@ Note: this can be a defconfig file or a complete .config file. -choice LINUXBOOT_KERNEL_FORMAT +choice prompt "Kernel binary format" default LINUXBOOT_KERNEL_BZIMAGE if LINUXBOOT_X86 || LINUXBOOT_X86_64 default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 -- To view, visit https://review.coreboot.org/c/coreboot/+/32390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic35f0697f1f7bb92c12414c17a8790464b376012 Gerrit-Change-Number: 32390 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
by Nico Huber (Code Review) 29 Apr '19

29 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 ) Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ...................................................................... Patch Set 9: > > > If LPSS (SIO DMA1) pci device 0/30/0 is configured in ACPI mode, PWM, HS2UARTS, and SPI controller needs to be configured in ACPI mode. > > > If LPSS (SIO DMA2) pci device 0/24/0 is configured in ACPI mode, I2C controller needs to be configured in ACPI mode. > > > In other words: If function > 1 in PCI mode, function 0 must be PCI mode to be PCI-enumerated. > > > (See 33.1 of Intel Braswell BIOS Writes Guide) > > > (See 24.3 of Intel Braswell External Design Guide Volume 2) > > > > > > This is NOT a bug in FSP. I expect it's responsibility of coreboot/developer to provide correct parameters API of FSP. > > > > IMO it is still a BUG in FSP docs. The FSP docs do not document ACPI mode for DMAs and the dependency for child devices following the parent device setting. How a developer can integrate the binary correctly when the documentation and API have bugs? Not everyone has access to FSP source code, let's keep that in mind. > > I (now) realize that not everyone has access to all Intel document/FSP source code. > > On the other hand providing a patch and having code-review score of -1, I don't feel much support for supplying for this kit of fixes/update to coreboot. A -1 merely states that somebody doesn't like the current state of a patch, not the patch itself (it should automa- tically vanish once you push a new version). Your help here is much appreciated. When you write some code that conflicts an API documentation, that's ok when you know better. But most developers (no matter if they have access to FSP sources) will probably trust the API documentation and think that your code is wrong. So please add a code comment in such cases (or try to get the documentation fixed). But before you continue, I would like to know in detail how you tested this. The interaction of coreboot and FSP is most fragile, especially when coreboot and FSP both offer options to configure the same thing (ACPI mode in this case). I fear, in case FSP hides the PCI device too early, dev_enable_acpi_mode() in core- boot might not work correctly anymore (e.g. fail to report the correct BARs). -- To view, visit https://review.coreboot.org/c/coreboot/+/29284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8 Gerrit-Change-Number: 29284 Gerrit-PatchSet: 9 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 29 Apr 2019 08:57:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/braswell: Move LPE ACPI code to mainboard
by Nico Huber (Code Review) 29 Apr '19

29 Apr '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: soc/intel/braswell: Move LPE ACPI code to mainboard ...................................................................... soc/intel/braswell: Move LPE ACPI code to mainboard The ACPI code of LPE device is included regardless of the availability of the LPE controller. Linux remains requesting the status of device LPEA even if this device is disabled. Include ACPI LPE controller code at Braswell mainboards with LPE enabled. BUG=N/A TEST=Linux 4.17+ on Portwell PQ7-M107 Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29414 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/google/cyan/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/soc/intel/braswell/acpi/southcluster.asl 3 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 397f6d2..3afdaaa 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -42,6 +42,7 @@ #else #include <acpi/dptf/cpu.asl> #endif + #include <acpi/lpe.asl> } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index c8be3ce..5052ba26 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", @@ -39,6 +38,7 @@ { #include <acpi/southcluster.asl> #include <acpi/dptf/cpu.asl> + #include <acpi/lpe.asl> } /* Dynamic Platform Thermal Framework */ diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index f7e3168..9ecf67a 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -286,7 +286,4 @@ /* SCC Devices */ #include "scc.asl" - - /* LPE Device */ - #include "lpe.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2019