coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Christian Herzog (Code Review) 26 Apr '19

26 Apr '19

Christian Herzog has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 7: > Hi all, > > new guy here. I ported patch set 7 to an X220 (nitrocaster FullHD mod + LP125WF2 SPB4) and managed to create a coreboot config that shows seabios output and works nicely in Linux (VGA BIOS dump needed). If you're interested, I'd be happy to create a PR and provide .config and all relevant information. > > cheers, > -Christian here's a write-up with all necessary information and the github repo: https://daduke.org/hardware/x220-fhd/ -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 7 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Fri, 26 Apr 2019 19:52:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Revert "soc/intel/common/block: add VMX support"
by Matt DeVillier (Code Review) 26 Apr '19

26 Apr '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29683 ) Change subject: Revert "soc/intel/common/block: add VMX support" ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a5d558b03497d106083eece10c5b34e0e7cbb2d Gerrit-Change-Number: 29683 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 26 Apr 2019 18:11:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Add RHSA and ANDD structures for DMAR table
by John Zhao (Code Review) 26 Apr '19

26 Apr '19

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32189 Change subject: ACPI: Add RHSA and ANDD structures for DMAR table ...................................................................... ACPI: Add RHSA and ANDD structures for DMAR table Remapping Hardware Status Affinity (RHSA) structure is applicable for platforms supporting non-uniform memory. An ACPI Name-space Device Declaration (ANDD) structure uniquely represents an ACPI name-space enumerated device capable of issuing DMA requests in the platform. Add RHSA and ANDD structures support for DMAR table generation. Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7 Signed-off-by: zhaojohn <john.zhao(a)intel.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32189/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..781efac 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -568,6 +568,32 @@ return atsr->length; } +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, + u32 proximity_domain) +{ + dmar_rhsa_entry_t *rhsa = (dmar_rhsa_entry_t *)current; + memset(rhsa, 0, sizeof(*rhsa)); + rhsa->type = DMAR_RHSA; + rhsa->length = sizeof(*rhsa); /* will be fixed up later */ + rhsa->base_address = base_addr; + rhsa->proximity_domain = proximity_domain; + + return rhsa->length; +} + +unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, + const char *device_name) +{ + dmar_andd_entry_t *andd = (dmar_andd_entry_t *)current; + memset(andd, 0, sizeof(*andd)); + andd->type = DMAR_ANDD; + andd->length = sizeof(*andd); /* will be fixed up later */ + andd->device_number = device_number; + memcpy(&andd->device_name, device_name, 4); + + return andd->length; +} + void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current) { dmar_entry_t *drhd = (dmar_entry_t *)base; @@ -586,6 +612,18 @@ atsr->length = current - base; } +void acpi_dmar_rhsa_fixup(unsigned long base, unsigned long current) +{ + dmar_rhsa_entry_t *rhsa = (dmar_rhsa_entry_t *)base; + rhsa->length = current - base; +} + +void acpi_dmar_andd_fixup(unsigned long base, unsigned long current) +{ + dmar_andd_entry_t *andd = (dmar_andd_entry_t *)base; + andd->length = current - base; +} + static unsigned long acpi_create_dmar_ds(unsigned long current, enum dev_scope_type type, u8 enumeration_id, u8 bus, u8 dev, u8 fn) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f4ed744..3df0c64 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -366,6 +366,22 @@ u16 segment; } __packed dmar_atsr_entry_t; +typedef struct dmar_rhsa_entry { + u16 type; + u16 length; + u32 reserved; + u64 base_address; + u32 proximity_domain; +} __packed dmar_rhsa_entry_t; + +typedef struct dmar_andd_entry { + u16 type; + u16 length; + u8 reserved[3]; + u8 device_number; + char device_name[4]; +} __packed dmar_andd_entry_t; + /* DMAR (DMA Remapping Reporting Structure) */ typedef struct acpi_dmar { struct acpi_table_header header; @@ -850,9 +866,15 @@ u64 bar, u64 limit); unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment); +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, + u32 proximity_domain); +unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, + const char *device_name); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); +void acpi_dmar_rhsa_fixup(unsigned long base, unsigned long current); +void acpi_dmar_andd_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn); unsigned long acpi_create_dmar_ds_pci(unsigned long current, -- To view, visit https://review.coreboot.org/c/coreboot/+/32189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7 Gerrit-Change-Number: 32189 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by HAOUAS Elyes (Code Review) 26 Apr '19

26 Apr '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h File src/soc/intel/cannonlake/chip.h: https://review.coreboot.org/#/c/32389/2/src/soc/intel/cannonlake/chip.h@24 PS2, Line 24: #include <smbios.h> Please why this is included ? -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 26 Apr 2019 17:18:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apl/acpi: Do not report 8259 PICs
by Nico Huber (Code Review) 26 Apr '19

26 Apr '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29833 ) Change subject: soc/intel/apl/acpi: Do not report 8259 PICs ...................................................................... soc/intel/apl/acpi: Do not report 8259 PICs The IRQ tables don't support this path, so we shouldn't report presence of the legacy PICs. As the _PIC method is optional and we ignore the passed parameter anyway, drop it. Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29833 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Lance Zhao <lance.zhao(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/acpi/platform.asl 2 files changed, 1 insertion(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Lance Zhao: Looks good to me, approved diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d715f39..98fdb02 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_NO_PCAT_8259 select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl index ec1844a..f3202a0 100644 --- a/src/soc/intel/apollolake/acpi/platform.asl +++ b/src/soc/intel/apollolake/acpi/platform.asl @@ -18,19 +18,3 @@ /* Enable ACPI _SWS methods */ #include <soc/intel/common/acpi/acpi_wake_source.asl> #include <soc/intel/common/acpi/platform.asl> - -Name(\PICM, Zero) // IOAPIC/8259 - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207 Gerrit-Change-Number: 29833 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/braswell: Move LPE ACPI code to mainboard
by Nico Huber (Code Review) 26 Apr '19

26 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: soc/intel/braswell: Move LPE ACPI code to mainboard ...................................................................... Patch Set 12: Code-Review+2 (3 comments) https://review.coreboot.org/#/c/29414/11//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29414/11//COMMIT_MSG@12 PS11, Line 12: LPE enabled. > I still miss the information that this works around an […] Done https://review.coreboot.org/#/c/29414/10/src/mainboard/google/cyan/dsdt.asl File src/mainboard/google/cyan/dsdt.asl: https://review.coreboot.org/#/c/29414/10/src/mainboard/google/cyan/dsdt.asl… PS10, Line 7: * Copyright (C) 2019 Eltan B.V. > Is this contribution really worth adding a copyright line? Is it a "Creative and significant" contr […] Done https://review.coreboot.org/#/c/29414/8/src/soc/intel/braswell/acpi/southcl… File src/soc/intel/braswell/acpi/southcluster.asl: https://review.coreboot.org/#/c/29414/8/src/soc/intel/braswell/acpi/southcl… PS8, Line 291: > This issue can be solved different ways. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 26 Apr 2019 16:56:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/{amd,intel}/chip: Use local include for chip.h
by HAOUAS Elyes (Code Review) 26 Apr '19

26 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32014 Change subject: soc/{amd,intel}/chip: Use local include for chip.h ...................................................................... soc/{amd,intel}/chip: Use local include for chip.h Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/fsp_broadwell_de/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/chip.c 6 files changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32014/1 diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1bd8cbf..5c2a58b 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <bootstate.h> #include <console/console.h> #include <cpu/amd/mtrr.h> @@ -30,6 +29,8 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include "chip.h" + /* Supplied by i2c.c */ extern struct device_operations stoneyridge_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e8fd9d1..dbf697d 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -23,6 +22,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + static void pci_domain_set_resources(struct device *dev) { printk(BIOS_SPEW, "%s/%s (%s)\n", diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index d50c689..8df0aa7 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -28,6 +27,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index 6b14845..1711e3a 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -22,7 +22,8 @@ #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <chip.h> + +#include "chip.h" static void pci_domain_set_resources(struct device *dev) { diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 0e4388e..e275fd2 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +28,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 98e5baf..fa2e0fb 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -15,7 +15,6 @@ */ #include <arch/acpi.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -33,6 +32,8 @@ #include <soc/ramstage.h> #include <string.h> +#include "chip.h" + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a -- To view, visit https://review.coreboot.org/c/coreboot/+/32014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Gerrit-Change-Number: 32014 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Fill SMBIOS type 9
by Lijian Zhao (Code Review) 26 Apr '19

26 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32294 Change subject: mb/google/sarien: Fill SMBIOS type 9 ...................................................................... mb/google/sarien: Fill SMBIOS type 9 Fill mainboard specific system slots information into SMBIOS type 9. BUG=b:129485789 TEST=Boot up into OS on sarien platform and use dmidecode to confirm type9 is presnet and valid. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I2e2795fb4573daadc7e84085d21445e43c4699d1 --- M src/mainboard/google/sarien/ramstage.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32294/1 diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 96321f8..a6a4591 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,11 +14,27 @@ */ #include <arch/acpi.h> +#include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + len += smbios_write_type9( + current, handle, + "NVME SLOT", /* name */ + SlotTypeM2Socket2, /* slot type */ + SMBIOS_SLOT_3P3V, + SMBIOS_SLOT_PME, + 2, 0); /* BDF */ + + return len; +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { const struct pad_config *gpio_table; @@ -31,6 +47,8 @@ static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + + dev->ops->get_smbios_data = mainboard_smbios_data; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/32294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e2795fb4573daadc7e84085d21445e43c4699d1 Gerrit-Change-Number: 32294 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi: Add Kconfig to toggle 8259 reporting
by Nico Huber (Code Review) 26 Apr '19

26 Apr '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29832 ) Change subject: x86/acpi: Add Kconfig to toggle 8259 reporting ...................................................................... x86/acpi: Add Kconfig to toggle 8259 reporting Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/arch/x86/Kconfig M src/arch/x86/acpi.c 2 files changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 242a7cf..827c1cb 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -265,6 +265,14 @@ Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successful boot. +config ACPI_NO_PCAT_8259 + bool + help + Selected by platforms that don't expose a PC/AT 8259 PIC pair. + +config ACPI_HAVE_PCAT_8259 + def_bool y if !ACPI_NO_PCAT_8259 + config ACPI_CPU_STRING string default "\\_PR.CP%02d" diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f08a401..8a620bb 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -229,7 +229,8 @@ header->revision = get_acpi_table_revision(MADT); madt->lapic_addr = LOCAL_APIC_ADDR; - madt->flags = 0x1; /* PCAT_COMPAT */ + if (CONFIG(ACPI_HAVE_PCAT_8259)) + madt->flags |= 1; current = acpi_fill_madt(current); -- To view, visit https://review.coreboot.org/c/coreboot/+/29832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Gerrit-Change-Number: 29832 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/arcada: Add settings for noise mitgation
by Nathan Chen (Code Review) 26 Apr '19

26 Apr '19

Nathan Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32403 Change subject: mb/google/arcada: Add settings for noise mitgation ...................................................................... mb/google/arcada: Add settings for noise mitgation Follow DELL decision. Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen(a)wistron.corp-partner.google.com> Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4 --- A coreboot M src/mainboard/google/sarien/variants/arcada/devicetree.cb 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/32403/1 diff --git a/coreboot b/coreboot new file mode 160000 index 0000000..1db39a4 --- /dev/null +++ b/coreboot @@ -0,0 +1 @@ +Subproject commit 1db39a44661f57c2ffe0d795e21c0a4d5dddb494 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 57c4e65..426bdae 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -37,10 +37,10 @@ register "tdp_pl2_override" = "51" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "0" - register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "0" + register "SlowSlewRateForFivr" = "2" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C -- To view, visit https://review.coreboot.org/c/coreboot/+/32403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4 Gerrit-Change-Number: 32403 Gerrit-PatchSet: 1 Gerrit-Owner: Nathan Chen <nathan_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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