coreboot-gerrit April 2019

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Change in ...libhwbase[master]: Makefile: Revise support for generated sources
by Angel Pons (Code Review) 28 Apr '19

28 Apr '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/27139 ) Change subject: Makefile: Revise support for generated sources ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/libhwbase/+/27139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I5479c436f39088ae9d0ebddf9a97446be0f191f3 Gerrit-Change-Number: 27139 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 28 Apr 2019 20:50:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/ocp/monolake: add TPM and IPMI support
by Łukasz Siudut (Code Review) 28 Apr '19

28 Apr '19

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32443 Change subject: mb/ocp/monolake: add TPM and IPMI support ...................................................................... mb/ocp/monolake: add TPM and IPMI support Changes includes: - enable TPM1 + add entry in devicetree - configure LPC IO to make IPMI work + add entry in devicetree - introduce DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut(a)fb.com> Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04 --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 5 files changed, 147 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32443/1 diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index aff6619..037c322 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,11 @@ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + +config INTEGRATED_UART + def_bool n config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c2..2d91b73 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..72b1c3c 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ { #include "acpi/platform.asl" + Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -290,5 +293,97 @@ } } + Scope (_SB.PCI0.LPC0) + { + Device (SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index 93c2a58..d457859 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,17 +15,51 @@ */ #include <device/device.h> +#include <smbios.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif +#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 2bb50f0..e556aed 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -20,6 +20,8 @@ #include <cpu/x86/msr.h> #include <cf9_reset.h> #include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -49,7 +51,9 @@ */ void late_mainboard_romstage_entry(void) { - + // IPMI through BIC + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); } /** @@ -57,5 +61,4 @@ */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - } -- To view, visit https://review.coreboot.org/c/coreboot/+/32443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04 Gerrit-Change-Number: 32443 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses
by Daniel Maslowski (Code Review) 28 Apr '19

28 Apr '19

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32473 Change subject: Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses ...................................................................... Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addresses Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: cyrevolt --- M Documentation/northbridge/intel/haswell/mrc.bin.md 1 file changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32473/1 diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index 36ab4c4..7f8d3ca 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -27,6 +27,83 @@ Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to its location when building coreboot. +## SPD Addresses + +When porting a board from vendor firmware, the SPD addresses can be obtained +through `i2c-tools`, which can be found in many GNU/Linux distributions. A more +[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of +the procedure and beyond can be found in +[Hannu Hartikainen's blog](https://hannuhartikainen.fi). + +First load the kernel modules: + +```bash +modprobe i2c-dev +modprobe eeprom +``` + +Find the SMBus and the addresses of the DIMM's EEPROMs (example output): +```bash +$ decode-dimms | grep Decoding +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050 +Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052 +``` + +Alternatively, look at the sys filesystem: +```bash +$ ls -l /sys/bus/i2c/drivers/eeprom/ +total 0 +lrwxrwxrwx 1 root root 0 Apr 4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/ +lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/ +--w------- 1 root root 4096 Apr 4 01:47 bind +lrwxrwxrwx 1 root root 0 Apr 4 01:47 module -> ../../../../module/eeprom/ +--w------- 1 root root 4096 Apr 4 01:46 uevent +--w------- 1 root root 4096 Apr 4 01:47 unbind +``` + +The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`. +Note that the above values are actually hex values. + +You can check the correctness of the SMBus and the addresses of the EEPROMs via +`i2cdetect`: + +```bash +$ i2cdetect -l +i2c-3 unknown i915 gmbus dpc N/A +i2c-1 unknown i915 gmbus vga N/A +i2c-6 unknown DPDDC-A N/A +i2c-4 unknown i915 gmbus dpb N/A +i2c-2 unknown i915 gmbus panel N/A +i2c-0 unknown i915 gmbus ssc N/A +i2c-7 unknown SMBus I801 adapter at f040 N/A +i2c-5 unknown i915 gmbus dpd N/A +``` + +Probing the SMBus: + +```bash +$ i2cdetect -r 7 +WARNING! This program can confuse your I2C bus, cause data loss and worse! +I will probe file /dev/i2c-7 using receive byte commands. +I will probe address range 0x03-0x77. +Continue? [Y/n] + 0 1 2 3 4 5 6 7 8 9 a b c d e f +00: -- -- -- -- -- -- -- -- -- -- -- -- -- +10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- +50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- +60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +70: -- -- -- -- -- -- -- -- +``` + +The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied +by 2. For example, if the addresses read through `i2c-tools` when booted from +vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and +`0xa4`. This is because the I2C addresses are 7 bits long. + ## ECC DRAM When `mrc.bin` has finished executing, ECC is active on the channels -- To view, visit https://review.coreboot.org/c/coreboot/+/32473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Gerrit-Change-Number: 32473 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in ...libgfxinit[master]: gma: Add Kaby Lake support
by Nico Huber (Code Review) 27 Apr '19

27 Apr '19

Hello Patrick Rudolph, Arthur Heymans, Thomas Heijligen, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/28763 to look at the new patch set (#6). Change subject: gma: Add Kaby Lake support ...................................................................... gma: Add Kaby Lake support Including some weird Amber Lake Y parts that are treated like Kaby Lake in Linux' i915. Only differences to Skylake in the DDI output buffer tuning. Change-Id: Ice05e07b016cebc7258a9790e38e079e63227a4b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads M common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb 4 files changed, 77 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/63/28763/6 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/28763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ice05e07b016cebc7258a9790e38e079e63227a4b Gerrit-Change-Number: 28763 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...libhwbase[master]: Makefile: Revise support for generated sources
by Nico Huber (Code Review) 27 Apr '19

27 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/27139 ) Change subject: Makefile: Revise support for generated sources ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/libhwbase/+/27139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I5479c436f39088ae9d0ebddf9a97446be0f191f3 Gerrit-Change-Number: 27139 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 27 Apr 2019 15:29:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libhwbase[master]: Makefile: Revise support for generated sources
by Nico Huber (Code Review) 27 Apr '19

27 Apr '19

Hello Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libhwbase/+/27139 to look at the new patch set (#3). Change subject: Makefile: Revise support for generated sources ...................................................................... Makefile: Revise support for generated sources Handle generated source files more independently from normal source files. This allows mixing of generated specs with existing source bodies. As with the source file list, we filter the list of generated sources, `$(name)-gens`: All spec (.ads) files that have a respective body file (.adb), are moved into `$(name)-extra-gens`. This way, we can still add these files as dependencies to all pre-existing source files. Change-Id: I5479c436f39088ae9d0ebddf9a97446be0f191f3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M Makefile.proof 2 files changed, 16 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/39/27139/3 -- To view, visit https://review.coreboot.org/c/libhwbase/+/27139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I5479c436f39088ae9d0ebddf9a97446be0f191f3 Gerrit-Change-Number: 27139 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...libhwbase[master]: Makefile.proof: Add --no-inlining to SPARKFLAGS
by Nico Huber (Code Review) 27 Apr '19

27 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/26850 ) Change subject: Makefile.proof: Add --no-inlining to SPARKFLAGS ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/c/libhwbase/+/26850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: Ia6055da326901c1c25b9d0c757767891284bc515 Gerrit-Change-Number: 26850 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 27 Apr 2019 15:15:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...libhwbase[master]: direct pci, debug: Fix minor style issues
by Nico Huber (Code Review) 27 Apr '19

27 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libhwbase/+/26840 ) Change subject: direct pci, debug: Fix minor style issues ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/26840/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26840/1//COMMIT_MSG@7 PS1, Line 7: direct pci, debug: Minor style fixes > Statement please: […] Done, thanks -- To view, visit https://review.coreboot.org/c/libhwbase/+/26840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I8adbf75babc233dff79e5c8921d1f24692a939ab Gerrit-Change-Number: 26840 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 27 Apr 2019 14:57:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...libhwbase[master]: direct pci, debug: Fix minor style issues
by Nico Huber (Code Review) 27 Apr '19

27 Apr '19

Nico Huber has uploaded a new patch set (#2). ( https://review.coreboot.org/c/libhwbase/+/26840 ) Change subject: direct pci, debug: Fix minor style issues ...................................................................... direct pci, debug: Fix minor style issues Change-Id: I8adbf75babc233dff79e5c8921d1f24692a939ab Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/direct/hw-pci-dev.adb M debug/hw-debug.adb M debug/hw-debug.ads 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/40/26840/2 -- To view, visit https://review.coreboot.org/c/libhwbase/+/26840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: I8adbf75babc233dff79e5c8921d1f24692a939ab Gerrit-Change-Number: 26840 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: google/link: remove non-existant output port HDMI3
by Matt DeVillier (Code Review) 27 Apr '19

27 Apr '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32488 Change subject: google/link: remove non-existant output port HDMI3 ...................................................................... google/link: remove non-existant output port HDMI3 Remove non-existant HDMI3 from output port list in gma-mainboard, since having it there triggers a bug elsewhere in libgfxinit causing the GMBUS controller to end up in a bad state, which results in the touchscreen not working properly under ChromiumOS. Test: Boot ChromiumOS (r67, r69) on google/link w/libgfxinit, verify touchscreen functional. Change-Id: I80a5c6e2684e3488bc66daae778689c4f8a5fd16 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/link/gma-mainboard.ads 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32488/1 diff --git a/src/mainboard/google/link/gma-mainboard.ads b/src/mainboard/google/link/gma-mainboard.ads index 4173725..5e08b1c 100644 --- a/src/mainboard/google/link/gma-mainboard.ads +++ b/src/mainboard/google/link/gma-mainboard.ads @@ -19,7 +19,6 @@ ports : constant Port_List := (Internal, DP3, - HDMI3, others => Disabled); end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/32488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a5c6e2684e3488bc66daae778689c4f8a5fd16 Gerrit-Change-Number: 32488 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019