Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30118 )
Change subject: arch/x86/boot: Call payload in protected mode
......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/#/c/30118/8/src/arch/x86/c_start.S
File src/arch/x86/c_start.S:
https://review.coreboot.org/#/c/30118/8/src/arch/x86/c_start.S@387
PS8, Line 387: push %rsp
> This should be `push %rdx`, then restoration in setCodeSelectorLongJump32 is not required. […]
Done
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Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Gerrit-Change-Number: 30118
Gerrit-PatchSet: 14
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30114 )
Change subject: arch/x86/assembly_entry: Enable long mode on x86_64
......................................................................
Patch Set 12:
(3 comments)
https://review.coreboot.org/#/c/30114/11/src/arch/x86/long_mode.S
File src/arch/x86/long_mode.S:
https://review.coreboot.org/#/c/30114/11/src/arch/x86/long_mode.S@86
PS11, Line 86: or %esi, 0x0(%edi)
> Repeated line. […]
Done
https://review.coreboot.org/#/c/30114/11/src/arch/x86/long_mode.S@90
PS11, Line 90: cmp $(4), %eax
> I may be overzealous here, but counting downwards is slightly faster and easier to understand.
Done
https://review.coreboot.org/#/c/30114/11/src/arch/x86/long_mode.S@194
PS11, Line 194: cmpq $(4), %rax
> As above.
Done
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 )
Change subject: arch/x86: Support x86_64 exceptions
......................................................................
Patch Set 14:
(3 comments)
https://review.coreboot.org/#/c/30117/13/src/arch/x86/idt.S
File src/arch/x86/idt.S:
https://review.coreboot.org/#/c/30117/13/src/arch/x86/idt.S@131
PS13, Line 131: */
> Perhaps SS should be listed as well.
Done
https://review.coreboot.org/#/c/30117/13/src/arch/x86/idt.S@145
PS13, Line 145: lea 64(%rsp), %rbp
> This is also wrong, should be 128(%rsp) due to 8 new registers on stack.
I removed this code as RSP is pushed by interrupt on stack.
https://review.coreboot.org/#/c/30117/13/src/arch/x86/idt.S@159
PS13, Line 159: pop %rax
> Stack was aligned two instructions earlier, this pops wrong values.
Done
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Hello Patrick Rudolph, Aaron Durbin, ron minnich, Julius Werner, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29667
to look at the new patch set (#22).
Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
......................................................................
mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes
Working:
* Boots to Linux
* Boots to SeaBios
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
Broken:
* Entering SMM due to missing long mode setup
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
---
M Documentation/arch/x86/index.md
A Documentation/mainboard/emulation/qemu-i440fx.md
A Documentation/mainboard/emulation/qemu-q35.md
M Documentation/mainboard/index.md
M src/arch/x86/Kconfig
M src/cpu/qemu-x86/Kconfig
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
8 files changed, 168 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29667/22
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Gerrit-MessageType: newpatchset
Patrick Rudolph has uploaded a new patch set (#14) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30118 )
Change subject: arch/x86/boot: Call payload in protected mode
......................................................................
arch/x86/boot: Call payload in protected mode
On ARCH_RAMSTAGE_X86_64 call the payload in protected mode.
Add a helper function to call arbitraty code in protected mode,
similar to the real mode call handler.
Tested on qemu using SeaBios as payload.
Untested for anything else.
Doesn't affect existing x86_32 code.
Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/arch/x86/index.md
M src/arch/x86/boot.c
M src/arch/x86/c_start.S
M src/include/program_loading.h
4 files changed, 188 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30118/14
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Gerrit-MessageType: newpatchset
Patrick Rudolph has uploaded a new patch set (#12) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30114 )
Change subject: arch/x86/assembly_entry: Enable long mode on x86_64
......................................................................
arch/x86/assembly_entry: Enable long mode on x86_64
* Install simple page tables for long mode
* Activate long mode
* Add new Kconfig for CPUs that have 1 GiB hugepage support
* Use a minimum of two pagetables if possible
* Autodetect 1 GiB hugepage support if not known at compile time
The same approach was done on AMD based platforms.
The main reason to have a 64bit romstage, is to support rmodules.
The existing code assumes that both stages (the loader and the one
that is being relocated) have the same architecture.
Tested on qemu using KVM.
Doesn't affect existing x86_32 code.
Change-Id: I57974a55f3b778c90b3587f39e86e4eb8692ad48
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/arch/x86/index.md
M src/arch/x86/Kconfig
M src/arch/x86/Makefile.inc
M src/arch/x86/assembly_entry.S
M src/arch/x86/c_start.S
M src/arch/x86/exit_car_x86_64.S
A src/arch/x86/long_mode.S
M src/cpu/Kconfig
M src/cpu/intel/fsp_model_406dx/Kconfig
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_206ax/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/fsp_baytrail/Kconfig
M src/soc/intel/fsp_broadwell_de/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/skylake/Kconfig
21 files changed, 316 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30114/12
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Gerrit-MessageType: newpatchset
Patrick Rudolph has uploaded a new patch set (#14) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30117 )
Change subject: arch/x86: Support x86_64 exceptions
......................................................................
arch/x86: Support x86_64 exceptions
Tested on qemu using division by zero.
Doesn't affect existing x86_32 code.
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
---
M Documentation/arch/x86/index.md
M src/arch/x86/exception.c
M src/arch/x86/idt.S
M src/arch/x86/include/arch/registers.h
4 files changed, 140 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/30117/14
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Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 )
Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/26346/7/src/soc/intel/common/block/cpu/cpul…
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/#/c/26346/7/src/soc/intel/common/block/cpu/cpul…
PS7, Line 327: lapicid
This value should be cached in a local variable.
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 )
Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
......................................................................
Patch Set 9:
(5 comments)
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/Kconfig
File src/soc/intel/braswell/Kconfig:
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/Kconfig@68
PS9, Line 68: VBOOT_STARTS_IN_ROMSTAGE
> Could be changed.
Will change to VBOOT_STARTS_IN_BOOTBLOCK
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/Kconfig@70
PS9, Line 70: config BOOTBLOCK_CPU_INIT
: string
: default "soc/intel/braswell/bootblock/bootblock.c"
> unused now
Ack
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/bootblock/bo…
File src/soc/intel/braswell/bootblock/bootblock.c:
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/bootblock/bo…
PS9, Line 76:
> Microcode needs to be updated before running CAR. You can use cpu/intel/microcode/microcode_asm. […]
This code is not used in latest patch.
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/romstage/car…
File src/soc/intel/braswell/romstage/car_stage_entry.S:
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/romstage/car…
PS9, Line 24: #include "src/drivers/intel/fsp1_1/after_raminit.S"
> It is better to link files than to include them like this.
This include file does not have entry point (yet)
Now similar to other platforms
https://review.coreboot.org/#/c/29662/9/src/soc/intel/braswell/romstage/car…
PS9, Line 31: #if IS_ENABLED(CONFIG_POST_IO)
: outb %al, $CONFIG_POST_IO_PORT
: #else
: post_code(POST_DEAD_CODE)
: #endif
> Why is this needed?
Will remove the post_code() call. This is just dummy code when CONFIG_POST_IO is not specified.
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