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Change in ...coreboot[master]: Documentation: Add FIT
by Patrick Rudolph (Code Review) 30 Apr '19

30 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32325 Change subject: Documentation: Add FIT ...................................................................... Documentation: Add FIT Describe the Firmware Interface Table and reference useful documentation. Change-Id: I00abc1fd13be7b48d56ba8cb65d2542ed07f9017 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/soc/intel/fit.dia A Documentation/soc/intel/fit.md A Documentation/soc/intel/fit.svg M Documentation/soc/intel/index.md 4 files changed, 193 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32325/1 diff --git a/Documentation/soc/intel/fit.dia b/Documentation/soc/intel/fit.dia new file mode 100644 index 0000000..7e07978 --- /dev/null +++ b/Documentation/soc/intel/fit.dia Binary files differ diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md new file mode 100644 index 0000000..8b638f0 --- /dev/null +++ b/Documentation/soc/intel/fit.md @@ -0,0 +1,60 @@ +# Intel Firmware Interface Table + +The FIT allows to run code before the actual IA32 reset vector is executed +by the CPU. The FIT resides in the BIOS region (usually near the reset vector) +and is pointed to by the FIT pointer residing at `0xFFFFFFC0`. + +## Table layout +The table consists of blocks each 16 bytes in size. +The first is called *FIT header* the other are called *FIT entry*. + +![FIT in x86 memory map][fit] + +[fit]: fit.svg + +## Fit types + +Each entry has a *type* that give the other bits in the entry a different +meaning. The following types are known: + +```eval_rst ++-----------+------------------------------------------------------------------+ +| no. | Description | ++===========+==================================================================+ +| 0x0 | HEADER. | ++-----------+------------------------------------------------------------------+ +| 0x1 | MICROCODE. | ++-----------+------------------------------------------------------------------+ +| 0x2 | STARTUP_ACM. | ++-----------+------------------------------------------------------------------+ +| 0x7 | BIOS_STARTUP_MODULE. | ++-----------+------------------------------------------------------------------+ +| 0x8 | TPM_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0x9 | BIOS_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0xa | TXT_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0xb | KEY_MANIFEST. | ++-----------+------------------------------------------------------------------+ +| 0xc | BOOT_POLICY_MANIFEST. | ++-----------+------------------------------------------------------------------+ +| 0x10 | CSE_SECURE_BOOT. | ++-----------+------------------------------------------------------------------+ +| 0x2d | TXTSX_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0x2f | JMP_DEBUG_POLICY. | ++-----------+------------------------------------------------------------------+ +| 0x7f | SKIP. | ++-----------+------------------------------------------------------------------+ +``` + +## Usage in coreboot + +The most common usage of FIT is to use *Type1* to update microcode before +execution of the IA32 reset vector happens. + +## References + +* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Han… +* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents… diff --git a/Documentation/soc/intel/fit.svg b/Documentation/soc/intel/fit.svg new file mode 100644 index 0000000..eb6c696 --- /dev/null +++ b/Documentation/soc/intel/fit.svg @@ -0,0 +1,132 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="15cm" height="11cm" viewBox="520 311 299 204" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="521.518" y="312.25" width="296.25" height="201.75"/> + <rect style="fill: none; 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Change in ...coreboot[master]: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 30 Apr '19

30 Apr '19

Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29662 to look at the new patch set (#11). Change subject: (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... (drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add post init console functions romstage_c_entry() . - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblokc_c_entry(). Remove the unused cache_as_ram_main(). BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c R src/soc/intel/braswell/bootblock/cache_as_ram.S M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/car_stage_entry.S 9 files changed, 107 insertions(+), 174 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 11 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/icelake: Select FSP_M_XIP
by Subrata Banik (Code Review) 30 Apr '19

30 Apr '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32507 ) Change subject: soc/intel/icelake: Select FSP_M_XIP ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32507/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32507/2//COMMIT_MSG@11 PS2, Line 11: and family > nit: currently ICL seems to support only ice lake SoC. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Gerrit-Change-Number: 32507 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Apr 2019 05:35:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Select FSP_M_XIP
by Subrata Banik (Code Review) 30 Apr '19

30 Apr '19

Hello Patrick Rudolph, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32507 to look at the new patch set (#3). Change subject: soc/intel/icelake: Select FSP_M_XIP ...................................................................... soc/intel/icelake: Select FSP_M_XIP This patch ports CB:32275 changes from CNL to ICL. Ice Lake require that FSP-M component should be XIP. This change selects FSP_M_XIP so that the right arguments are passed into cbfstool when adding this component. Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32507/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Gerrit-Change-Number: 32507 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups
by Furquan Shaikh (Code Review) 30 Apr '19

30 Apr '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32508 ) Change subject: soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8 Gerrit-Change-Number: 32508 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Apr 2019 05:09:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Select FSP_M_XIP
by Furquan Shaikh (Code Review) 30 Apr '19

30 Apr '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32507 ) Change subject: soc/intel/icelake: Select FSP_M_XIP ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32507/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32507/2//COMMIT_MSG@11 PS2, Line 11: and family nit: currently ICL seems to support only ice lake SoC. -- To view, visit https://review.coreboot.org/c/coreboot/+/32507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Gerrit-Change-Number: 32507 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Apr 2019 05:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Select FSP_M_XIP
by Furquan Shaikh (Code Review) 30 Apr '19

30 Apr '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32507 ) Change subject: soc/intel/icelake: Select FSP_M_XIP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Gerrit-Change-Number: 32507 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Apr 2019 05:08:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 30 Apr '19

30 Apr '19

Hello Patrick Rudolph, Aaron Durbin, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26346 to look at the new patch set (#9). Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index() ...................................................................... soc/intel/common/block/cpu: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not true incase of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retriving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpu_mp structure to get correct cpu_index() BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h M src/soc/intel/common/block/cpu/cpulib.c 3 files changed, 24 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/26346/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 30 Apr '19

30 Apr '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index() ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/26346/7/src/soc/intel/common/block/cpu/cpul… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/26346/7/src/soc/intel/common/block/cpu/cpul… PS7, Line 327: lapicid > This value should be cached in a local variable. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Apr 2019 04:18:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/block/cpu: Use core apic id to get cpu_index()
by build bot (Jenkins) (Code Review) 30 Apr '19

30 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: soc/intel/common/block/cpu: Use core apic id to get cpu_index() ...................................................................... Patch Set 8: (3 comments) https://review.coreboot.org/#/c/26346/8/src/arch/x86/cpu.c File src/arch/x86/cpu.c: https://review.coreboot.org/#/c/26346/8/src/arch/x86/cpu.c@314 PS8, Line 314: struct cpu_info *ci; please, no spaces at the start of a line https://review.coreboot.org/#/c/26346/8/src/arch/x86/cpu.c@315 PS8, Line 315: ci = cpu_info(); please, no spaces at the start of a line https://review.coreboot.org/#/c/26346/8/src/arch/x86/cpu.c@316 PS8, Line 316: return ci->index; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Apr 2019 04:12:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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