coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: Revert "mb/google/sarien: Enable ISH on arcada, disable on sarien"
by Li1 Feng (Code Review) 29 Apr '19

29 Apr '19

Hello Jett Rink, Jett Rink, Duncan Laurie, build bot (Jenkins), Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32218 to review the following change. Change subject: Revert "mb/google/sarien: Enable ISH on arcada, disable on sarien" ...................................................................... Revert "mb/google/sarien: Enable ISH on arcada, disable on sarien" This reverts commit b0c726b683bf52fd94250d18aa4c3f78e6622fca. Change-Id: I8f8edf7bba230cb707c1d9dadf1b3de11c1e60da --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32218/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93e0af9..54308e1 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -113,7 +113,6 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d25e725..6afc13c 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -113,7 +113,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub + device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/32218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f8edf7bba230cb707c1d9dadf1b3de11c1e60da Gerrit-Change-Number: 32218 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

4 15

Change in ...coreboot[master]: soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups
by Furquan Shaikh (Code Review) 29 Apr '19

29 Apr '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32508 ) Change subject: soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/32508/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32508/1//COMMIT_MSG@9 PS1, Line 9: This patch ports CB:32175 changes from CNL to ICL. mapping for CNL is very different than ICL, isn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/32508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8 Gerrit-Change-Number: 32508 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 29 Apr 2019 18:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/icelake: Select FSP_M_XIP
by Furquan Shaikh (Code Review) 29 Apr '19

29 Apr '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32507 ) Change subject: soc/intel/icelake: Select FSP_M_XIP ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/32507/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32507/1//COMMIT_MSG@11 PS1, Line 11: Cannon It would be good to update the message to indicate the requirement for ICL -- To view, visit https://review.coreboot.org/c/coreboot/+/32507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Gerrit-Change-Number: 32507 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 29 Apr 2019 18:50:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: fleex: Add VPD entry for deciding which touchscreen ACPI nodes to gen...
by Tim Wawrzynczak (Code Review) 29 Apr '19

29 Apr '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32006 Change subject: fleex: Add VPD entry for deciding which touchscreen ACPI nodes to generate. ...................................................................... fleex: Add VPD entry for deciding which touchscreen ACPI nodes to generate. Fleex has the option of two different touchscreens, WDT or Elan. A new VPD entry will go along with this (key="touchscreen", value="wdt" or "elan"). If the VPD entry exists, only one ACPI node will be generated for that I2C bus. If no entry exists, or no tag is specified in the device tree, then both nodes will be generated and it will be up to the kernel to probe for them. Change-Id: I0e0a9f96f3d3de9be36b218600268711b80c18b9 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/i2c/generic/chip.h M src/drivers/i2c/generic/generic.c M src/mainboard/google/octopus/variants/fleex/overridetree.cb M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/vpd_ssdt.c A src/vendorcode/google/chromeos/vpd_ssdt.h 6 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/32006/1 diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 9e2abb9..7cf04cd 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -75,6 +75,8 @@ /* Generic properties for exporting device-specific data to the OS */ struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST]; int property_count; + const char *vpd_string_tag; + const char *vpd_string_value; }; /* diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 598f211..75a365f 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -22,6 +22,8 @@ #include <gpio.h> #include <stdint.h> #include <string.h> +#include <vendorcode/google/chromeos/vpd_ssdt.h> + #include "chip.h" #if CONFIG(HAVE_ACPI_TABLES) @@ -79,6 +81,11 @@ return; } + if (config->vpd_string_tag && config->vpd_string_value && + !vpd_should_generate_ssdt(config->vpd_string_tag, + config->vpd_string_value)) + return; + /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 19246e0..a368598 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -122,6 +122,8 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "vpd_string_tag" = ""touchscreen"" + register "vpd_string_value" = ""elan"" device i2c 10 on end end chip drivers/i2c/hid @@ -136,6 +138,8 @@ register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" + register "generic.vpd_string_tag" = ""touchscreen"" + register "generic.vpd_string_value" = ""wdt"" device i2c 2c on end end end # - I2C 7 diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..6776c5f 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -18,6 +18,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += vpd_ssdt.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c diff --git a/src/vendorcode/google/chromeos/vpd_ssdt.c b/src/vendorcode/google/chromeos/vpd_ssdt.c new file mode 100644 index 0000000..7ed0199 --- /dev/null +++ b/src/vendorcode/google/chromeos/vpd_ssdt.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> +#include <drivers/vpd/vpd.h> + +#include <string.h> + +#include "vpd_ssdt.h" + +/* + * For multi-sourced components, we may decide to store the presence + * of one or the other in the VPD area. If that's the case, we can + * decide to only populate the ACPI SSDT table with the one that's + * actually in the device in question. In that case, we'll search + * the VPD tables to find a matching entry; if there is an entry + * with the appropriate tag, return true if the value matches, false + * otherwise. If there is no entry, then return true as well, meaning + * we don't know which component is being used, so the entry should be + * available in the SSDT and the kernel can probe for both. + */ +int vpd_should_generate_ssdt(const char *key, const char *value) +{ + const void *vpd_entry; + int size; + int keys_cmp; + + vpd_entry = vpd_find(key, &size, VPD_RO); + + /* If no entry was found, then generate an SSDT node */ + if (!vpd_entry) + return 1; + + /* If an entry was found, then compare values */ + keys_cmp = strncmp((char *)vpd_entry, value, size); + + if (keys_cmp == 0) + return 1; + else + return 0; +} diff --git a/src/vendorcode/google/chromeos/vpd_ssdt.h b/src/vendorcode/google/chromeos/vpd_ssdt.h new file mode 100644 index 0000000..37e887e --- /dev/null +++ b/src/vendorcode/google/chromeos/vpd_ssdt.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VPD_ACPI_H +#define VPD_ACPI_H + +int vpd_should_generate_ssdt(const char *key, const char *value); + +#endif /* VPD_ACPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0a9f96f3d3de9be36b218600268711b80c18b9 Gerrit-Change-Number: 32006 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: sb/intel/bd82x6x: Use system_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32497 Change subject: sb/intel/bd82x6x: Use system_reset() ...................................................................... sb/intel/bd82x6x: Use system_reset() Use already defined system_reset() function. Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_me.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32497/1 diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index edb514b..f82ed3e 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <device/pci_ops.h> +#include <cf9_reset.h> #include <console/console.h> #include <delay.h> #include <device/pci_def.h> @@ -179,8 +180,7 @@ reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); - outb(0x6, 0xcf9); - halt(); + system_reset(); } if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Gerrit-Change-Number: 32497 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: ich7/i945: Use do_system_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32378 Change subject: ich7/i945: Use do_system_reset() ...................................................................... ich7/i945: Use do_system_reset() Use already defined do_system_reset() function. Change-Id: Ieff4271c4a09d564d5f3415d8bc2c3843c8460f2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32378/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 0c92c4b..08a818c 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -15,6 +15,7 @@ #include <stdint.h> #include <stdlib.h> +#include <cf9_reset.h> #include <console/console.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -518,8 +519,7 @@ reg32 &= ~(7 << 0); reg32 |= (3 << 0); DMIBAR32(0x224) = reg32; - outb(0x06, 0xcf9); - halt(); /* wait for reset */ + do_system_reset(); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieff4271c4a09d564d5f3415d8bc2c3843c8460f2 Gerrit-Change-Number: 32378 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: src/mb: Use system_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32379 Change subject: src/mb: Use system_reset() ...................................................................... src/mb: Use system_reset() Use already defined system_reset() function. Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c 10 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32379/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index c524446..c056ac8f 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/intel/romstage.h> @@ -245,8 +246,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 6727f4a..e9af430 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -214,8 +215,7 @@ if (!s3resume && setup_sio_gpio(c_bsel)) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - outb(0xe, 0xcf9); - halt(); + system_reset(); } /* Enable SPD ROMs and DDR-II DRAM */ diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 8ce5979..42336f1 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -16,6 +16,7 @@ */ #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> @@ -191,8 +192,7 @@ if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - outb(0xe, 0xcf9); - halt(); + system_reset(); } sdram_initialize(boot_path, spd_addrmap); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 81669ed..d643b12 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -256,8 +257,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index a356195..7e3b7db 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <halt.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> @@ -218,8 +219,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 5100735..a7b35a4 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <halt.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> @@ -52,8 +53,7 @@ RCBA32(BUC) &= ~PCH_DISABLE_GBE; /* Datasheet says clearing the bit requires a reset after */ printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); - outb(0xe, 0xcf9); - halt(); + system_reset(); } #endif diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 05f9d1f..3d01eb1 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <halt.h> #include <arch/io.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> @@ -266,8 +267,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index be71cf4..ea207e8 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -195,8 +196,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 86d94a6..0d68fac 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -196,8 +197,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index efb376c..e85da1f 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -228,8 +229,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required -- To view, visit https://review.coreboot.org/c/coreboot/+/32379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806 Gerrit-Change-Number: 32379 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/pineview: Use system_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32496 Change subject: nb/intel/pineview: Use system_reset() ...................................................................... nb/intel/pineview: Use system_reset() Use already defined system_reset() function. Change-Id: I32c731de0c30940d15fd01fec6f10b3b33c04370 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/32496/1 diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 7714344..bdb685b 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <cf9_reset.h> #include <halt.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -113,8 +114,7 @@ if (!cbmem_was_initted && s3resume) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } romstage_handoff_init(s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/32496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32c731de0c30940d15fd01fec6f10b3b33c04370 Gerrit-Change-Number: 32496 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/nehalem: Use system_reset() and full_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32495 Change subject: nb/intel/nehalem: Use system_reset() and full_reset() ...................................................................... nb/intel/nehalem: Use system_reset() and full_reset() Use already defined system_reset() and full_reset() functions. Change-Id: Ib7e399b5186aa704d0388c4a4b18480f2e3799f3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32495/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 3164a58..5b6077f 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -22,6 +22,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cbmem.h> +#include <cf9_reset.h> #include <arch/cbfs.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> @@ -3681,8 +3682,7 @@ if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); MCHBAR8(0x2ca8) = 0; - outb(0x6, 0xcf9); - halt(); + system_reset(); } #if 0 if (!s3resume) { @@ -3907,8 +3907,7 @@ printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } } @@ -4346,8 +4345,7 @@ "Couldn't find training data. Rebooting\n"); reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - outb(0xe, 0xcf9); - halt(); + full_reset(); } int tm; info.training = *info.cached_training; @@ -4788,7 +4786,6 @@ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); /* Failed S3 resume, reset to come up cleanly */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e399b5186aa704d0388c4a4b18480f2e3799f3 Gerrit-Change-Number: 32495 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/haswell: Use system_reset()
by HAOUAS Elyes (Code Review) 29 Apr '19

29 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32494 Change subject: nb/intel/haswell: Use system_reset() ...................................................................... nb/intel/haswell: Use system_reset() Use already defined system_reset() function. Change-Id: I436f62c4402736fb74c59d8b359d0b3963f0e659 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32494/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index faaa9d0..fddada4 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> +#include <cf9_reset.h> #include <halt.h> #include <ip_checksum.h> #include <memory_info.h> @@ -136,8 +137,7 @@ post_code(POST_RESUME_FAILURE); printk(BIOS_DEBUG, "Giving up in sdram_initialize: " "No MRC data\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Pass console handler in pei_data */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I436f62c4402736fb74c59d8b359d0b3963f0e659 Gerrit-Change-Number: 32494 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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