Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31520 )
Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
......................................................................
Patch Set 9:
> Patch Set 9: Code-Review+2
>
> Does this change make no difference for the intel rvp boards?
We haven't yet configured any of display related pins for RVPs in gpio.c and using default settings. We will make changes as needed later.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31520 )
Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
......................................................................
Patch Set 9: Code-Review+2
Does this change make no difference for the intel rvp boards?
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Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32007
Change subject: Revert "UPSTREAM: ec/google/wilco: Enable software sync for VBOOT"
......................................................................
Revert "UPSTREAM: ec/google/wilco: Enable software sync for VBOOT"
This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165.
I was not ready to enable this option yet, until it is enabled
in depthcharge it needs to stay off in coreboot or depthcharge
will attempt to do software sync without a proper driver.
Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/ec/google/wilco/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32007/1
diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig
index f4a4111..4202c1d 100644
--- a/src/ec/google/wilco/Kconfig
+++ b/src/ec/google/wilco/Kconfig
@@ -3,7 +3,6 @@
default n
select EC_GOOGLE_COMMON_MEC
select EC_ACPI
- select VBOOT_EC_SOFTWARE_SYNC if VBOOT
help
Google Wilco Embedded Controller interface.
--
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Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32002
Change subject: mb/google/sarien: Add SKU for boards with signed EC
......................................................................
mb/google/sarien: Add SKU for boards with signed EC
To support both boards with the same firmware add a SKU for
each variant that is used to include the proper EC firmware
image to match what the EC is expecting.
BUG=b:119490232
TEST=tested by faking the EC response to ensure that the OS
and firmware update tools are able to determine the correct
model based on the value returned by the EC.
Change-Id: Iaa677975e0bccbee5ec8a39821fe1637f08270fa
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/mainboard/google/sarien/sku.c
M src/mainboard/google/sarien/variants/arcada/include/variant/variant.h
M src/mainboard/google/sarien/variants/sarien/include/variant/variant.h
3 files changed, 19 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/32002/1
diff --git a/src/mainboard/google/sarien/sku.c b/src/mainboard/google/sarien/sku.c
index 708793d..d0b48f0 100644
--- a/src/mainboard/google/sarien/sku.c
+++ b/src/mainboard/google/sarien/sku.c
@@ -14,15 +14,22 @@
*/
#include <boardid.h>
+#include <ec/google/wilco/commands.h>
#include <smbios.h>
#include <variant/variant.h>
uint32_t sku_id(void)
{
- return VARIANT_SKU_ID;
+ if (wilco_ec_signed_fw())
+ return VARIANT_SKU_ID_SIGNED_EC;
+ else
+ return VARIANT_SKU_ID;
}
const char *smbios_system_sku(void)
{
- return VARIANT_SKU_NAME;
+ if (wilco_ec_signed_fw())
+ return VARIANT_SKU_NAME_SIGNED_EC;
+ else
+ return VARIANT_SKU_NAME;
}
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h
index d128432..da1189e 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h
@@ -16,8 +16,10 @@
#ifndef VARIANT_H
#define VARIANT_H
-/* Arcada is SKU ID 2 */
-#define VARIANT_SKU_ID 2
-#define VARIANT_SKU_NAME "sku2"
+/* Arcada is SKU ID 2 and 4 */
+#define VARIANT_SKU_ID 2
+#define VARIANT_SKU_NAME "sku2"
+#define VARIANT_SKU_ID_SIGNED_EC 4
+#define VARIANT_SKU_NAME_SIGNED_EC "sku4"
#endif
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h
index d367505..bbb3e9e 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h
@@ -16,8 +16,10 @@
#ifndef VARIANT_H
#define VARIANT_H
-/* Sarien is SKU ID 1 */
-#define VARIANT_SKU_ID 1
-#define VARIANT_SKU_NAME "sku1"
+/* Sarien is SKU ID 1 and 3 */
+#define VARIANT_SKU_ID 1
+#define VARIANT_SKU_NAME "sku1"
+#define VARIANT_SKU_ID_SIGNED_EC 3
+#define VARIANT_SKU_NAME_SIGNED_EC "sku3"
#endif
--
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Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31887
Change subject: vboot: make vboot_working_data available to payload
......................................................................
vboot: make vboot_working_data available to payload
* Create a new cbtable entry called VBOOT_WD for storing a
pointer to the vboot vboot_working_data structure.
* Copy relevant parts of vboot_working_data struct to a new
libpayload header (libpayload/include/vboot.h).
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none
Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91
Signed-off-by: Joel Kitching <kitching(a)google.com>
---
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/sysinfo.h
A payloads/libpayload/include/vboot.h
M payloads/libpayload/libc/coreboot.c
M src/commonlib/include/commonlib/coreboot_tables.h
M src/lib/coreboot_table.c
M src/security/vboot/common.c
M src/security/vboot/misc.h
8 files changed, 98 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31887/1
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 1568526..4a31b4e 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -202,6 +202,7 @@
#define CB_TAG_VBNV 0x0019
#define CB_TAG_VBOOT_HANDOFF 0x0020
+#define CB_TAG_VBOOT_WD 0x0034
#define CB_TAG_DMA 0x0022
#define CB_TAG_RAM_OOPS 0x0023
#define CB_TAG_MTC 0x002b
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index 845b7c4..db5f7fd 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -40,6 +40,7 @@
#include <coreboot_tables.h>
+struct vboot_working_data;
struct cb_serial;
/*
@@ -97,6 +98,7 @@
void *vboot_handoff;
u32 vboot_handoff_size;
+ struct vboot_working_data *vboot_wd;
#if CONFIG(LP_ARCH_X86)
int x86_rom_var_mtrr_index;
diff --git a/payloads/libpayload/include/vboot.h b/payloads/libpayload/include/vboot.h
new file mode 100644
index 0000000..3004531
--- /dev/null
+++ b/payloads/libpayload/include/vboot.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __LIBPAYLOAD_VBOOT_H__
+#define __LIBPAYLOAD_VBOOT_H__
+
+#include <stdint.h>
+
+struct vboot_working_data {
+ uint32_t reserved0[2];
+ /* offset of the buffer from the start of this struct */
+ uint32_t buffer_offset;
+ uint32_t buffer_size;
+};
+
+#endif /* __LIBPAYLOAD_VBOOT_H__ */
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index ba5bb27..c59e70a 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -86,6 +86,13 @@
info->vboot_handoff_size = vbho->range_size;
}
+static void cb_parse_vboot_wd(unsigned char *ptr, struct sysinfo_t *info)
+{
+ struct lb_range *vbwd = (struct lb_range *)ptr;
+
+ info->vboot_wd = (void *)(uintptr_t)vbwd->range_start;
+}
+
static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
{
struct lb_range *vbnv = (struct lb_range *)ptr;
@@ -355,6 +362,9 @@
case CB_TAG_VBOOT_HANDOFF:
cb_parse_vboot_handoff(ptr, info);
break;
+ case CB_TAG_VBOOT_WD:
+ cb_parse_vboot_wd(ptr, info);
+ break;
case CB_TAG_MAC_ADDRS:
cb_parse_mac_addresses(ptr, info);
break;
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 6ca0f77..9b33522 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -292,6 +292,7 @@
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
+#define LB_TAB_VBOOT_WD 0x0034
#define LB_TAB_DMA 0x0022
#define LB_TAG_RAM_OOPS 0x0023
#define LB_TAG_MTC 0x002b
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 960ab0f..28f6713 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -43,6 +43,9 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
+#if CONFIG(VBOOT)
+#include <security/vboot/misc.h>
+#endif
static struct lb_header *lb_table_init(unsigned long addr)
{
@@ -223,8 +226,24 @@
vbho->range_start = (intptr_t)addr;
vbho->range_size = size;
}
+
+static void lb_vboot_wd(struct lb_header *header)
+{
+ struct lb_range *vbwd;
+ struct vboot_working_data *wd;
+
+ if ((wd = vboot_get_working_data()) == NULL)
+ return;
+
+ vbwd = (struct lb_range *)lb_new_record(header);
+ vbwd->tag = LB_TAB_VBOOT_WD;
+ vbwd->size = sizeof(*vbwd);
+ vbwd->range_start = (uintptr_t)wd;
+ vbwd->range_size = wd->buffer_offset + wd->buffer_size;
+}
#else
static inline void lb_vboot_handoff(struct lb_header *header) {}
+static inline void lb_vboot_wd(struct lb_header *header) {}
#endif /* CONFIG_VBOOT */
#endif /* CONFIG_CHROMEOS */
@@ -538,6 +557,9 @@
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
+
+ /* pass along the vboot working data address. */
+ lb_vboot_wd(head);
#endif
/* Add strapping IDs if available */
diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c
index 496ab78..21be031 100644
--- a/src/security/vboot/common.c
+++ b/src/security/vboot/common.c
@@ -25,24 +25,6 @@
#include <security/vboot/symbols.h>
#include <security/vboot/vboot_common.h>
-struct selected_region {
- uint32_t offset;
- uint32_t size;
-};
-
-/*
- * this is placed at the start of the vboot work buffer. selected_region is used
- * for the verstage to return the location of the selected slot. buffer is used
- * by the vboot2 core. Keep the struct CPU architecture agnostic as it crosses
- * stage boundaries.
- */
-struct vboot_working_data {
- struct selected_region selected_region;
- /* offset of the buffer from the start of this struct */
- uint32_t buffer_offset;
- uint32_t buffer_size;
-};
-
/* TODO(kitching): Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE instead. */
static size_t vboot_working_data_size(void)
{
@@ -56,7 +38,7 @@
die("impossible!");
}
-static struct vboot_working_data * const vboot_get_working_data(void)
+struct vboot_working_data * const vboot_get_working_data(void)
{
struct vboot_working_data *wd = NULL;
diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h
index 24e349d..27317ad 100644
--- a/src/security/vboot/misc.h
+++ b/src/security/vboot/misc.h
@@ -21,9 +21,28 @@
struct vb2_context;
struct vb2_shared_data;
+struct selected_region {
+ uint32_t offset;
+ uint32_t size;
+};
+
+/*
+ * this is placed at the start of the vboot work buffer. selected_region is used
+ * for the verstage to return the location of the selected slot. buffer is used
+ * by the vboot2 core. Keep the struct CPU architecture agnostic as it crosses
+ * stage boundaries.
+ */
+struct vboot_working_data {
+ struct selected_region selected_region;
+ /* offset of the buffer from the start of this struct */
+ uint32_t buffer_offset;
+ uint32_t buffer_size;
+};
+
/*
* Source: security/vboot/common.c
*/
+struct vboot_working_data * const vboot_get_working_data(void);
void vboot_init_work_context(struct vb2_context *ctx);
void vboot_finalize_work_context(struct vb2_context *ctx);
struct vb2_shared_data *vboot_get_shared_data(void);
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31930 )
Change subject: mb/*/chromeos.c: Be explicit about code for ramstage
......................................................................
Patch Set 1: Code-Review+2
> We currently define pci_config_read/writeX() differently for ramstage. I am working on to get rid of this __SIMPLE_DEVICE__ nuicance.
Oh okay... that's unfortunate. In that case wouldn't the cleanest thing be to use the same differentiator that the definition of those functions uses (i.e. #ifdef __SIMPLE_DEVICE__)? Although I guess that might make it harder if you want to get rid of those. I guess I don't really care.
You could still remove it from Beltino and Jecht, though, those don't seem to use those functions.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31930 )
Change subject: mb/*/chromeos.c: Be explicit about code for ramstage
......................................................................
Patch Set 1:
We currently define pci_config_read/writeX() differently for ramstage. I am working on to get rid of this __SIMPLE_DEVICE__ nuicance.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31930 )
Change subject: mb/*/chromeos.c: Be explicit about code for ramstage
......................................................................
Patch Set 1:
Can we just take the #ifs out completely? They look like they're just to reduce code size from back before we used --gc-sections. They shouldn't be necessary anymore.
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Gerrit-Comment-Date: Wed, 20 Mar 2019 22:14:19 +0000
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