coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: arch/ppc64: Add <arch/mmio.h> stubs
by Timothy Pearson (Code Review) 22 Mar '19

22 Mar '19

Timothy Pearson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31996 ) Change subject: arch/ppc64: Add <arch/mmio.h> stubs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdaa0995c8610dcc636923cc79b8455dfaeaa057 Gerrit-Change-Number: 31996 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2019 15:58:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/nvidia/tegra{124,210}: Use 'halt()' already defined in <halt.h>
by HAOUAS Elyes (Code Review) 22 Mar '19

22 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31979 Change subject: soc/nvidia/tegra{124,210}: Use 'halt()' already defined in <halt.h> ...................................................................... soc/nvidia/tegra{124,210}: Use 'halt()' already defined in <halt.h> This fix the error introduced in Change-Id: Ie7afe77 : tegra_lp0_resume.c:431:40: error: static declaration of 'halt' follows non-static declaration static __always_inline void __noreturn halt(void) ^~~~ In file included from tegra_lp0_resume.c:17: ../../../../include/halt.h:26:17: note: previous declaration of 'halt' was here void __noreturn halt(void); ^~~~ Change-Id: I3a67abb77846172597b8ebde779878b9aa2ff8d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31979/1 diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 4f219e4..f268ba1 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -264,11 +264,6 @@ /* Utility functions. */ -static __always_inline void __noreturn halt(void) -{ - for (;;); -} - static inline uint32_t read32(const void *addr) { return *(volatile uint32_t *)addr; diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index ddd1f4f..acfcd48 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -428,11 +428,6 @@ /* Utility functions. */ -static __always_inline void __noreturn halt(void) -{ - for (;;); -} - static inline uint32_t read32(const void *addr) { return *(volatile uint32_t *)addr; -- To view, visit https://review.coreboot.org/c/coreboot/+/31979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a67abb77846172597b8ebde779878b9aa2ff8d7 Gerrit-Change-Number: 31979 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [RFC] lib/spd_bin: Redesign API
by Philipp Deppenwiese (Code Review) 21 Mar '19

21 Mar '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29481 ) Change subject: [RFC] lib/spd_bin: Redesign API ...................................................................... Patch Set 2: Great idea, please add documentation -- To view, visit https://review.coreboot.org/c/coreboot/+/29481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Gerrit-Change-Number: 29481 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Thu, 21 Mar 2019 14:11:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/siemens/mc_apl1: use comment in Kconfig.name
by Thomas Heijligen (Code Review) 21 Mar '19

21 Mar '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31969 Change subject: mb/siemens/mc_apl1: use comment in Kconfig.name ...................................................................... mb/siemens/mc_apl1: use comment in Kconfig.name Change-Id: I3c8791a0ed7b3bc670cf1433fa58f9b3d68e0b97 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/mainboard/siemens/mc_apl1/Kconfig.name 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/31969/1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 3a5b6a3..cae6ac1 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -1,3 +1,5 @@ +comment "MC APLx" + config BOARD_SIEMENS_MC_APL1 bool "-> MC APL1" select BOARD_SIEMENS_BASEBOARD_MC_APL1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c8791a0ed7b3bc670cf1433fa58f9b3d68e0b97 Gerrit-Change-Number: 31969 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/seabios: Update stable from 1.12.0 to 1.12.1
by Paul Menzel (Code Review) 21 Mar '19

21 Mar '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31957 Change subject: payloads/seabios: Update stable from 1.12.0 to 1.12.1 ...................................................................... payloads/seabios: Update stable from 1.12.0 to 1.12.1 The two commits below were supplied to the stable branch. 1. 7d63249 tpm: Check for TPM related ACPI tables before attempting hw probe 2. a5cab58 (tag: rel-1.12.1, origin/1.12-stable) usb-ehci: Clear pipe token on pipe reallocate Change-Id: I7f1165d87950145e0538eac094c5bb9bfca4db3c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/external/SeaBIOS/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31957/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index e6df425..131c0d2 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.12.0" + bool "1.12.1" help Stable SeaBIOS version config SEABIOS_MASTER -- To view, visit https://review.coreboot.org/c/coreboot/+/31957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f1165d87950145e0538eac094c5bb9bfca4db3c Gerrit-Change-Number: 31957 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by build bot (Jenkins) (Code Review) 21 Mar '19

21 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 11: (15 comments) https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… File payloads/external/tint/generate_core.sh: https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 38: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 40: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 54: FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 64: import_from_file $buildgcc $corescript "# Find all the required tools" "# Allow" last_line_disabled || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 70: import_from_file $buildgcc $corescript "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 86: sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 95: # Insert prepare_${package} function call between the unpack and patch operations line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/generate_co… PS11, Line 99: sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… File payloads/external/tint/tintify_core.sh: https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 12: # <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 54: echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ]; then" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 55: echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 70: sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" $tintified line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 72: sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" $tintified line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 83: echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters https://review.coreboot.org/#/c/23856/11/payloads/external/tint/tintify_cor… PS11, Line 87: echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 11 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2019 11:16:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/*/chromeos.c: Be explicit about code for ramstage
by Kyösti Mälkki (Code Review) 21 Mar '19

21 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31930 ) Change subject: mb/*/chromeos.c: Be explicit about code for ramstage ...................................................................... mb/*/chromeos.c: Be explicit about code for ramstage Motivation is to reduce use of !__PRE_RAM__, it does not mean ENV_RAMSTAGE but we also exclude ENV_SMM with the change. Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31930 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 9 files changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index c6b0db2..dfa93a2 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -28,7 +28,7 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 4108e31..11b28cd 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -30,7 +30,7 @@ #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 05c8a3e..548470e 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -29,7 +29,7 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 6e6a4de..1420bf5 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -27,7 +27,7 @@ #include "ec.h" -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 6a4be31..d366e40 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -26,7 +26,7 @@ #include "ec.h" #include <ec/quanta/it8518/ec.h> -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #define GPIO_COUNT 7 diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 69e1050..1c62e5e 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -23,7 +23,7 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 24f8875..8c0aeea 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -23,7 +23,7 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index baa4094..0dba27a 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -31,7 +31,7 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __SIMPLE_DEVICE__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #include "ec.h" #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 85f9038..d055444 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -30,7 +30,7 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1 Gerrit-Change-Number: 31930 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Use standard pci_dev_set_subsystem function where possible
by Peter Lemenkov (Code Review) 21 Mar '19

21 Mar '19

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29195 ) Change subject: Use standard pci_dev_set_subsystem function where possible ...................................................................... Patch Set 2: > > Patch Set 2: > > > > Follow up in these commits: > > > > * I5fbed39ed448baf11f0e0786ce0ee94741d57237 > > * I91982597fdf586ab514bec3d8e4d09f2565fe56d > > * I954ee9cf8228c6352743cae968a0dd665865496c > > * Ia7a3eb2e29eb245c0e70abc23c2139aebc07cbfe > > * I2b1f46865aa380c2a31e05e55418b27296c72136 > > * Ie36a87314054d00daed6a63b495bd5f5eabef66e > > * I99b87004ea74a1ad0ec1d6e0c500df11dae4997c > > Sorry, I had not come across your work :( No problem - your approach is better reviewable and mergeable than mine (abandoned few months ago). https://www.youtube.com/watch?v=odiMeEhfi9I -- To view, visit https://review.coreboot.org/c/coreboot/+/29195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 Gerrit-Change-Number: 29195 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 21 Mar 2019 09:37:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Clear PMCON status bits
by Krishna P Bhat D (Code Review) 21 Mar '19

21 Mar '19

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 ) Change subject: soc/intel/cannonlake: Clear PMCON status bits ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c File src/soc/intel/cannonlake/pmutil.c: https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@1… PS3, Line 146: pmc_clear_suspwrflr > > Does FSP rely on these values? If yes, what for? Ideally I was thinking of doing this in pmc_init […] I looked at the FSP code, FSP is using these bits to determine bootmode in PreMem stage. PWR_FLR, GBL_RST_STS and HOST_RST_STS bits are cleared in FSP Post PCI enumeration. We can clear it in pmc_init(), but to be on safer side it would be good to do it in pch_finalize() as Rizwan suggested. -- To view, visit https://review.coreboot.org/c/coreboot/+/31902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Gerrit-Change-Number: 31902 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Mar 2019 07:14:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Enable Display ports
by Krishna P Bhat D (Code Review) 21 Mar '19

21 Mar '19

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31540 ) Change subject: mb/google/hatch: Enable Display ports ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/31540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e88905370256930270a87a66eede39de11818e Gerrit-Change-Number: 31540 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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coreboot-gerrit March 2019